F-Tile JESD204C Intel FPGA IP Dhizaini Example

Nezve F-Tile JESD204C Intel® FPGA IP Dhizaini Example User Guide

Iri bhuku remushandisi rinopa maitiro, nhungamiro yekushandisa, uye tsananguro yakadzama nezve dhizaini examples yeF-Tile JESD204C Intel® FPGA IP uchishandisa Intel Agilex™ zvishandiso.

Vateereri Vanotarisirwa

Gwaro iri rakaitirwa:

• Dhizaini mugadziri wekuita IP kusarudzwa panguva yedanho redhizaini dhizaini yekuronga chikamu
• Hardware vagadziri kana vachibatanidza iyo IP mune yavo system level dhizaini
• Validation mainjiniya panguva yezinga resimulation uye hardware yekusimbisa chikamu

Related Documents
Tafura inotevera inonyora mamwe magwaro ereferenzi ane hukama neF-Tile JESD204C Intel FPGA IP.

Tafura 1. Related Documents

Reference	Tsanangudzo
F-Tile JESD204C Intel FPGA IP User Guide	Inopa ruzivo nezve F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Intel FPGA IP Release Notes	Inonyora shanduko dzakaitwa yeF-Tile JESD204C F-Tile JESD204C mune imwe kuburitswa.
Intel Agilex Device Data Sheet	Ichi chinyorwa chinotsanangura maitiro emagetsi, kushandura maitiro, zvigadziriso zvekugadzirisa, uye nguva yeIntel Agilex madivayiri.

Acronyms uye Glossary

Tafura 2. Acronym List

Acronym	Kuwedzera
LEMC	Local Yakawedzerwa Multiblock Clock
FC	Frame clock rate
ADC	Analogi kune Digital Converter
DAC	Digital kune Analog Converter
DSP	Digital Signal processor
TX	Transmitter
RX	Receiver

Acronym	Kuwedzera
DLL	Data chinongedzo
CSR	Kudzora uye chimiro chekunyoresa
CRU	Clock uye Reset Unit
ISR	Kudzongonyedza Basa Routi
FIFO	Kutanga-Mu-Kutanga-Kubuda
SERDES	Serializer Deserializer
ECC	Kukanganisa Kugadzirisa Kodhi
FEC	Mberi Kukanganisa Kugadziriswa
SERR	Imwe Kanganiso Kuonekwa (muECC, inogadziriswa)
DERR	Kaviri Kukanganisa Kuona (muECC, inouraya)
PRBS	Pseudorandom binary sequence
MAC	Media Access Controller. MAC inosanganisira protocol sublayer, yekufambisa layer, uye data link layer.
PHY	Physical Layer. PHY inowanzo sanganisira iyo yemuviri layer, SERDES, vatyairi, vanogamuchira uye CDR.
PCS	Physical Coding Sub-layer
PMA	Physical Medium Attachment
RBD	RX Buffer Kunonoka
UI	Unit Interval = nguva yeserial bit
RBD kuverenga	RX Buffer Kunonoka ichangoburwa nzira kusvika
RBD inogadzirisa	RX Buffer Kunonoka kuburitsa mukana
SH	Batanidza musoro
TL	Chokufambisa dura
EMIB	Yakamisikidzwa Multi-die Interconnect Bridge

Tafura 3. Rondedzero Yemashoko

Term	Tsanangudzo
Converter Chishandiso	ADC kana DAC converter
Logic Device	FPGA kana ASIC
Octet	Boka remabhiti masere, rinoshanda sekuisa ku8/64 encoder uye kubuda kubva kudhikodha.
Nibble	Seti ye4 bits inova iyo base inoshanda unit yeJESD204C yakatarwa
Block	Chiratidzo che66-bit chinogadzirwa ne 64/66 encoding scheme
Line Rate	Inoshanda data mwero weserial link Lane Line Rate = (Mx Sx N'x 66/64 x FC) / L
Link Clock	Link Clock = Lane Line Rate/66.
Frame	Seti yeanoteedzana octets umo chinzvimbo che octet yega yega inogona kuzivikanwa nekutarisa kune furemu yekumisikidza chiratidzo.
Frame Clock	Wachi yehurongwa inomhanya nechiyero chefuremu, inofanira kunge iri 1x uye 2x yekubatanidza wachi.

Term	Tsanangudzo
Sampzvishoma pane furemu wachi	Sampzvishoma pawachi, huwandu sampLes mufuremu wachi yeinoshandura mudziyo.
LEMC	Wachi yemukati inoshandiswa kurongedza muganho weiyo yakawedzera multiblock pakati penzira uye mune ekunze mareferenzi (SYSREF kana Subclass 1).
Chidimbu 0	Hapana tsigiro ye deterministic latency. Iyo data inofanirwa kuburitswa nekukurumidza munzira yekuenda kune deskew pane inogamuchira.
Chidimbu 1	Deterministic latency uchishandisa SYSREF.
Multipoint Link	Inter-device inobatanidza ne 2 kana kupfuura inoshandura zvishandiso.
64B / 66B Encoding	Line kodhi iyo inomepu 64-bit data kune 66 bits kuita bhuroka. Iyo base level data chimiro chivharo chinotanga ne 2-bit sync musoro.

Tafura 4. Zviratidzo

Term	Tsanangudzo
L	Nhamba yemigwagwa pane chinoshandura mudziyo
M	Nhamba yevanoshandura pamudziyo
F	Nhamba ye octets pafuremu pane imwe nzira
S	Nhamba yesampLes transmitted per single converter per furemu kutenderera
N	Shanduro yekugadzirisa
N'	Nhamba yese yebhiti pa sample mune mushandisi data fomati
CS	Huwandu hwemabhiti ekudzora pashanduko sample
CF	Huwandu hwemazwi ekudzora panguva yewachi yenguva pane link
HD	High Density mushandisi data fomati
E	Nhamba yemultiblock mune yakawedzera multiblock

F-Tile JESD204C Intel FPGA IP Dhizaini Exampuye Quick Start Guide

Iyo F-Tile JESD204C Intel FPGA IP dhizaini examples yeIntel Agilex madivayiri anoratidza simulating testbench uye dhizaini yehardware inotsigira kuunganidza uye kuyedza Hardware.
Unogona kugadzira iyo F-Tile JESD204C dhizaini exampzvishoma kuburikidza neiyo IP catalog muIntel Quartus® Prime Pro Edition software.

Mufananidzo 1. Budiriro Stages yeDesign Example

Design Exampuye Block Diagram

Mufananidzo 2. F-Tile JESD204C Dhizaini Example High-level Block Diagram

Iyo yakagadzirwa exampLe ine ma modules anotevera:

• Platform Designer system
  • F-Tile JESD204C Intel FPGA IP
  • JTAG kuenda kuAvalon Master bridge
  • Parallel I/O (PIO) controller
  • Serial Port Interface (SPI)—master module— IOPLL
  • SYSREF jenareta
  • Example Dhizaini (ED) Kudzora CSR
  • Reset sequencers
• System PLL
• Muenzaniso jenareta
• Patani cheki

Tafura 5. Dhizaini Example modules

Zvikamu	Tsanangudzo
Platform Designer system	Iyo Platform Dhizaini system inosimbisa iyo F-Tile JESD204C IP data nzira uye inotsigira peripherals.
F-Tile JESD204C Intel FPGA IP	Iyi Platform Dhizaini subsystem ine iyo TX uye RX F-Tile JESD204C IPs yakasimbiswa pamwe neiyo duplex PHY.
JTAG kuenda kuAvalon Master bridge	Iri bhiriji rinopa system console host kuwana kune iyo memory-mamepu IP mudhizaini kuburikidza neJTAG interface.
Parallel I/O (PIO) controller	Uyu mutongi anopa memory-mapped interface ye sampling uye kutyaira zvakajairika chinangwa I/O ports.
SPI tenzi	Iyi module inobata serial yekuendesa data yekumisikidza kune SPI interface pane inoshandura magumo.
SYSREF jenareta	Iyo SYSREF jenareta inoshandisa wachi yekubatanidza sewachi yekunongedzera uye inogadzira SYSREF pulses yeF-Tile JESD204C IP. Cherechedza: Iyi dhizaini example inoshandisa SYSREF jenareta kuratidza iyo duplex F-Tile JESD204C IP link yekutanga. Mune F-Tile JESD204C subclass 1 system level application, unofanirwa kugadzira iyo SYSREF kubva kune imwechete sosi sewachi yemudziyo.
IOPLL	Iyi dhizaini example inoshandisa IOPLL kugadzira wachi yekufambisa data muF-Tile JESD204C IP.
ED Kudzora CSR	Iyi module inopa SYSREF yekuona kutonga uye chimiro, uye bvunzo maitiro ekutonga uye chimiro.
Reset sequencers	Iyi dhizaini example ine 2 reset sequencers: Reset Sequence 0-Inobata reset kuTX/RX Avalon® yekushambadzira domain, Avalon memory-mapped domain, core PLL, TX PHY, TX musimboti, uye SYSREF jenareta. Reset Sequence 1-Inobata iyo reset kuRX PHY uye RX musimboti.
System PLL	Yekutanga wachi sosi yeiyo F-tile yakaoma IP uye EMIB kuyambuka.
Muenzaniso jenareta	Iyo pateni jenareta inogadzira PRBS kana ramp muenzaniso.
Patani cheki	Iyo pateni cheki inosimbisa iyo PRBS kana ramp patani yakagamuchirwa, uye inomira chikanganiso kana ikawana kusawirirana kwedata sample.

Software Zvinodiwa

Intel inoshandisa inotevera software kuyedza dhizaini exampzvishoma muLinux system:

• Intel Quartus Prime Pro Edition software
• Questa*/ModelSim* kana VCS*/VCS MX simulator

Kugadzira Dhizaini

Kugadzira iyo dhizaini exampkubva ku IP parameter editor:

1. Gadzira purojekiti yakanangana neIntel Agilex F-tile mudziyo mhuri uye sarudza yaunoda mudziyo.
2. Mune IP Catalog, Zvishandiso ➤ IP Catalog, sarudza F-Tile JESD204C Intel FPGA IP.
3. Rondedzera zita repamusoro-level uye folda yeyako tsika IP musiyano. Dzvanya OK. Iyo parameter editor inowedzera yepamusoro-level .ip file kune purojekiti yazvino otomatiki. Kana ukakumbirwa kuti uwedzere nemaoko .ip file kuchirongwa, tinya Chirongwa ➤ Wedzera/ Bvisa Files muProjekti yekuwedzera iyo file.
4. Pasi peExample Dhizaini tab, tsanangura iyo dhizaini example paramita sekutsanangurwa kwazvinoitwa muKugadzira Example Parameters.
5. Dzvanya Gadzira Example Design.

Iyo software inogadzira zvese dhizaini files mune madiki-dhairekitori. Izvi files inodiwa kumhanyisa simulation uye kuunganidza.

Design Example Parameters
Iyo F-Tile JESD204C Intel FPGA IP parameter mupepeti inosanganisira iyo Example Dhizaini tab yekuti iwe utaure mamwe ma paramita usati wagadzira iyo dhizaini example.

Tafura 6. Parameters muExampuye Design Tab

Parameter	Options	Tsanangudzo
Sarudza Dhizaini	System Console Kudzora Hapana	Sarudza iyo system console control kuti uwane iyo dhizaini example data nzira kuburikidza neiyo system console.
Simulation	Vhura, Bvisa	Batidza iyo IP kuti igadzire zvinodiwa files yekutevedzera dhizaini example.
Synthesis	Vhura, Bvisa	Batidza iyo IP kuti igadzire zvinodiwa files yeIntel Quartus Prime kuunganidza uye hardware kuratidzira.
HDL format (yekuenzanisa)	Verilog VDHL	Sarudza iyo HDL fomati yeRTL files yekufananidza.
HDL format (ye synthesis)	Verilog chete	Sarudza iyo HDL fomati yeRTL files for synthesis.

Parameter	Options	Tsanangudzo
Gadzira 3- waya SPI module	Vhura, Bvisa	Batidza kugonesa 3-waya SPI interface pane 4-waya.
Sysref mode	Imwe-pfuti Periodic Gapped periodic	Sarudza kana iwe uchida kuti SYSREF kurongeka kuve imwe-kupfura pulse modhi, nguva nenguva, kana gapped periodic, zvichibva pane yako dhizaini zvinodiwa uye nguva inoshanduka. Imwe-pfuti-Sarudza iyi sarudzo kugonesa SYSREF kuve imwe-pfuti pulse modhi. The sysref_ctrl[17] register bit's value i0. Mushure meF-Tile JESD204C IP yagadzirisazve madhizi, shandura kukosha kwe sysref_ctrl[17] register kubva pa0 kuenda pa1, wozoenda ku0, kune imwe-pfuti SYSREF kupomba. Periodic-SYSREF mu periodic mode ine 50:50 basa kutenderera. SYSREF nguva iE*SYSREF_MULP. Gapped periodic-SYSREF ine programmable basa kutenderera kwe granularity ye1 link wachi kutenderera. SYSREF nguva iE*SYSREF_MULP. Kune yekunze-ye-ye-ye-ye-ye-duty cycle setting, iyo SYSREF yechizvarwa block inofanira kungoita 50:50 duty cycle. Tarisa kune SYSREF Jenareta chikamu kuti uwane rumwe ruzivo nezve SYSREF period.
Sarudza bhodhi	Hapana	Sarudza bhodhi rekugadzira example. Hapana-Iyi sarudzo haisanganisi zvinhu zvehardware zveiyo dhizaini example. Ese mapini anopihwa anozoiswa kune chaiwo mapini.
Test Pattern	PRBS-7 PRBS-9 PRBS-15 PRBS-23 Ramp	Sarudza pateni jenareta uye cheki bvunzo pateni. Muenzaniso Jenareta-JESD204C inotsigira PRBS patani jenareta pa data sample. Izvi zvinoreva kuti hupamhi hwe data iN + CS sarudzo. PRBS pateni jenareta uye cheki zvinobatsira pakugadzira data sample stimulus yekuyedza uye haienderane nePRBS test mode pane ADC/DAC converter. Ramp Patani Jenareta-JESD204C link layer inoshanda zvakajairwa asi chekufambisa gare gare chinovharwa uye mapindiro kubva kufomati anofuratirwa. Imwe neimwe nzira inofambisa yakafanana octet rukova iyo inowedzera kubva 0x00 kusvika 0xFF uye yozodzokorora. Ramp pattern test inogoneswa ne prbs_test_ctl. PRBS Pattern Checker-JESD204C PRBS scrambler inozviwiriranisa uye zvinotarisirwa kuti kana iyo IP musimboti yakwanisa kudhidha link kumusoro, mhodzi inokwenya inenge yatowiriraniswa. PRBS kukwenya mhodzi inotora 8 octets kuti uzvitange wega. Ramp Patani Cheki-JESD204C kukwenya kuri kuzviwiriranisa uye zvinotarisirwa kuti kana iyo IP musimboti yakwanisa kubatanidza kumusoro, mhodzi yekukwenya yatove yakawiriraniswa. Yekutanga octet inoshanda inotakurwa se ramp kukosha kwekutanga. Iyo inotevera data inofanirwa kuwedzera kusvika ku0xFF uye kukungurukira kusvika ku0x00. Ramp Pateni cheki inofanirwa kutarisa yakafanana patani mumigwagwa yese.
Bvisa mukati serial loopback	Vhura, Bvisa	Sarudza yemukati serial loopback.
Gonesa Command Channel	Vhura, Bvisa	Sarudza kuraira chiteshi patani.

Directory Structure
Iyo F-Tile JESD204C dhizaini example madhairekitori ane akagadzirwa files yekugadzira examples.

Mufananidzo 3. Dhairekitori Mamiriro eF-Tile JESD204C Intel Agilex Dhizaini Example

Tafura 7. Dhairekitori Files

Folders	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
simulation/mentor	modelim_sim.tcl tb_top_waveform.do
simulation/synopsy	vcs vcs_sim.sh tb_top_wave_ed.do vcsmx vcsmx_sim.sh tb_top_wave_ed.do

Kutevedzera Dhizaini Example Testbench

Iyo yakagadzirwa example testbench inotevedzera dhizaini yako yakagadzirwa.

Mufananidzo 4. Maitiro

Kutevedzera dhizaini, ita nhanho dzinotevera:

1. Chinja dhairekitori rekushanda kutiample_design_directory>/simulation/ .
2. Mumutsara wekuraira, mhanyisa script yekufananidza. Tafura iri pazasi inoratidza mirairo yekumhanyisa simulators inotsigirwa.

Simulator	Command
Questa/ModelSim	vsim -do modelim_sim.tcl
	vsim -c -do modelim_sim.tcl (isina Questa/ ModelSim GUI)
VCS	sh vcs_sim.sh
VCS MX	sh vcsmx_sim.sh

Kutevedzera kunopera nemeseji inoratidza kuti kumhanya kwakabudirira here kana kuti kwete.

Mufananidzo 5. Kubudirira Kutevedzera
Iyi nhamba inoratidza yakabudirira simulation meseji yeVCS simulator.

Kugadzira iyo Dhizaini Example

Kuunganidza iyo yekuunganidza-chete example project, tevera matanho aya:

1. Iva nechokwadi chekubatanidza dhizaini example generation yapera.
2. MuIntel Quartus Prime Pro Edition software, vhura iyo Intel Quartus Prime Pro Edition chirongwaample_ dhizaini_ dhairekitori>/ed/quartus.
3. Pane iyo Processing menyu, tinya Start Compilation.

Tsanangudzo Yakadzama yeF-Tile JESD204C Dhizaini Example

Iyo F-Tile JESD204C dhizaini example inoratidza mashandiro ekufambisa data uchishandisa loopback mode.
Iwe unogona kutsanangura iyo parameter marongero esarudzo yako uye kugadzira iyo dhizaini example.
Iyo yakagadzirwa example inowanikwa chete mune duplex modhi kune ese Base uye PHY musiyano. Iwe unogona kusarudza Base chete kana PHY chete mutsauko asi iyo IP yaizogadzira iyo dhizaini example yezvose Base uye PHY.

Cherechedza:  Mamwe magadzirirwo epamusoro data rate anogona kutadza kuita nguva. Kuti udzivise kutadza kuita nguva, funga kudoma yakaderera furemu wachi frequency multiplier (FCLK_MULP) kukosha mune Configurations tab yeF-Tile JESD204C Intel FPGA IP parameter mupepeti.

System Zvikamu

Iyo F-Tile JESD204C dhizaini example inopa software-based control flow inoshandisa iyo yakaoma control unit ine kana isina system console rutsigiro.

Iyo yakagadzirwa example inogonesa auto kubatanidza kumusoro mukati nekunze loopback modes.

JTAG kuenda kuAvalon Master Bridge
Iye JTAG kuAvalon Master Bridge inopa chinongedzo pakati peiyo host system kuti iwane ndangariro-mamepu F-Tile JESD204C IP uye yeperipheral IP kutonga uye chimiro marejista kuburikidza neJ.TAG interface.

Mufananidzo 6. Sistimu ine JTAG kuenda kuAvalon Master Bridge Core

Cherechedza:  System wachi inofanira kunge iri 2X nekukurumidza kupfuura JTAG wachi. Iyo system wachi ndeye mgmt_clk (100MHz) mune iyi dhizaini example.

Parallel I/O (PIO) Core
Iyo yakafanana yekupinza / kubuda (PIO) musimboti neAvalon interface inopa ndangariro-mamepu interface pakati peAvalon memory-mapped muranda port uye general chinangwa I/O ports. Iwo maI/O madoko anobatana kungave kune-chip mushandisi mantiki, kana kune I/O mapini anobatana nemidziyo yekunze kuFPGA.

Mufananidzo 7. PIO Core ine Input Ports, Output Ports, uye IRQ Tsigiro
Nekumisikidza, chikamu chePlatform Designer chinodzima iyo Interrupt Service Line (IRQ).

Iyo PIO I/O ports inopihwa padanho repamusoro HDL file (io_ chimiro chezviteshi zvekupinza, io_ control yezvinobuda ports).

Tafura iri pazasi inotsanangura kubatana kwechiratidzo chechimiro uye kutonga I/O ports kune DIP switch uye LED pane yekuvandudza kit.

Tafura 8. PIO Core I/O Ports

Port	Bit	Signal
Out_port	0	USER_LED SPI kuronga kwaitwa
	31:1	Reserved
In_port	0	USER_DIP yemukati serial loopback gonesa Off = 1 Pa = 0
	1	USER_DIP FPGA-yakagadzirwa SYSREF gonesa Off = 1 Pa = 0
	31:2	Reserved.

SPI Master
Iyo SPI master module ndeye yakajairwa Platform Dhizaini chikamu muIP Catalog standard raibhurari. Iyi module inoshandisa SPI protocol kufambisa kugadziridzwa kwevashanduri vekunze (yeexample, ADC, DAC, uye ekunze wachi jenareta) kuburikidza nenzvimbo yakarongeka yerejista mukati memidziyo iyi.

Iyo SPI tenzi ine Avalon memory-mapped interface inobatanidza kune Avalon tenzi (JTAG kuenda kuAvalon master bridge) kuburikidza neAvalon memory-mapped interconnect. Iyo SPI tenzi inogamuchira mirairo yekumisikidza kubva kuAvalon master.

Iyo SPI master module inodzora anosvika makumi matatu nemaviri akazvimirira SPI varanda. Iyo SCLK baud rate inogadziriswa kusvika 32 MHz (inoparadzaniswa ne20).
Iyi module yakagadziridzwa kune 4-waya, 24-bit hupamhi interface. Kana iyo Gadzira 3-Wire SPI Module sarudzo yasarudzwa, imwe moduru inosimbiswa kushandura iyo 4-waya kubuda kweSPI master kuita 3-waya.

IOPLL
Iyo IOPLL inogadzira wachi inodiwa kugadzira frame_clk uye link_clk. Chirevo chewachi kuPLL inogadziriswa asi inogumira kuchiyero che data / chinhu che33.

• For design example inotsigira chiyero che data che 24.33024 Gbps, chiyero chewachi che frame_clk uye link_clk i368.64 MHz.
• For design example inotsigira chiyero che data che 32 Gbps, chiyero chewachi che frame_clk uye link_clk i484.848 MHz.

SYSREF jenareta
SYSREF chiratidzo chakakosha chenguva yevanoshandura data neF-Tile JESD204C interface.

Iyo SYSREF jenareta mune dhizaini example inoshandiswa kune duplex JESD204C IP link yekutanga kuratidzira chinangwa chete. MuJESD204C subclass 1 system level application, iwe unofanirwa kugadzira SYSREF kubva kune imwechete sosi sewachi yemudziyo.

Kune F-Tile JESD204C IP, iyo SYSREF yekuwedzera (SYSREF_MULP) yeSYSREF control register inotsanangura nguva yeSYSREF, inova n-integer yakawanda yeE parameter.

Unofanira kuona E*SYSREF_MULP ≤16. For example, kana E=1, mitemo yeSYSREF_MULP inofanira kuva mukati me1–16, uye kana E=3, hurongwa hwemutemo hweSYSREF_MULP hunofanira kuva mukati me1–5.

Cherechedza:  Kana ukaseta kunze-kwe-renji SYSREF_MULP, jenareta reSYSREF rinogadzirisa marongero kuti SYSREF_MULP=1.
Unogona kusarudza kana uchida kuti SYSREF ive imwe-pfuti pulse, periodic, kana gapped periodic kuburikidza neEx.ample Dhizaini tebhu muF-Tile JESD204C Intel FPGA IP parameter mupepeti.

Tafura 9. Exampzvinyorwa zvePeriodic uye Gapped Periodic SYSREF Counter

E	SYSREF_MULP	SYSREF PERIOD (E*SYSREF_MULP* 32)	Duty Cycle	Tsanangudzo
1	1	32	1..31 (Zvinogoneka)	Gapped Periodic
1	1	32	16 (Yakagadziriswa)	Periodic
1	2	64	1..63 (Zvinogoneka)	Gapped Periodic
1	2	64	32 (Yakagadziriswa)	Periodic
1	16	512	1..511 (Zvinogoneka)	Gapped Periodic
1	16	512	256 (Yakagadziriswa)	Periodic
2	3	19	1..191 (Zvinogoneka)	Gapped Periodic
2	3	192	96 (Yakagadziriswa)	Periodic
2	8	512	1..511 (Zvinogoneka)	Gapped Periodic
2	8	512	256 (Yakagadziriswa)	Periodic
2	9 (Zvisiri pamutemo)	64	32 (Yakagadziriswa)	Gapped Periodic
2	9 (Zvisiri pamutemo)	64	32 (Yakagadziriswa)	Periodic

 

Tafura 10. SYSREF Control Registers
Iwe unokwanisa kugadzirisa zvakare marejista eSYSREF kana iyo rejista yekumisikidza yakasiyana pane iyo yawakatsanangura pawakagadzira dhizaini ex.ample. Gadzirisa marejista eSYSREF pamberi peF-Tile JESD204C Intel FPGA IP yapera. Kana ukasarudza yekunze SYSREF jenareta kuburikidza ne
sysref_ctrl[7] register zvishoma, unogona kufuratira marongero eSYSREF mhando, multiplier, duty cycle uye chikamu.

Bits	Default Value	Tsanangudzo
sysref_ctrl[1:0]	2'b00: One-pfuti 2'b01: Periodic 2'b10: Gapped periodic	SYSREF mhando. Iko kukosha kweiyo default kunoenderana neSYSREF modhi yekumisikidza mu Example Dhizaini tab muF-Tile JESD204C Intel FPGA IP parameter mupepeti.
sysref_ctrl[6:2]	5'b00001	SYSREF muwedzere. Iyi SYSREF_MULP ndima inoshanda kune periodic uye gapped-periodic SYSREF mhando. Unofanira kugadzirisa kukosha kwekuwandisa kuti uone kukosha kweE*SYSREF_MULP kuri pakati pe1 kusvika 16 F-Tile JESD204C IP isati yagadziriswa. Kana kukosha kweE*SYSREF_MULP kuri kunze kwechikamu ichi, kukosha kwekuwandisa kunoenda ku5'b00001.
sysref_ctrl[7]	Duplex datapath: 1'b1 Simplex TX kana RX datapath: 1'b0	SYSREF sarudza. Iko kukosha kweiyo default kunoenderana neiyo data nzira yekumisikidza muExample Dhizaini tebhu muF-Tile JESD204C Intel FPGA IP parameter mupepeti. 0: Simplex TX kana RX (Yekunze SYSREF) 1: Duplex (Yemukati SYSREF)
sysref_ctrl[16:8]	9'h0	SYSREF yebasa kutenderera kana SYSREF mhando iri periodic kana gapped periodic. Iwe unofanirwa kugadzirisa kutenderera kwebasa F-Tile JESD204C IP isati yapera. Maximum value = (E*SYSREF_MULP*32)-1 For example: 50% basa kutenderera = (E*SYSREF_MULP*32)/2 Basa rekutenderera rinokanganisa kusvika ku50% kana iwe ukasagadzirisa iyi rejista ndima, kana iwe ukagadzirisa nzvimbo yekunyoresa ku0 kana kupfuura iyo yakakosha kukosha inobvumidzwa.
sysref_ctrl[17]	1'b0	Manual control kana SYSREF mhando iri imwe-pfuti. Nyora 1 kuseta chiratidzo cheSYSREF kusvika kumusoro. Nyora 0 kuseta iyo SYSREF chiratidzo kune yakaderera. Iwe unofanirwa kunyora 1 ipapo 0 kugadzira SYSREF kupuruzira mune imwe-kupfura modhi.
sysref_ctrl[31:18]	22'h0	Reserved.

Reset Sequencers
Iyi dhizaini example rine maviri reset sequencers:

• Reset Sequence 0-Inobata iyo reset kuTX/RX Avalon yekushambadzira domain, Avalon memory-mapped domain, core PLL, TX PHY, TX musimboti, uye SYSREF jenareta.
• Reset Sequence 1-Inobata iyo reset kuRX PHY uye RX Core.

3-Waya SPI
Iyi module ndeyekusarudza kushandura SPI interface kuita 3-waya.

System PLL
F-tile ine matatu pane-bhodhi system PLLs. Aya masystem PLLs ndiwo ekutanga wachi sosi yeIP yakaoma (MAC, PCS, uye FEC) uye EMIB kuyambuka. Izvi zvinoreva kuti, paunoshandisa system PLL clocking mode, zvidhinha hazvina kuvharwa ne PMA wachi uye hazvinei newachi inobva kuFPGA musimboti. Imwe neimwe system PLL inongoburitsa wachi yakabatana neiyo frequency interface. For example, unoda maviri system PLLs kumhanya imwe interface pa1 GHz uye imwe interface pa500 MHz. Kushandisa system PLL inokutendera kuti ushandise nzira yega yega pasina shanduko yewachi inobata nzira yepedyo.
Imwe neimwe system PLL inogona kushandisa chero masere masere FGT mareferensi wachi. MaSystem PLL anogona kugovera wachi yekurevera kana kuve nemareferensi wachi. Imwe neimwe interface inogona kusarudza iyo system PLL yainoshandisa, asi, kana yasarudzwa, inogadziriswa, isingagadzirike zvakare uchishandisa ine simba reconfiguration.

Related Information
F-tile Architecture uye PMA uye FEC Yakananga PHY IP User Guide

Rumwe ruzivo nezve system PLL yekuvharisa modhi muIntel Agilex F-tile zvishandiso.

Muenzaniso jenareta uye Checker
Iyo pateni jenareta uye cheki inobatsira pakugadzira data samples uye monitoring yezvinangwa zvekuyedza.
Tafura 11. Inotsigirwa Patani Jenareta

Muenzaniso jenareta	Tsanangudzo
PRBS muenzaniso jenareta	Iyo F-Tile JESD204C dhizaini example PRBS pateni jenareta inotsigira iyo inotevera dhigirii yemapolynomials: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp muenzaniso jenareta	The ramp patani kukosha kwekuwedzera ne1 kune yega yega anotevera sample nejenareta hupamhi hweN, uye inokunguruka kuenda ku0 kana ese mabhiti musampiri 1. Gonesa iyo ramp pattern jenareta nekunyora 1 kusvika bit 2 yetst_ctl register yeED control block.
Raira chiteshi ramp muenzaniso jenareta	Iyo F-Tile JESD204C dhizaini example inotsigira command chiteshi ramp patani jenareta pamukoto. The ramp pateni kukosha kwekuwedzera ne1 pa6 bits emazwi ekuraira. Mbeu yekutanga inzira yekuwedzera panzira dzese.

Tafura 12. Inotsigirwa Patani Cheki

Pattern Checker	Tsanangudzo
PRBS pateni cheki	Mbeu inokwenya mucheki yekutarisisa inozviwiriranisa kana iyo F-Tile JESD204C IP ikawana kurongeka kwedeskew. Iyo pateni yekutarisa inoda 8 octets kuti mbeu inokwenya iwirirane.
Ramp pattern checker	Yekutanga data data sample yeshanduro yega yega (M) inoremerwa seyekutanga kukosha kweiyo ramp muenzaniso. Mashoko anotevera sampLes values ​​dzinofanira kuwedzera ne1 muwachi yega yega kusvika pakakwirira uye wobva wapfuura kuenda ku0.

Pattern Checker	Tsanangudzo
	For example, apo S=1, N=16 uye WIDTH_MULP = 2, hupamhi hwedhadha pashanduro imwe neimwe ndiS * WIDTH_MULP * N = 32. Iyo data yakawanda sampkukosha kwe 0xFFFF. The ramp pattern checker inosimbisa kuti mapatani akafanana anogamuchirwa kune ese maconverter.
Raira chiteshi ramp pattern checker	Iyo F-Tile JESD204C dhizaini example inotsigira command chiteshi ramp pattern checker. Izwi rekutanga rekuraira (6 bits) rakagamuchirwa rinotakurwa sekukosha kwekutanga. Mazwi ekuraira anotevera ari mugwara mumwechete anofanira kuwedzera kusvika pa0x3F uye achiumburuka kuenda ku0x00. Iyo yekuraira chiteshi ramp pattern checker inotarisa ramp maitiro mumigwagwa yese.

F-Tile JESD204C TX uye RX IP
Iyi dhizaini example inokubvumira kuti ugadzirise imwe neimwe TX/RX mune simplex mode kana duplex mode.
Duplex zvigadziriso zvinobvumira IP mashandiro ekuratidzira uchishandisa ingave yemukati kana yekunze serial loopback. MaCSR mukati meIP haana kugadziridzwa kure kuti abvumire IP kutonga uye chimiro chekutarisa.

F-Tile JESD204C Dhizaini Example Clock uye Reset

Iyo F-Tile JESD204C dhizaini example ine seti yewachi uye isazve masaini.

Tafura 13.Design Example Clocks

Clock Signal	Direction	Tsanangudzo
mgmt_clk	Input	LVDS yakasiyana wachi ine frequency ye100 MHz.
refclk_xcvr	Input	Transceiver reference wachi ine frequency ye data rate/factor of 33.
refclk_core	Input	Core referensi wachi ine frequency yakafanana neye refclk_xcvr.
mu_sysref	Input	SYSREF chiratidzo. Yakanyanya SYSREF frequency ndeye data rate/(66x32xE).
sysref_out	Output
txlink_clk rxlink_clk	Internal	TX uye RX yekubatanidza wachi ine frequency yedata reti/66.
txframe_clk rxframe_clk	Internal	TX uye RX furemu wachi ine frequency yedata reti/33 (FCLK_MULP=2) TX uye RX furemu wachi ine frequency yedata reti/66 (FCLK_MULP=1)
tx_fclk rx_fclk	Internal	TX uye RX chikamu wachi ine frequency yedata reti/66 (FCLK_MULP=2) TX neRX phase wachi inogara yakakwira (1'b1) kana FCLK_MULP=1
spi_SCLK	Output	SPI baud rate wachi ine frequency ye20 MHz.

Paunotakura dhizaini example mumudziyo weFPGA, chiitiko chemukati ninit_done chinovimbisa kuti JTAG kuAvalon Master bhiriji iri museti pamwe nemamwe mabhuroki ese.

Iyo SYSREF jenareta ine yakazvimirira reset yekubaya nemaune asynchronous hukama hweiyo txlink_clk uye rxlink_clk wachi. Iyi nzira yakawedzera kuteedzera chiratidzo cheSYSREF kubva kune yekunze wachi chip.

Tafura 14. Design Example Resets

Reset Signal	Direction	Tsanangudzo
global_rst_n	Input	Push bhatani reseti yepasi rose kune ese mabhuroko, kunze kweiyo JTAG kuenda kuAvalon Master bridge.
ninit_done	Internal	Kubuda kubva kuReset Release IP yeJTAG kuenda kuAvalon Master bridge.
edctl_rst_n	Internal	Iyo ED Control block inoiswa patsva naJTAG kuenda kuAvalon Master bridge. Iyo hw_rst uye global_rst_n ports haigadzirise ED Control block.
hw_rst	Internal	Assert uye dessert hw_rst nekunyorera kune rst_ctl rejista yeED Control block. mgmt_rst_in_n anosimbisa kana hw_rst ichinzi.
mgmt_rst_in_n	Internal	Reset yeAvalon memory-mapped interfaces eakasiyana IPs uye mapimendi ereset sequencers:  j20c_reconfig_reset yeF-Tile JESD204C IP duplex Native PHY spi_rst_n yeSPI master pio_rst_n yePIO chimiro uye kutonga reset_in0 port of reset sequencer 0 and 1 The global_rst_n, hw_rst, or edctl_rst_n port assserts setzve pa mgmt_rst_in_n.
sysref_rst_n	Internal	Reset yeSYSREF jenareta block muED Control block uchishandisa reset sequencer 0 reset_out2 port. Reset sequencer 0 reset_out2 port dhiasserts reset kana core PLL yakakiyiwa.
core_pll_rst	Internal	Inogadzirisa zvakare iyo yakakosha PLL kuburikidza neiyo reset sequencer 0 reset_out0 chiteshi. Iyo yakakosha PLL inogadziridza kana mgmt_rst_in_n reset yasimbiswa.
j204c_tx_avs_rst_n	Internal	Reset iyo F-Tile JESD204C TX Avalon memory- mapped interface kuburikidza nereset sequencer 0. Iyo TX Avalon memory-mapped interface inosimbisa kana mgmt_rst_in_n ichinzi.
j204c_rx_avs_rst_n	Internal	Reset iyo F-Tile JESD204C TX Avalon memory- mapped interface kuburikidza nereset sequencer 1. Iyo RX Avalon memory-mapped interface inosimbisa kana mgmt_rst_in_n ichinzi.
j204c_tx_rst_n	Internal	Inogadzirisa zvakare iyo F-Tile JESD204C TX link uye yekutakura maseru mu txlink_clk, uye txframe_clk, madomasi. Mutevedzeri wekugadzirisa 0 reset_out5 port reset j204c_tx_rst_n. Iyi reset desserts kana iyo yakakosha PLL yakakiyiwa, uye tx_pma_ready uye tx_ready masaini anosimbiswa.
j204c_rx_rst_n	Internal	Inogadzirisa zvakare iyo F-Tile JESD204C RX link uye yekutakura maseru mukati, rxlink_clk, uye rxframe_clk domains.

Reset Signal	Direction	Tsanangudzo
		Iyo yekuseta patsva sequencer 1 reset_out4 port reset j204c_rx_rst_n. Iyi reset desserts kana iyo yakakosha PLL yakakiyiwa, uye iyo rx_pma_ready uye rx_ready masaini anosimbiswa.
j204c_tx_rst_ack_n	Internal	Gadzirisa masaini ekubata maoko uchishandisa j204c_tx_rst_n.
j204c_rx_rst_ack_n	Internal	Gadzirisa masaini ekubata maoko ne j204c_rx_rst_n.

Mufananidzo 8. Nguva yedhizaini yedhizaini Example Resets

F-Tile JESD204C Dhizaini Example Signals

Tafura 15. System Interface Signals

Signal	Direction	Tsanangudzo
Wachi uye Resets
mgmt_clk	Input	100 MHz wachi yekutarisira system.
refclk_xcvr	Input	Reference wachi yeF-tile UX QUAD uye System PLL. Yakaenzana nechiyero che data / chinhu che33.
refclk_core	Input	Core PLL referensi wachi. Inoshandisa wachi yakafanana nerefclk_xcvr.
mu_sysref	Input	SYSREF chiratidzo kubva kunze SYSREF jenareta yeJESD204C Subclass 1 kuita.
sysref_out	Output	SYSREF chiratidzo cheJESD204C Subclass 1 kuitiswa inogadzirwa neFPGA mudziyo wekugadzira ex.ample link yekutanga chinangwa chete.

 

Signal	Direction	Tsanangudzo
SPI
spi_SS_n[2:0]	Output	Inoshanda yakaderera, SPI muranda sarudza chiratidzo.
spi_SCLK	Output	SPI serial wachi.
spi_sdio	Input/Output	Kuburitsa data kubva kuna tenzi kuenda kumuranda wekunze. Isa data kubva kumuranda wekunze kuenda kuna tenzi.

Signal	Direction	Tsanangudzo
Cherechedza:Kana Gadzira 3-Waya SPI Module sarudzo inogoneswa.
spi_MISO Cherechedza: Kana Gadzira 3-Waya SPI Module sarudzo haina kugoneswa.	Input	Isa data kubva kumuranda wekunze kune SPI tenzi.
spi_MOSI Cherechedza: Kana Gadzira 3-Waya SPI Module sarudzo haina kugoneswa.	Output	Kuburitsa data kubva kuSPI tenzi kuenda kumuranda wekunze.

 

Signal	Direction	Tsanangudzo
ADC / DAC
tx_serial_data[LINK*L-1:0]	Output	Yakasiyana yakakwira yekumhanyisa serial yakabuda data kuDAC. Wachi yakanyudzwa mune serial data stream.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]	Input	Yakasiyana yekumhanyisa serial yekuisa data kubva kuADC. Iyo wachi inodzoserwa kubva kune serial data stream.
rx_serial_data_n[LINK*L-1:0]

 

Signal	Direction	Tsanangudzo
General Chinangwa I/O
user_led[3:0]	Output	Inoratidza mamiriro ezvinotevera mamiriro: [0]: SPI chirongwa chaitwa [1]: TX link kukanganisa [2]: RX link kukanganisa [3]: Patani yekutarisa kukanganisa kweAvalon yekufambisa data
user_dip[3:0]	Input	Mushandisi modhi yeDIP switch yekupinda: [0]: Yemukati serial loopback gonesa [1]: FPGA-yakagadzirwa SYSREF gonesa [3:2]: Zvakachengetwa

 

Signal	Direction	Tsanangudzo
Kunze-kwe-bhendi (OOB) uye Chimiro
rx_patchk_data_error[LINK-1:0]	Output	Kana chiratidzo ichi chataurwa, chinoratidza kuti pateni cheki chaona kukanganisa.
rx_link_error[LINK-1:0]	Output	Kana ichi chiratidzo chikasimbiswa, chinoratidza JESD204C RX IP yati kuvhiringidza.
tx_link_error[LINK-1:0]	Output	Kana chiratidzo ichi chasimbiswa, chinoratidza JESD204C TX IP yati kuvhiringidza.
emb_lock_out	Output	Kana chiratidzo ichi chasimbiswa, chinoratidza JESD204C RX IP yawana EMB kukiya.
sh_lock_out	Output	Kana chiratidzo ichi chasimbiswa, chinoratidza JESD204C RX IP sync musoro wakavharwa.

 

Signal	Direction	Tsanangudzo
Avalon Streaming
rx_avst_valid[LINK-1:0]	Input	Inoratidza kana shanduri sample data kune iyo application layer inoshanda kana kuti haina basa. 0: Data haina basa 1: Data ndeyechokwadi
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Input	Converter sample data kune iyo application layer.

F-Tile JESD204C Dhizaini Example Control Registers

Iyo F-Tile JESD204C dhizaini example marejista muED Control block shandisa byte-addressing (32 bits).

Tafura 16. Design Example Address Map
Aya 32-bit ED Control block marejista ari mumgmt_clk domain.

Chikamu	Kero
F-Tile JESD204C TX IP	0x000C_0000 – 0x000C_03FF
F-Tile JESD204C RX IP	0x000D_0000 – 0x000D_03FF
SPI Kudzora	0x0102_0000 – 0x0102_001F
PIO Control	0x0102_0020 – 0x0102_002F
PIO Status	0x0102_0040 – 0x0102_004F
Reset Sequencer 0	0x0102_0100 – 0x0102_01FF
Reset Sequencer 1	0x0102_0200 – 0x0102_02FF
ED Kudzora	0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Tafura 17. Nyoresa Access Type uye Tsanangudzo
Iyi tafura inotsanangura regisheni yekuwana mhando yeIntel FPGA IPs.

Access Type	Tsanangudzo
RO/V	Software kuverenga-chete (hapana mhedzisiro pakunyora). Kukosha kunogona kusiyana.
RW	Software inoverenga uye inodzorera ikozvino bit kukosha. Software inonyora uye inoisa chidimbu kune yaunoda kukosha.
RW1C	Software inoverenga uye inodzorera ikozvino bit kukosha. Software inonyora 0 uye haina mhedzisiro. Software inonyora 1 uye inobvisa zvishoma kusvika ku0 kana bhiti rakaiswa ku1 nehardware. Hardware inoisa iyo bit ku1. Software clear ine yepamusoro pekutanga pane Hardware set.

Tafura 18. ED Kudzora Kero Mepu

Offset	Register Zita
0x00	rst_ctl
0x04	kutanga_sts0
akaenderera…

Offset	Register Zita
0x10	rst_sts_detected0
0x40	sysref_ctl
0x44	sysref_sts
0x80	tst_ctl
0x8c	tst_err0

Tafura 19. ED Control Block Control uye Status Registers

Byte Offset	Register	Zita	Access	Reset	Tsanangudzo
0x00	rst_ctl	rst_assert	RW	0x0	Reset control. [0]: Nyora 1 kuratidza kuseta patsva. (hw_rst) Nyora 0 zvakare kuti deassert reset. [31:1]: Zvakachengetwa.
0x04	kutanga_sts0	rst_status	RO/V	0x0	Reset status. [0]: Core PLL yakavharwa chimiro. [31:1]: Zvakachengetwa.
0x10	rst_sts_dete cted0	rst_sts_set	RW1C	0x0	SYSREF kumucheto kwekuona mamiriro emukati kana ekunze SYSREF jenareta. [0]: Kukosha kwe1 Kunoratidza SYSREF inokwira mupendero inoonekwa kune subclass 1 kushanda. Software inogona kunyora 1 kujekesa iyi bhiti kugonesa SYSREF nyowani yekuonekwa. [31:1]: Zvakachengetwa.
0x40	sysref_ctl	sysref_contr ol	RW	Duplex datapath Imwe-pfuti: 0x00080	SYSREF kutonga. Tarisa kune Tafura 10 papeji 17 kuti uwane rumwe ruzivo nezve mashandisirwo erejista iyi.
				Nguva:	Cherechedza: Iko kukosha kwekugadzirisa kunoenderana
				0x00081	iyo SYSREF mhando uye F-Tile
				Gapped- periodic:	JESD204C IP data nzira parameter marongero.
				0x00082
				TX kana RX data
				nzira
				Imwe-pfuti:
				0x00000
				Nguva:
				0x00001
				Yakaganhurwa-
				periodic:
				0x00002
0x44	sysref_sts	sysref_statu s	RO/V	0x0	SYSREF chimiro. Iri rejista rine yazvino SYSREF nguva uye yebasa kutenderera marongero emukati SYSREF jenareta. Tarisa kune Tafura 9 papeji 16 yemutengo wepamutemo weSYSREF nguva uye kutenderera kwebasa.
akaenderera…

Byte Offset	Register	Zita	Access	Reset	Tsanangudzo
					[8:0]: SYSREF nguva. Kana kukosha kuri 0xFF, iyo SYSREF nguva = 255 Kana kukosha kana 0x00, iyo SYSREF nguva = 256. [17: 9]: SYSREF basa rekutenderera. [31:18]: Zvakachengetwa.
0x80	tst_ctl	tst_control	RW	0x0	Test control. Shandisa rejista iyi kugonesa akasiyana bvunzo mapatani epateni jenareta uye cheki. [1:0] = Munda wakachengetwa [2] = ramp_test_ctl 1'b0 = Inogonesa PRBS pateni jenareta uye cheki 1'b1 = Inogonesa ramp muenzaniso jenareta uye cheki [31:3]: Zvakachengetwa.
0x8c	tst_err0	tst_error	RW1C	0x0	Chikanganiso mureza weLinganiso 0. Kana iyo bit iri 1'b1, inoratidza kukanganisa kwaitika. Iwe unofanirwa kugadzirisa chikanganiso usati wanyora 1'b1 kune iyo yakatarisana bit kuti ubvise mureza wekukanganisa. [0] = Patani yekutarisa kukanganisa [1] = tx_link_error [2] = rx_link_error [3] = Command pattern checker error [31:4]: Yakachengetwa.

Gwaro Rekudzokorora Nhoroondo yeF-Tile JESD204C Intel FPGA IP Dhizaini Example User Guide

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2021.10.11	21.3	1.0.0	Kusunungurwa kwekutanga.

Zvinyorwa / Zvishandiso

intel F-Tile JESD204C Intel FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi F-Tile JESD204C Intel FPGA IP Dhizaini Example, F-Tile JESD204C, Intel FPGA IP Dhizaini Example, IP Dhizaini Example, Dhizaini Example

References

• User Manual