DisplayPort Agilex F-Tile FPGA IP Tsim Example
Cov neeg siv phau ntawv qhia
Hloov tshiab rau Intel® Quartus® Prime Design Suite: 21.4
Tus IP Version: 21.0.0

DisplayPort Intel FPGA IP Tsim Example Quick Start Guide

Lub DisplayPort Intel® FPGA IP tsim examples rau Intel Agilex™ F-tile li muaj qhov simulating testbench thiab kho vajtse tsim uas txhawb kev muab tso ua ke thiab kuaj kho vajtse.
Lub DisplayPort Intel FPGA IP muaj cov qauv hauv qab no examples:

• DisplayPort SST parallel loopback tsis muaj Pixel Clock Recovery (PCR) module ntawm tus nqi zoo li qub

Thaum koj tsim ib tug tsim example, parameter editor cia li tsim cov files yuav tsum simulate, compile, thiab sim tus tsim nyob rau hauv hardware.
Nco tseg: Intel Quartus® Prime 21.4 software version tsuas yog txhawb nqa Preliminary Design Example rau Simulation, Synthesis, Compilation, and Timing analysis purposes. Hardware functionality tsis tau lees paub tag nrho.
Daim duab 1. Kev Txhim Kho Stages

Cov ntaub ntawv ntsig txog

• DisplayPort Intel FPGA IP Tus Neeg Siv Qhia
• Hloov mus rau Intel Quartus Prime Pro Edition

1.1. Directory Structure
Daim duab 2. Daim Ntawv Teev Npe

Table 1. Tsim Exampcov Components

Cov ntaub ntawv	Files
rtl/cov	dp_core.ip ib
	dp_rx.ip ib
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX lub tsev thaiv)
	dp_rx_data_fifo.ip ib
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX lub tsev thaiv)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Hardware thiab Software Requirements
Intel siv cov cuab yeej thiab software hauv qab no los kuaj tus qauv tsim example:
Kho vajtse

• Intel Agilex I-Series Development Kit

Software

• Intel Quartus Prime
• Synopsys* VCL Simulator

1.3. Tsim tus Tsim
Siv DisplayPort Intel FPGA IP parameter editor hauv Intel Quartus Prime software los tsim cov qauv tsim example.
Daim duab 3. Tsim cov qauv tsim

1. Xaiv Cov Cuab Yeej ➤ IP Catalog, thiab xaiv Intel Agilex F-tile ua lub hom phiaj ntaus tsev neeg.
   Nco tseg: Tus tsim example tsuas txhawb Intel Agilex F-tile li.
2. Hauv IP Catalog, nrhiav thiab nyem ob npaug rau DisplayPort Intel FPGA IP. Lub qhov rais tshiab IP Variation tshwm.
3. Qhia meej lub npe saum toj kawg nkaus rau koj qhov kev hloov pauv IP. Tus parameter editor txuag tus IP variation nqis hauv a file npe .ip ib.
4. Koj tuaj yeem xaiv ib qho tshwj xeeb Intel Agilex F-tile ntaus ntawv hauv Cov Ntaus Ntaus, lossis khaws lub neej ntawd Intel Quartus Prime software xaiv khoom siv.
5. Nyem OK. Cov parameter editor tshwm.
6. Configure cov yam tsis xav tau rau ob qho tib si TX thiab RX
7. Hauv Design Exampnyob rau hauv tab, xaiv DisplayPort SST Parallel Loopback Tsis muaj PCR.
8. Xaiv Simulation los tsim cov testbench, thiab xaiv Synthesis los tsim kho vajtse tsim example. Koj yuav tsum xaiv yam tsawg kawg ib qho ntawm cov kev xaiv no los tsim cov qauv tsim example files. Yog tias koj xaiv ob qho tib si, lub sijhawm tiam yuav ntev dua.
9. Nyem Tsim Example Design.

1.4. Simulating Tus Tsim
Lub DisplayPort Intel FPGA IP tsim example testbench simulates ib tug serial loopback tsim los ntawm ib tug TX piv txwv mus rau ib tug RX piv txwv. Ib qho kev yees duab sab hauv lub tshuab hluav taws xob module tsav lub DisplayPort TX piv txwv thiab RX piv txwv video tso tawm txuas mus rau CRC checkers hauv testbench.
Daim duab 4. Tsim Simulation Flow

1. Mus rau Synopsys simulator folder thiab xaiv VCS.
2. Khiav simulation tsab ntawv.
   Qhov chaw vcs_sim.sh
3. Cov ntawv ua haujlwm Quartus TLG, suav nrog thiab khiav lub testbench hauv lub simulator.
4. Txheeb xyuas qhov tshwm sim.
   Qhov kev sim ua tiav xaus nrog qhov sib piv ntawm Qhov Chaw thiab Sink SRC.

1.5. Compiling thiab Simulating tus tsim
Daim duab 5. Compiling thiab Simulating tus tsim

Txhawm rau sau thiab khiav qhov kev sim ua qauv qhia ntawm lub hardware example design, ua raws li cov kauj ruam no:

1. Xyuas kom hardware example tsim tiam ua tiav.
2. Tua tawm Intel Quartus Prime Pro Edition software thiab qhib /quartus/agi_dp_demo.qpf.
3. Nyem Ua Haujlwm ➤ Pib Sau.
4. Tos kom txog thaum Compilation tiav.

Nco tseg: Design example tsis ua haujlwm kom paub tseeb Preliminary Design Example ntawm hardware nyob rau hauv no tso tawm Quartus.
Cov ntaub ntawv ntsig txog
Intel Agilex I-Series FPGA Cov Khoom Siv Txhim Kho Cov Neeg Siv

1.6. DisplayPort Intel FPGA IP Tsim Example Parameters
Table 2. DisplayPort Intel FPGA IP Tsim Example Parameters rau Intel Agilex F-tile Device

Parameter	Tus nqi	Kev piav qhia
Muaj Tsim Example
Xaiv Tsim	• Tsis muaj • DisplayPort SST Parallel Loopback tsis muaj PCR	Xaiv tus tsim example yuav generated. • Tsis muaj: Tsis muaj qauv example yog muaj rau kev xaiv parameter tam sim no • DisplayPort SST Parallel Loopback tsis muaj PCR: Qhov no tsim example ua kom pom qhov sib npaug ntawm qhov sib npaug ntawm DisplayPort dab dej rau DisplayPort qhov tsis muaj Pixel Clock Recovery (PCR) module thaum koj qhib rau Pab Pawg Video Input Image Port parameter.
Tsim Example Files
Kev simulation	Rau, Tawm	Qhib qhov kev xaiv no los tsim qhov tsim nyog files rau lub simulation testbench.
Synthesis	Rau, Tawm	Qhib qhov kev xaiv no los tsim qhov tsim nyog files rau Intel Quartus Prime muab tso ua ke thiab kho vajtse tsim.
Tsim HDL hom ntawv
Tsim File Hom ntawv	Verilog, VHDL	Xaiv qhov koj nyiam HDL hom rau cov tsim tsim example fileteeb. Nco tseg: Qhov kev xaiv no tsuas yog txiav txim siab hom ntawv rau qhov tsim tawm sab saum toj IP files. Tag nrho lwm yam files (egample testbenches thiab sab saum toj theem files rau hardware demonstration) yog nyob rau hauv Verilog HDL hom.
Target Development Kit
Xaiv Board	• Tsis Muaj Cov Khoom Siv Txhim Kho • Intel Agilex I-Series Cov khoom siv txhim kho	Xaiv lub rooj tsavxwm rau lub hom phiaj tsim example. • Tsis Muaj Cov Khoom Siv Txhim Kho: Qhov kev xaiv no tsis suav nrog txhua yam khoom siv kho vajtse rau tus qauv tsim example. Tus IP core teeb tsa txhua tus pin txoj haujlwm rau tus pins virtual. • Intel Agilex I-Series FPGA Development Kit: Qhov kev xaiv no cia li xaiv qhov project lub hom phiaj ntaus ntawv kom phim cov cuab yeej ntawm cov khoom siv txhim kho no. Koj tuaj yeem hloov lub hom phiaj ntaus ntawv siv qhov Hloov Lub Hom Phiaj Ntaus Parameter yog tias koj lub rooj tsav xwm kho dua tshiab muaj qhov sib txawv ntawm cov cuab yeej sib txawv. IP tub ntxhais teeb tsa tag nrho cov haujlwm pin raws li cov khoom siv txhim kho. Nco tseg: Kev tsim qauv ua ntej Example tsis tau txheeb xyuas qhov ua tau zoo ntawm cov khoom siv hauv qhov kev tso tawm Quartus no. • Custom Development Kit: Qhov kev xaiv no tso cai rau tus tsim example yuav tsum tau sim ntawm cov khoom siv txhim kho thib peb nrog Intel FPGA. Tej zaum koj yuav tau teeb tsa tus pin txoj haujlwm ntawm koj tus kheej.
	Lub Hom Phiaj
Hloov Lub Hom Phiaj Ntaus	Rau, Tawm	Qhib qhov kev xaiv no thiab xaiv cov khoom siv uas nyiam tshaj plaws rau cov khoom siv txhim kho.

Parallel Loopback Design Examples

Lub DisplayPort Intel FPGA IP tsim examples ua kom pom qhov sib npaug ntawm kev rov qab los ntawm DisplayPort RX piv txwv rau DisplayPort TX piv txwv yam tsis muaj Pixel Clock Recovery (PCR) module ntawm tus nqi zoo li qub.
Table 3. DisplayPort Intel FPGA IP Tsim Example rau Intel Agilex F-tile Device

Tsim Example	Lub npe	Cov ntaub ntawv tus nqi	Channel hom	Loopback Hom
DisplayPort SST parallel loopback tsis muaj PCR	DisplayPort SST	HBR3	Simplex	Parallel tsis muaj PCR

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Tsim Nta
SST parallel loopback tsim examples ua qauv qhia kev sib kis ntawm ib qho kwj video los ntawm DisplayPort dab dej rau DisplayPort qhov tsis muaj Pixel Clock Recovery (PCR) ntawm tus nqi zoo li qub.

Daim duab 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback tsis muaj PCR

• Hauv qhov hloov pauv no, DisplayPort qhov chaw tsis muaj, TX_SUPPORT_IM_ENABLE, tau qhib thiab siv cov duab yees duab interface.
• Lub DisplayPort dab dej tau txais cov yeeb yaj kiab thiab cov suab tawm los ntawm cov yeeb yaj kiab sab nraud xws li GPU thiab txiav txim siab nws mus rau qhov sib txuas video.
• Lub DisplayPort dab dej tso tawm video ncaj qha tsav lub DisplayPort qhov chaw video interface thiab encodes rau DisplayPort lub ntsiab txuas ua ntej xa mus rau tus saib.
• Lub IOPLL tsav ob qho tib si DisplayPort dab dej thiab qhov chaw video moos ntawm lub sijhawm ruaj khov.
• Yog tias DisplayPort dab dej thiab qhov chaw MAX_LINK_RATE parameter tau teeb tsa rau HBR3 thiab PIXELS_PER_CLOCK tau teeb tsa rau Quad, lub moos video khiav ntawm 300 MHz los txhawb 8Kp30 pixel tus nqi (1188/4 = 297 MHz).

2.2. Clocking Scheme
Lub tswv yim clocking qhia txog lub moos domains hauv DisplayPort Intel FPGA IP tsim example.
Daim duab 7. Intel Agilex F-tile DisplayPort Transceiver clocking scheme

Table 4. Clocking Scheme Signals

Lub moos hauv daim duab	Kev piav qhia
SysPLL refclk	F-tile System PLL siv moos uas tuaj yeem yog txhua lub moos zaus uas faib tau los ntawm System PLL rau qhov tso zis ntau zaus. Nyob rau hauv no tsim example, system_pll_clk_link thiab rx/tx refclk_link yog sib koom tib yam SysPLL refclk uas yog 150Mhz. Nws yuav tsum yog lub moos ua haujlwm pub dawb uas txuas nrog los ntawm lub siab transceiver siv moos tus pin mus rau lub moos input chaw nres nkoj ntawm Kev Siv thiab System PLL Clocks IP, ua ntej txuas cov khoom siv sib txuas rau DisplayPort Phy Top.
system_pll_clk_link	Qhov tsawg kawg nkaus System PLL tso zis zaus los txhawb txhua qhov DisplayPort tus nqi yog 320Mhz. Qhov no tsim example siv 900 Mhz (siab tshaj) tso zis zaus kom SysPLL refclk tuaj yeem koom nrog rx/tx refclk_link uas yog 150 Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	Rx CDR thiab Tx PLL Link refclk uas kho rau 150 Mhz los txhawb tag nrho DisplayPort cov ntaub ntawv tus nqi.
rx_ls_clkout/tx is clkout	DisplayPort Txuas Ceev Clock rau moos DisplayPort IP core. Ntau zaus sib npaug rau Cov Ntaub Ntawv Rate faib los ntawm cov ntaub ntawv sib luag. Example: Zaus = data rate/data width = 8.1G (HBR3) / 40bits = 202.5 Mhz

2.3. Simulation Testbench
Lub simulation testbench simulates DisplayPort TX serial loopback rau RX.
Daim duab 8. DisplayPort Intel FPGA IP Simplex Hom Simulation Testbench Block Diagram

Table 5. Testbench Cheebtsam

Cheebtsam	Kev piav qhia
Video Qauv Generator	Lub tshuab hluav taws xob no tsim cov xim bar qauv uas koj tuaj yeem teeb tsa. Koj muaj peev xwm parameterize lub video hom sij hawm.
Testbench tswj	Qhov thaiv no tswj cov kev sim ua ntu zus ntawm qhov simulation thiab tsim cov cim tsim nyog rau TX core. Lub testbench tswj thaiv kuj tseem nyeem CRC tus nqi los ntawm ob qho tib si thiab dab dej los ua kev sib piv.
RX Link Speed ​​Clock Frequency Checker	Tus checker no txheeb xyuas yog tias RX transceiver rov qab tau lub moos zaus sib xws li cov ntaub ntawv xav tau.
TX Link Speed ​​Clock Frequency Checker	Tus neeg kuaj xyuas no txheeb xyuas yog tias TX transceiver rov qab tau lub moos zaus sib xws li cov ntaub ntawv xav tau.

Lub simulation testbench ua cov ntawv pov thawj hauv qab no:
Table 6. Testbench Verifications

Kev ntsuas ntsuas	Kev pov thawj
• Txuas Kev Kawm ntawm Cov Ntaub Ntawv Tus Nqi HBR3 • Nyeem DPCD cov ntawv sau npe los xyuas seb DP Status teeb tsa thiab ntsuas qhov zaus ntawm TX thiab RX Link Ceev.	Integrate Frequency Checker los ntsuas qhov Link Speed ​​clock's zaus tso zis los ntawm TX thiab RX transceiver.
• Khiav video qauv ntawm TX rau RX. • Tshawb xyuas CRC rau ob qho tib si qhov chaw thiab lub dab dej los xyuas seb lawv puas sib haum	• Txuas lub tshuab hluav taws xob video qauv rau DisplayPort Source los tsim cov qauv video. • Testbench tswj tom ntej no nyeem tawm ob qho tib si Source thiab Sink CRC los ntawm DPTX thiab DPRX sau npe thiab sib piv kom ntseeg tau tias CRC qhov tseem ceeb zoo ib yam. Nco tseg: Txhawm rau kom paub tseeb tias CRC raug xam, koj yuav tsum ua kom muaj kev txhawb nqa CTS qhov ntsuas qhov ntsuas automation parameter.

Cov ntaub ntawv kho dua tshiab rau DisplayPort Intel

Agilex F-tile FPGA IP Tsim Example User Guide

Cov ntaub ntawv Version	Intel Quartus Prime Version	IP Version	Hloov
2021.12.13	21.4	21.0.0	Kev tso tawm thawj zaug.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam.
* Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.
ISO 9001: 2015 Sau npe

Online Version
Xa lus tawm tswv yim
UA-20347
ID: 709308
Version: 2021.12.13

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