FPGA tus IP
Tsim Example User Guide
F-Tile 25G Ethernet Intel®
Hloov tshiab rau Intel® Quartus®
Prime Design Suite: 22.3
Tus IP Version: 1.0.0

Phau Ntawv Qhia Pib Ceev

F-tile 25G Ethernet Intel FPGA IP rau Intel Agilex™ pab kiag li lawm muab lub peev xwm ntawm generating tsim examples rau xaiv configurations.
Daim duab 1. Tsim Exampsiv le

Directory Structure

Daim duab 2. 25G Ethernet Intel FPGA IP Tsim Example Directory Structure

• Kev simulation files (testbench rau simulation nkaus xwb) nyob rau hauvample_dir>/example_testbench.
• Kev sau ua ke-tsuas yog tsim example nyob rau hauvample_dir>/ compilation_test_design.
• Hardware configuration thiab kuaj files (design example in hardware) nyob rau hauvample_dir>/hardware_test_design.

Table 1. Phau ntawv thiab File Cov lus piav qhia

File Cov npe	Kev piav qhia
eth_ex_25g.qpf	Qhov project Intel Quartus® Prime file.
eth_ex_25g.qsf	Intel Quartus Prime qhov project nqis file.
eth_ex_25g.sdc	Synopsys Design Constraints file. Koj tuaj yeem luam thiab hloov kho qhov no file rau koj tus kheej 25GbE Intel FPGA IP core tsim.
eth_ex_25g.v	Sab saum toj-theem Verilog HDL tsim example file. Ib leeg-channel tsim siv Verilog file.
nquag/	Kho vajtse design example txhawb files.
hwtest/main.tcl	Main file rau kev nkag mus rau System Console.

Tsim cov Design Example

Daim duab 4. Example Tsim Tab hauv F-tile 25G Ethernet Intel FPGA IP Parameter Editor

Ua raws li cov kauj ruam no los tsim kho kho vajtse tsim example and testbench:

1. Hauv Intel Quartus Prime Pro Edition, nyem File ➤ New Project Wizard los tsim ib qhov project Quartus Prime tshiab, lossis File ➤ Qhib Project qhib qhov project Quartus Prime uas twb muaj lawm. Tus wizard qhia koj kom qhia meej lub cuab yeej.
2. Hauv IP Catalog, nrhiav thiab xaiv 25G Ethernet Intel FPGA IP rau Agilex. Lub qhov rais tshiab IP Variation tshwm.
3. Qhia meej lub npe saum toj kawg nkaus rau koj qhov kev hloov pauv IP thiab nyem OK. Tus parameter editor ntxiv rau sab saum toj-theem .ip file mus rau qhov project tam sim no tau txais. Yog tias koj raug ceeb toom kom manually ntxiv .ip file mus rau qhov project, nyem qhov Project ➤ Ntxiv / Tshem tawm Files hauv Project ntxiv rau file.
4. Hauv Intel Quartus Prime Pro Edition software, koj yuav tsum xaiv ib qho tshwj xeeb Intel Agilex ntaus ntawv hauv Cov Ntaus Ntaus, lossis khaws cov cuab yeej ua ntej uas Intel Quartus Prime software npaj.
   Nco tseg: The hardware design example overwrite cov kev xaiv nrog cov cuab yeej ntawm lub hom phiaj board. Koj qhia kom meej lub hom phiaj board los ntawm cov ntawv qhia zaub mov ntawm tsim example options in the Example Design tab.
5. Nyem OK. Cov parameter editor tshwm.
6. Ntawm tus IP tab, qhia qhov tsis muaj rau koj tus IP qhov hloov pauv.
7. Hauv Example Design tab, for Examptsim Files, xaiv qhov kev xaiv Simulation los tsim lub testbench, thiab xaiv qhov kev xaiv Synthesis los tsim kho vajtse tsim example. Tsuas yog Verilog HDL files yog generated.
   Nco tseg: Ib qho ua haujlwm VHDL IP core tsis muaj. Qhia meej Verilog HDL nkaus xwb, rau koj tus IP core tsim example.
8. Rau Cov Khoom Siv Lub Hom Phiaj, xaiv Agilex I-series Transceiver-SoC Dev Kit
9. Nyem qhov Generate Example Design button. Xaiv Example Design Directory window tshwm.
10. Yog tias koj xav hloov kho tus tsim example directory path or name from the defaults displayed (alt_e25_f_0_example_design), xauj rau txoj hauv kev tshiab thiab ntaus tus qauv tshiab examplub npe directory (ample_dir>).
11. Nyem OK.

1.2.1. Tsim Example Parameters
Table 2. Parameters hauv Example Design Tab

Parameter	Kev piav qhia
Examptsim	Muaj example designs rau tus IP parameter nqis. Tsuas yog ib leeg-channel example tsim tau txhawb rau qhov IP no.
Examptsim Files	Cov files los tsim rau cov theem kev loj hlob sib txawv. • Simulation—tsim qhov tsim nyog files rau simulating example design. • Synthesis—tsim cov synthesis files. Siv cov no files los sau cov qauv tsim hauv Intel Quartus Prime Pro Edition software rau kev sim kho vajtse thiab ua qhov kev tshawb xyuas lub sijhawm zoo li qub.
Tsim File Hom ntawv	Cov hom ntawv ntawm RTL files rau simulation-Verilog.
Xaiv Board	Txhawb kev kho vajtse rau kev tsim qauv siv. Thaum koj xaiv Intel FPGA pawg thawj coj loj hlob, siv cov cuab yeej AGIB027R31B1E2VRO ua Lub Hom Phiaj Ntaus rau kev tsim example tiam. Agilex I-series Transceiver-SoC Dev Kit: Qhov kev xaiv no tso cai rau koj los ntsuas tus qauv tsim example ntawm qhov xaiv Intel FPGA IP txhim kho cov khoom siv. Qhov kev xaiv no cia li xaiv lub Hom Phiaj Ntaus ntawm AGIB027R31B1E2VRO. Yog tias koj lub rooj tsavxwm kho dua tshiab muaj qib ntaus ntawv sib txawv, koj tuaj yeem hloov lub hom phiaj ntaus ntawv. Tsis muaj: Qhov kev xaiv no tsis suav nrog cov khoom kho vajtse rau tus tsim example.

1.3. Tsim Pobzeb Files

Kev Txhawb-Logic Generation yog ib kauj ruam ua ntej kev sib txuas siv los tsim cov pobzeb ntsig txog files xav tau rau kev simulation thiab kho vajtse tsim. Kev tsim cov pobzeb yog xav tau rau txhua tus
F-tile raws li tsim simulations. Koj yuav tsum ua kom tiav cov kauj ruam no ua ntej simulation.

1. Ntawm qhov kev hais kom ua, mus rau lub compilation_test_design folder hauv koj tus exampua design:cd /compilation_test_design.
2. Khiav cov lus txib nram qab no: quartus_tlg alt_eth_25g

1.4. Simulating F-tile 25G Ethernet Intel FPGA IP Tsim 
Exampua Testbench
Koj tuaj yeem sau thiab simulate tus tsim los ntawm kev khiav ib tsab ntawv simulation los ntawm cov lus txib kom sai.

1. Ntawm qhov hais kom ua, hloov cov testbench simulating ua hauj lwm directory: cdample_dir>/ex_25g/sim.
2. Khiav tus IP teeb simulation: ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Table 3. Cov kauj ruam los simulate Testbench

Simulator	Cov lus qhia
VCS*	Hauv kab hais kom ua, ntaus sh run_vcs.sh
QuestaSim*	Hauv kab hais kom ua, ntaus vsim -do run_vsim.do -logfile vsim.log Yog tias koj xav simulate yam tsis tau nqa QuestaSim GUI, ntaus vsim -c -do run_vsim.do -logfile vsim.log
Cadence - Xcelium *	Hauv kab hais kom ua, ntaus sh run_xcelium.sh

Kev ua tiav simulation xaus nrog cov lus hauv qab no:
Simulation dhau lawm. los yog Testbench ua tiav.
Tom qab ua tiav tiav, koj tuaj yeem txheeb xyuas cov txiaj ntsig.
1.5. Compiling thiab Configuring Design Examphauv Hardware
25G Ethernet Intel FPGA IP core parameter editor tso cai rau koj los sau thiab teeb tsa tus tsim example ntawm lub hom phiaj kev txhim kho cov khoom siv.

Txhawm rau sau thiab teeb tsa tus qauv tsim examprau ntawm hardware, ua raws li cov kauj ruam no:

1. Tua tawm Intel Quartus Prime Pro Edition software thiab xaiv Kev Ua Haujlwm ➤ Pib Compilation los sau cov qauv tsim.
2. Tom qab koj tsim ib qho khoom SRAM file .sof, ua raws li cov kauj ruam no los tsim kho kho vajtse example ntawm Intel Agilex ntaus ntawv:
   a. Hauv Cov Cuab Yeej Cuab Yeej, nyem Programmer.
   b. Hauv Programmer, nyem Hardware Setup.
   c. Xaiv ib lub programming ntaus ntawv.
   d. Xaiv thiab ntxiv Intel Agilex pawg thawj coj saib rau koj qhov kev sib tham Intel Quartus Prime Pro Edition.
   e. Xyuas kom meej tias hom yog teem rau JTAG.
   f. Xaiv Intel Agilex ntaus ntawv thiab nyem Ntxiv Ntaus. Programmer qhia
   ib daim duab thaiv ntawm kev sib txuas ntawm cov khoom siv ntawm koj lub rooj tsavxwm.
   g. Hauv kab nrog koj .sof, kos lub thawv rau .sof.
   h. Kos lub npov nyob rau hauv Program/Configure kem.
   i. Nyem Pib.

1.6. Kuaj F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
Tom qab koj suav nrog F-tile 25G Ethernet Intel FPGA IP core tsim example thiab teeb tsa nws ntawm koj lub cuab yeej Intel Agilex, koj tuaj yeem siv System Console los pab txhawb IP core.
Txhawm rau qhib qhov System Console thiab sim kho vajtse tsim example, ua raws li cov kauj ruam no:

1. Hauv Intel Quartus Prime Pro Edition software, xaiv Cov Cuab Yeej ➤ System
   Debugging Tools ➤ System Console los tso lub system console.
2. Hauv Tcl Console pane, ntaus cd hwtest hloov cov npe rau / hardware_test_design/hwtest.
3. Ntaus qhov chaw main.tcl qhib kev sib txuas rau JTAG tus tswv.

Ua raws li cov txheej txheem xeem hauv ntu Hardware Testing ntawm tus tsim example thiab soj ntsuam cov txiaj ntsig kev xeem hauv System Console.

F-tile 25G Ethernet Tsim Example rau Intel Agilex Devices

F-tile 25G Ethernet tsim example ua qauv qhia kev daws teeb meem Ethernet rau Intel Agilex li siv 25G Ethernet Intel FPGA IP core.
Tsim tus tsim example example Tsim tab ntawm 25G Ethernet Intel FPGA IP parameter editor. Koj tuaj yeem xaiv los tsim cov qauv tsim nrog lossis tsis muaj
lub Reed-Solomon Forward Error Correction (RS-FEC) feature.
2.1. Nta

• Txhawb ib qho Ethernet channel ua haujlwm ntawm 25G.
• Generates tsim example nrog RS-FEC feature.
• Muab testbench thiab simulation tsab ntawv.
• Instantiates F-Tile Reference thiab System PLL Clocks Intel FPGA IP raws li IP teeb tsa.

2.2. Hardware thiab Software Requirements
Intel siv cov cuab yeej thiab software hauv qab no los kuaj tus qauv tsim exampnyob rau hauv Linux system:

• Intel Quartus Prime Pro Edition software.
• Siemens* EDA QuestaSim, Synopsys* VCS, thiab Cadence Xcelium simulator.
• Intel Agilex I-series Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) rau kev sim kho vajtse.

2.3. Cov lus piav qhia ua haujlwm
F-tile 25G Ethernet tsim example muaj MAC + PCS + PMA core variant. Cov duab thaiv hauv qab no qhia cov qauv tsim thiab cov cim qhia saum toj kawg nkaus ntawm MAC + PCS + PMA core variant hauv F-tile 25G Ethernet tsim example.
Daim duab 5. Block Diagram—F-tile 25G Ethernet Design Example (MAC + PCS + PMA Core Variant)

2.3.1. Tsim Cheebtsam
Table 4. Tsim Cheebtsam

Cheebtsam	Kev piav qhia
F-tile 25G Ethernet Intel FPGA IP	Muaj MAC, PCS, thiab Transceiver PHY, nrog rau cov kev teeb tsa hauv qab no: • Core Variant: MAC + PCS + PMA • Pab kom tswj tau ntws: Xaiv tau • Pab kom txuas qhov tsis raug tsim: Xaiv tau • Qhib preamble passthrough: Xaiv tau • Qhib cov ntaub ntawv txheeb cais: Xaiv tau • Qhib MAC cov ntaub ntawv txheeb cais: Xaiv tau • Siv lub moos zaus: 156.25 Rau tus tsim example nrog RS-FEC feature, cov nram qab no ntxiv parameter yog configured: • Qhib RS-FEC: Xaiv tau
F-Tile Reference thiab System PLL Clocks Intel FPGA IP	F-Tile Reference thiab System PLL Clocks Intel FPGA IP parameter editor teeb tsa ua ke nrog cov kev xav tau ntawm F-tile 25G Ethernet Intel FPGA IP. Yog tias koj tsim tus tsim example siv Tsim Examptsim khawm hauv tus IP parameter editor, tus IP instantiates tau. Yog koj tsim koj tus kheej tsim example, koj yuav tsum manually instantiate tus IP no thiab txuas tag nrho I/O ports. Yog xav paub ntxiv txog tus IP no, xa mus rau F-Tile Architecture thiab PMA thiab FEC Direct PHY IP Tus Neeg Siv Qhia.
Client logic	Muaj xws li: • Lub tshuab hluav taws xob tsheb, uas tsim cov pob ntawv tawg mus rau 25G Ethernet Intel FPGA IP core rau kev sib kis. • Kev saib xyuas tsheb, uas saib xyuas cov pob ntawv tawg uas tuaj ntawm 25G Ethernet Intel FPGA IP core.
Tau qhov twg los thiab soj ntsuam	Tau qhov twg los thiab soj ntsuam cov teeb liab, suav nrog lub kaw lus rov pib lub teeb liab tawm tswv yim, uas koj tuaj yeem siv rau kev debugging.

Cov ntaub ntawv ntsig txog
F-Tile Architecture thiab PMA thiab FEC Direct PHY IP Tus Neeg Siv Qhia

Kev simulation

Lub testbench xa cov tsheb khiav los ntawm tus tub ntxhais IP, ua haujlwm ntawm kev xa tawm sab thiab tau txais sab ntawm tus tub ntxhais IP.
2.4.1. Testbench
Daim duab 6. Block Diagram ntawm F-tile 25G Ethernet Intel FPGA IP Design Example Simulation Testbench

Table 5. Testbench Cheebtsam

Cheebtsam	Kev piav qhia
Device nyob rau hauv kev xeem (DUT)	25G Ethernet Intel FPGA IP core.
Ethernet Packet Generator thiab Packet Monitor	• Packet generator tsim thav duab thiab xa mus rau DUT. • Packet Monitor saib TX thiab RX datapaths thiab qhia cov thav duab hauv simulator console.
F-Tile Reference thiab System PLL Clocks Intel FPGA IP	Tsim cov transceiver thiab system PLL siv moos.

2.4.2. Simulation Design Exampcov Components
Table 6. F-tile 25G Ethernet Tsim Exampua Testbench File Cov lus piav qhia

File Lub npe	Kev piav qhia
Testbench thiab Simulation Files
Basic_avl_tb_top.v	Sab saum toj-theem testbench file. Lub testbench instantiates DUT, ua Avalon® nco-mapped configuration ntawm tsim cov khoom thiab cov neeg siv logic, thiab xa thiab tau txais pob ntawv mus rau los yog los ntawm 25G Ethernet Intel FPGA IP.
Testbench Scripts
txuas ntxiv…

File Lub npe	Kev piav qhia
run_vsim.do	ModelSim tsab ntawv los khiav lub testbench.
run_vcs.sh	Synopsys VCS tsab ntawv los khiav lub testbench.
run_xcelium.sh	Cadence Xcelium tsab ntawv los khiav lub testbench.

2.4.3. Kuaj Case
Cov ntaub ntawv simulation sim ua cov haujlwm hauv qab no:

1. Instantiates F-tile 25G Ethernet Intel FPGA IP thiab F-Tile Reference thiab System PLL Clocks Intel FPGA IP.
2. Tos rau RX moos thiab PHY xwm txheej teeb liab los daws teeb meem.
3. Luam tawm PHY xwm txheej.
4. Xa thiab tau txais 10 cov ntaub ntawv siv tau.
5. Txheeb xyuas cov txiaj ntsig. Qhov kev vam meej testbench qhia "Testbench tiav."

Cov nram qab no sample cov zis qhia txog kev ua tiav simulation kev xeem khiav:

Muab tso ua ke

Ua raws li cov txheej txheem hauv Compiling thiab Configuring Design Example hauv Hardware los compile thiab configure tus tsim example nyob rau hauv lub hardware xaiv.
Koj tuaj yeem kwv yees kev siv cov peev txheej thiab Fmax siv qhov kev sau ua ke-tsuas yog tsim example. Koj tuaj yeem suav koj tus qauv siv lub Start Compilation hais kom ua ntawm lub
Ua cov ntawv qhia zaub mov hauv Intel Quartus Prime Pro Edition software. Ib qho kev ua tiav tiav ua tiav cov ntaub ntawv sau ua ke.
Yog xav paub ntxiv, xa mus rau Tsim Kev Sau Npe hauv Intel Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv.
Cov ntaub ntawv ntsig txog

• Compiling thiab Configuring Design Example hauv Hardware ntawm nplooj 7
• Tsim Tso Cai Hauv Intel Quartus Prime Pro Tsab Ntawv Qhia Tus Neeg Siv

2.6. Kev sim kho vajtse
Hauv kev tsim kho vajtse example, koj tuaj yeem ua haujlwm rau IP core nyob rau hauv serial loopback hom thiab tsim cov tsheb khiav ntawm sab kis uas loops rov qab los ntawm qhov tau txais sab.
Ua raws li cov txheej txheem ntawm qhov muab cov ntaub ntawv txuas mus kuaj tus qauv example nyob rau hauv lub hardware xaiv.
Cov ntaub ntawv ntsig txog
Kuaj F-tile 25G Ethernet Intel FPGA IP Hardware Design Exampli ntawm nplooj 8
2.6.1. Kuaj Cov Txheej Txheem
Ua raws li cov kauj ruam no los ntsuas tus qauv tsim exampnyob rau hauv hardware:

1. Ua ntej koj khiav lub hardware kuaj rau qhov tsim exampYog li, koj yuav tsum rov pib dua qhov system:
   a. Nyem Cov cuab yeej ➤ Hauv-System Sources & Probes Editor cuab yeej rau lub neej ntawd Source thiab Probe GUI.
   b. Toggle lub kaw lus rov pib teeb liab (Qhov Chaw [3: 0]) los ntawm 7 mus rau 8 txhawm rau siv qhov rov pib dua thiab xa rov qab lub kaw lus rov teeb tsa rov qab mus rau 7 kom tso lub kaw lus los ntawm lub xeev rov pib dua.
   c. Saib xyuas cov Probe signals thiab xyuas kom meej tias cov xwm txheej siv tau.
2. Hauv qhov system console, mus rau hwtest folder thiab khiav cov lus txib: qhov chaw main.tcl los xaiv JTAG tus tswv. Los ntawm lub neej ntawd, thawj JTAG master ntawm JTAG saw hlau raug xaiv. Txhawm rau xaiv JTAG tswv rau Intel Agilex li, khiav cov lus txib no: set_jtag <number of appropriate JTAG tswv >. Example: set_jtag 1.
3. Khiav cov lus txib hauv qab no hauv qhov system console kom pib qhov kev xeem serial loopback:

Table 7. Hais kom Parameters

Parameter	Kev piav qhia	Exampsiv le
chkphy_status	Qhia lub moos zaus thiab PHY ntsuas phoo.	% chkphy_status 0 # Txheeb xyuas cov xwm txheej ntawm qhov txuas 0
chkmac_stats	Qhia cov txiaj ntsig hauv MAC cov txheeb cais.	% chkmac_stats 0 # Tshawb xyuas mac cov txheeb cais ntawm qhov txuas 0
clear_all_stats	Clears tus IP tseem ceeb txheeb cais cov txee.	% clear_all_stats 0 # Clears txheeb cais txee ntawm qhov txuas 0
pib_gen	Pib lub packet generator.	% start_gen 0 # Pib pob ntawv tsim ntawm qhov txuas 0
nres_gen	Nres lub pob ntawv tshuab hluav taws xob.	% stop_gen 0 # Nres pob ntawv tsim ntawm qhov txuas 0
rov_on	Tig rau sab hauv serial loopback.	% loop_on 0 # Tig rau sab hauv loopback ntawm qhov txuas 0
rov_off	Tua tawm internal serial loopback.	% loop_off 0 # Tua tawm sab hauv loopback ntawm qhov txuas 0
reg_read	Rov qab IP core register tus nqi ntawm .	% reg_read 0x402 # Nyeem IP CSR sau npe ntawm qhov chaw nyob 402 ntawm qhov txuas 0
reg_write	Sau mus rau IP tub ntxhais sau npe ntawm qhov chaw nyob .	% reg_write 0x401 0x1 # Sau 0x1 rau IP CSR kos npe ntawm qhov chaw nyob 401 ntawm qhov txuas 0

a. Ntaus loop_on los qhib lub internal serial loopback hom.
b. Ntaus chkphy_status txhawm rau txheeb xyuas qhov xwm txheej ntawm PHY. TXCLK, RXCLK, thiab RX cov xwm txheej yuav tsum muaj cov txiaj ntsig zoo ib yam qhia hauv qab no rau qhov txuas ruaj khov:

c. Ntaus clear_all_stats txhawm rau tshem TX thiab RX cov ntawv txheeb cais.
d. Ntaus start_gen pib pob ntawv tiam.
e. Ntaus stop_gen kom nres pob ntawv tiam.
f. Ntaus chkmac_stats nyeem TX thiab RX cov ntawv txheeb cais. Xyuas kom meej tias:
i. Cov pob ntawv kis tau zoo sib xws nrog cov pob ntawv tau txais.
ii. Tsis tau txais cov ntawv yuam kev.
g. Ntaus loop_off mus tua lub internal serial loopback.
Daim duab 7. Sample Test Output—TX and RX Statistics Counters

Cov ntaub ntawv kho dua tshiab rau F-tile 25G Ethernet FPGA IP Tsim Example User Guide

Cov ntaub ntawv Version	Intel Quartus Prime Version	IP Version	Hloov
2022.10.14	22.3	1.0.0	Kev tso tawm thawj zaug.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.
ISO
9001:2015 ua
Sau npe

Online Version
Xa lus tawm tswv yim
PIB: 750200
Version: 2022.10.14

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