F-Tile Interlaken Intel FPGA IP Tsim Example

Phau Ntawv Qhia Pib Ceev

F-Tile Interlaken Intel® FPGA IP core muab lub simulation testbench. Hardware design example uas txhawb kev muab tso ua ke thiab kev sim kho vajtse yuav muaj nyob rau hauv Intel Quartus® Prime Pro Edition software version 21.4. Thaum koj tsim tus tsim example, parameter editor cia li tsim cov files yuav tsum simulate, compile, thiab sim tus tsim.
The testbench thiab design example txhawb NRZ thiab PAM4 hom rau F-tile li. F-Tile Interlaken Intel FPGA IP core tsim tsim examples rau cov nram qab no txhawb kev sib txuas ntawm cov kab thiab cov ntaub ntawv tus nqi.

IP txhawb kev sib txuas ntawm cov xov tooj ntawm txoj kab thiab cov ntaub ntawv tus nqi
Cov kev sib txuas hauv qab no tau txais kev txhawb nqa hauv Intel Quartus Prime Pro Edition software version 21.3. Tag nrho lwm qhov kev sib xyaw ua ke yuav tau txais kev txhawb nqa yav tom ntej ntawm Intel Quartus Prime Pro Edition.

Number of Lanes	Txoj kab uas hla (Gbps)
	6.25	10.3125	12.5	25.78125	53.125
4	Yog lawm	-	Yog lawm	Yog lawm	-
6	-	-	-	Yog lawm	Yog lawm
8	-	-	Yog lawm	Yog lawm	-
10	-	-	Yog lawm	Yog lawm	-
12	-	Yog lawm	Yog lawm	Yog lawm	-

Daim duab 1.Development Steps for the Design Example

Nco tseg: Hardware Compilation thiab Testing yuav muaj nyob rau hauv Intel Quartus Prime Pro Edition software version 21.4.
F-Tile Interlaken Intel FPGA IP core tsim example txhawb cov yam ntxwv hauv qab no:

• Internal TX to RX serial loopback mode
• Tsis siv neeg tsim cov pob ntawv loj tas li
• Basic packet checking peev xwm
• Muaj peev xwm siv System Console los pib dua tus qauv tsim rau rov sim dua lub hom phiaj

Daim duab 2.High-theem Block Diagram

Cov ntaub ntawv ntsig txog

• F-Tile Interlaken Intel FPGA Tus Neeg Siv Phau Ntawv Qhia
• F-Tile Interlaken Intel FPGA IP Tso Lus Sau

Hardware thiab Software Requirements

Mus kuaj tus example tsim, siv hardware thiab software hauv qab no:

• Intel Quartus Prime Pro Edition software version 21.3
• System Console
• Txhawb Simulator:
  • Synopsys* VCS*
  • Synopsys VCS MX
  • Siemens* EDA ModelSim* SE or Questa*

Nco tseg:  Kev them nyiaj yug Hardware rau tsim example yuav muaj nyob rau hauv Intel Quartus Prime Pro Edition software version 21.4.

Tsim tus Tsim

Daim duab 3. Txheej txheem

Ua raws li cov kauj ruam no los tsim cov qauv tsim example and testbench:

1. Hauv Intel Quartus Prime Pro Edition software, nyem File ➤ New Project Wizard los tsim ib txoj haujlwm tshiab Intel Quartus Prime, lossis nyem File ➤ Qhib Project qhib qhov project Intel Quartus Prime uas twb muaj lawm. Tus wizard qhia koj kom qhia meej lub cuab yeej.
2. Qhia rau tsev neeg Agilex thiab xaiv cov cuab yeej nrog F-Tile rau koj tus qauv tsim.
3. Hauv IP Catalog, nrhiav thiab nyem ob npaug rau F-Tile Interlaken Intel FPGA IP. Lub qhov rais tshiab IP Variant tshwm.
4. Qhia lub npe saum toj kawg nkaus rau koj tus IP kev hloov pauv. Tus parameter editor txuag tus IP variation nqis hauv a file npe .ip ib.
5. Nyem OK. Cov parameter editor tshwm.

Daim duab 4. Example Design Tab

6. Ntawm tus IP tab, qhia qhov tsis muaj rau koj qhov kev hloov pauv ntawm tus IP tseem ceeb.
7. Example Tsim tab, xaiv qhov kev xaiv Simulation los tsim cov testbench.
Nco tseg: Kev xaiv Synthesis yog rau kho vajtse example tsim, uas yuav muaj nyob rau hauv Intel Quartus Prime Pro Edition software version 21.4.
8. Rau Generated HDL hom, ob qho tib si Verilog thiab VHDL kev xaiv muaj.
9. Nyem Tsim Example Design. Xaiv Example Design Directory window tshwm.
10. Yog tias koj xav hloov kho tus tsim example directory path or name from the defaults displayed (ilk_f_0_example_design), xauj rau txoj hauv kev tshiab thiab ntaus tus qauv tshiab exampnpe directory.
11. Nyem OK.

Nco tseg: Hauv F-Tile Interlaken Intel FPGA IP tsim example, SystemPLL yog instantiated tau, thiab txuas nrog F-Tile Interlaken Intel FPGA IP core. SystemPLL hierarchy txoj hauv kev tsim example yog:

example_design.test_env_inst.test_dut.dut.pl

SystemPLL hauv tus tsim example qhia tib yam 156.26 MHz siv moos raws li Transceiver.

Directory Structure

F-Tile Interlaken Intel FPGA IP core tsim cov hauv qab no files rau tus tsim example:
Daim duab 5. Daim Ntawv Teev Npe

Table 2. Hardware Design Example File Cov lus piav qhia
Cov no files yog inample_installation_dir>/ilk_f_0_example_design directory.

File Cov npe	Kev piav qhia
example_design.qpf	Qhov project Intel Quartus Prime file.
example_design.qsf	Intel Quartus Prime qhov project nqis file
example_design.sdc jtag_timeing_template.sdc	Synopsys Design Constraint file. Koj tuaj yeem luam thiab hloov kho rau koj tus kheej tsim.
sysconsole_testbench.tcl	Main file rau kev nkag mus rau System Console

Nco tseg: Kev them nyiaj yug Hardware rau tsim example yuav muaj nyob rau hauv Intel Quartus Prime Pro Edition software version 21.4.

Rooj 3. Testbench File Kev piav qhia

Qhov no file yog nyob rau hauvample_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.

File Lub npe	Kev piav qhia
top_tb.sv	Sab saum toj-theem testbench file.

Table 4. Testbench Scripts

Cov no files yog inample_installation_dir>/ilk_f_0_example_design/example_design/testbench directory

File Lub npe	Kev piav qhia
run_vcs.sh	Synopsys VCS tsab ntawv los khiav lub testbench.
run_vcsmx.sh	Synopsys VCS MX tsab ntawv los khiav lub testbench.
run_mentor.tcl	Siemens EDA ModelSim SE los yog Questa tsab ntawv los khiav lub testbench.

Simulating Design Exampua Testbench

Daim duab 6. Cov txheej txheem

Ua raws li cov kauj ruam no los simulate lub testbench:

1. Ntawm qhov hais kom ua, hloov mus rau testbench simulation directory. Txoj kev directory yogample_installation_dir>/example_design/testbench.
2. Khiav cov ntawv simulation rau qhov kev txhawb nqa simulator ntawm koj xaiv. Cov ntawv sau ua ke thiab khiav lub testbench hauv lub simulator. Koj tsab ntawv yuav tsum kuaj xyuas tias SOP thiab EOP suav qhov sib tw tom qab simulation tiav.

Rooj 5. Cov kauj ruam los khiav Simulation

Simulator	Cov lus qhia
VCS	Hauv kab hais kom ua, ntaus:   sh run_vcs.sh
VCS MX	Hauv kab hais kom ua, ntaus:   sh run_vcsmx.sh
ModelSim SE or Questa	Hauv kab hais kom ua, ntaus:   vsim -do run_mentor.tcl Yog tias koj xav simulate yam tsis tau nqa ModelSim GUI, ntaus:   vsim -c -do run_mentor.tcl

3. Txheeb xyuas cov txiaj ntsig. Kev simulation ua tiav xa thiab tau txais pob ntawv, thiab qhia tias "Test PASSED".

Testbench rau tus tsim example ua tiav cov haujlwm hauv qab no:

• Instantiates F-Tile Interlaken Intel FPGA IP core.
• Luam tawm PHY xwm txheej.
• Tshawb xyuas metaframe synchronization (SYNC_LOCK) thiab lo lus (block) ciam teb (WORD_LOCK).
• Tos rau tus kheej txoj kab yuav raug kaw thiab ua kom haum.
• Pib kis pob ntawv.
• Tshawb xyuas pob ntawv txheeb cais:
  • CRC24 yuam kev
  • SOPs
  • EOPs

Cov nram qab no sample cov zis qhia txog kev ua tiav simulation kev xeem khiav:

Compiling tus Design Example

1. Xyuas kom tus example tsim tiam ua tiav.
2. Hauv Intel Quartus Prime Pro Edition software, qhib Intel Quartus Prime projectample_installation_dir>/example_design.qpf>.
3. Nyob rau hauv cov ntawv qhia zaub mov, nyem Start Compilation.

Tsim Examplus piav qhia

Design example qhia txog kev ua haujlwm ntawm Interlaken IP core.

Tsim Exampcov Components

Cov example tsim txuas qhov system thiab PLL siv moos thiab cov khoom tsim tsim. Cov example tsim configures tus IP core nyob rau hauv internal loopback hom thiab generates packets ntawm tus IP core TX cov neeg siv cov ntaub ntawv hloov lwm lub tsev interface. IP tub ntxhais xa cov pob ntawv no rau ntawm txoj hauv kev rov qab los ntawm lub transceiver.
Tom qab tus IP tub ntxhais txais tau txais cov pob ntawv ntawm txoj kev rov qab, nws ua cov pob ntawv Interlaken thiab xa lawv ntawm RX cov neeg siv cov ntaub ntawv hloov chaw. Cov example tsim kuaj xyuas tias cov pob ntawv tau txais thiab kis sib tw.
F-Tile Interlaken Intel IP tsim example suav nrog cov hauv qab no:

1. F-Tile Interlaken Intel FPGA IP tub ntxhais
2. Packet Generator thiab Packet Checker
3. F-Tile Reference thiab System PLL Clocks Intel FPGA IP core

Interface Signals

Table 6. Tsim Example Interface Signals

Chaw nres nkoj npe	Kev taw qhia	Dav (ntsis)	Kev piav qhia
mgmt_clk	Tswv yim	1	System moos input. Lub moos zaus yuav tsum yog 100 MHz.
npl_ref_clk	Tswv yim	1	Transceiver siv moos. Tsav RX CDR PLL.
rx_pin	Tswv yim	Tus lej ntawm txoj kab	Tus neeg txais SERDES cov ntaub ntawv tus pin.
tx_pin	Tso zis	Tus lej ntawm txoj kab	Hloov SERDES cov ntaub ntawv tus pin.
rx_pin_n(1)	Tswv yim	Tus lej ntawm txoj kab	Tus neeg txais SERDES cov ntaub ntawv tus pin.
tx_pin_n(1)	Tso zis	Tus lej ntawm txoj kab	Hloov SERDES cov ntaub ntawv tus pin.
mac_clk_pl_ref	Tswv yim	1	Cov teeb liab no yuav tsum tau tsav los ntawm PLL thiab yuav tsum siv tib lub moos uas tsav lub pll_ref_clk. Cov teeb liab no tsuas yog muaj nyob rau hauv PAM4 hom ntaus ntawv hloov pauv.
usr_pb_reset_n	Tswv yim	1	Qhov system pib dua.

(1) Tsuas muaj nyob rau hauv PAM4 variants.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam.
* Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Sau npe daim ntawv qhia

Nco tseg:

• Tsim Example sau npe chaw nyob pib nrog 0x20** thaum Interlaken IP core register chaw nyob pib nrog 0x10**.
• F-tile PHY sau npe chaw nyob pib nrog 0x30** thaum F-tile FEC sau npe chaw nyob pib nrog 0x40**. FEC sau npe tsuas yog muaj nyob rau hauv PAM4 hom.
• Nkag mus rau code: RO—Nyeem nkaus xwb, thiab RW—Nyeem/Sau.
• System console nyeem tus tsim example sau npe thiab tshaj tawm cov xwm txheej xeem ntawm qhov screen.

Table 7. Tsim Example Register Map

Offset	Lub npe	Nkag mus	Kev piav qhia
8h00 ua	Khaws tseg
8h01 ua	Khaws tseg
8h02 ua	System PLL rov pib dua	RO	Cov khoom nram qab no qhia txog qhov system PLL rov pib thov thiab pab tus nqi: • Bit [0] – sys_pll_rst_req • ntsis [1] – sys_pll_rst_en
8h03 ua	RX txoj kab aligned	RO	Qhia txog RX txoj kab sib dhos.
8h04 ua	Lo lus xauv	RO	[NUM_LANES–1:0] – Lo lus (block) ciam teb kev txheeb xyuas.
8h05 ua	Sync xauv	RO	[NUM_LANES–1:0] – Metaframe synchronization.
8-06 Nws	CRC32 yuam kev suav	RO	Qhia txog CRC32 yuam kev suav.
8h0 ua	CRC24 yuam kev suav	RO	Qhia txog CRC24 yuam kev suav.
8h0 ib	Overflow / Underflow teeb liab	RO	Cov nram qab no qhia tias: • Ntsis [3] – TX underflow signal • Ntsis [2] – TX overflow signal • Ntsis [1] – RX overflow teeb liab
8h0c ua	SOP suav	RO	Qhia tus naj npawb ntawm SOP.
8h0d ua	EOP suav	RO	Qhia tus naj npawb ntawm EOP
8 h0e	yuam kev suav	RO	Qhia tus lej ntawm qhov yuam kev hauv qab no: • Poob txoj kab sib dhos • Lo lus tswj tsis raug cai • Tsis raug cai framing qauv • Qhov taw qhia SOP lossis EOP ploj lawm
8h0f ua	xa_data_mm_clk	RW	Sau 1 mus rau me ntsis [0] los pab kom lub tshuab hluav taws xob teeb liab.
8h10 ua	Checker yuam kev		Qhia tus checker yuam kev. (SOP cov ntaub ntawv yuam kev, Channel tus lej yuam kev, thiab PLD cov ntaub ntawv yuam kev)
8h11 ua	System PLL xauv	RO	Bit [0] qhia PLL ntsuas phoo.
8h14 ua	TX SOP count	RO	Qhia txog tus naj npawb ntawm SOP tsim los ntawm pob ntawv tshuab hluav taws xob.
8h15 ua	TX EOP count	RO	Qhia txog tus naj npawb ntawm EOP tsim los ntawm pob khoom siv hluav taws xob.
8h16 ua	Pob ntawv txuas ntxiv	RW	Sau 1 mus rau me ntsis [0] kom pab tau cov pob ntawv txuas ntxiv.
txuas ntxiv…

Offset	Lub npe	Nkag mus	Kev piav qhia
8h39 ua	ECC yuam kev suav	RO	Qhia tus lej ntawm ECC yuam kev.
8h40 ua	ECC kho qhov yuam kev suav	RO	Qhia txog tus lej ntawm kev kho ECC qhov yuam kev.
8h50 ua	tile_tx_rst_n	WO	Pobzeb rov pib dua rau SRC rau TX.
8h51 ua	tile_rx_rst_n	WO	Pobzeb rov pib dua rau SRC rau RX.
8h52 ua	tile_tx_rst_ack_n	RO	Pobzeb rov pib lees paub los ntawm SRC rau TX.
8h53 ua	tile_rx_rst_ack_n	RO	Pobzeb rov pib lees paub los ntawm SRC rau RX.

Rov pib dua

Hauv F-Tile Interlaken Intel FPGA IP core, koj pib rov pib dua (reset_n=0) thiab tuav kom txog thaum tus tub ntxhais IP rov qab lees paub (reset_ack_n=0). Tom qab rov pib dua raug tshem tawm (reset_n=1), qhov rov qab lees paub rov qab mus rau nws lub xeev thawj zaug
(reset_ack_n=1). Hauv kev tsim example, tus sau npe rst_ack_sticky tuav qhov kev lees paub rov pib dua thiab tom qab ntawd ua rau kev tshem tawm ntawm qhov pib dua (reset_n=1). Koj tuaj yeem siv lwm txoj hauv kev uas haum rau koj cov kev xav tau tsim.

Tseem ceeb: Nyob rau hauv txhua qhov xwm txheej uas yuav tsum tau muaj nyob rau hauv serial loopback, koj yuav tsum tso TX thiab RX ntawm F-tile cais nyob rau hauv ib qho kev txiav txim. Xa mus rau qhov system console tsab ntawv yog xav paub ntxiv.

Daim duab 7.Reset Sequence hauv NRZ hom

Daim duab 8.Reset Sequence hauv PAM4 hom

F-Tile Interlaken Intel FPGA IP Tsim Example User Guide Archives

Yog tias tus IP core version tsis tau teev tseg, cov lus qhia siv rau tus IP core version dhau los siv.

Intel Quartus Prime Version	IP Core Version	Cov neeg siv phau ntawv qhia
21.2	2.0.0	F-Tile Interlaken Intel FPGA IP Tsim Example User Guide

Cov ntaub ntawv kho dua tshiab rau F-Tile Interlaken Intel FPGA IP Tsim Example User Guide

Cov ntaub ntawv Version	Intel Quartus Prime Version	IP Version	Hloov
2021.10.04	21.3	3.0.0	• Ntxiv kev txhawb nqa rau txoj kab kev sib txuas tshiab. Yog xav paub ntxiv, saib mus rau Cov lus: IP txhawb kev sib txuas ntawm cov lej ntawm txoj kab thiab cov ntaub ntawv tus nqi. • Hloov kho cov npe simulator txhawb nqa hauv ntu: Hardware thiab Software Requirements. • Ntxiv cov ntawv teev npe rov pib dua tshiab hauv ntu: Sau npe daim ntawv qhia.
2021.06.21	21.2	2.0.0	Kev tso tawm thawj zaug.

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