intel 750856 Agilex FPGA Development Board

Bayanin samfur

Wannan ƙirar tunani don Intel Agilex F-Series FPGA Development Board ne. Yana amfani da Babban Mai Kula da Tsarin Kanfigareshan Waje na Intel FPGA IP kuma yana da yankin PR mai sauƙi. Saitin Hardware na Intel Agilex External Host Hardware ya ƙunshi na'urar waje (Mataimaki FPGA), DUT FPGA, da ƙirar mai masaukin ku na waje. Tsarin mai watsa shiri a cikin na'urar waje yana da alhakin ɗaukar nauyin tsarin PR. Ana amfani da fil ɗin PR don haɗa na'urori biyu kuma suna iya zama kowane mai amfani I/Os.

Umarnin Amfani da samfur

Kanfigareshan Mai watsa shiri na waje

Don aiwatar da daidaitawar runduna ta waje, bi waɗannan matakan:

1. Ƙirƙirar ƙirar mai watsa shiri a cikin na'urar waje don ɗaukar nauyin tsarin PR.
2. Haɗa fil ɗin PR daga na'urar waje zuwa Babban Mai sarrafa Kanfigareshan Tsare-tsare na Waje na Intel FPGA IP a cikin DUT FPGA.
3. Bayanan daidaitawa mai gudana daga ƙirar mai watsa shiri zuwa Intel Agilex Avalon fitattun filaye masu yawo waɗanda suka dace da siginar musabaha na PR daga IP.

Sake saita wani ɓangare ta hanyar Aiki na Kanfigareshan Finfiguration

Jeri mai zuwa yana bayyana aikin sake fasalin wani ɓangare ta hanyar fil ɗin daidaitawa:

1. Sanya fil ɗin pr_request da aka haɗa zuwa Babban Mai Kula da Kanfigareshan Kanfigareshan Waje na Intel FPGA IP.
2. IP ɗin yana tabbatar da siginar aiki don nuna cewa tsarin PR yana kan ci gaba (na zaɓi).
3. Idan tsarin daidaitawa ya shirya don aikin PR, an tabbatar da avst_ready fil, yana nuna cewa a shirye yake don karɓar bayanai.
4. Yada bayanan daidaitawar PR akan fil ɗin avst_data da fil ɗin avst_valid, bin ƙayyadaddun ƙayyadaddun yawo na Avalon don canja wurin bayanai tare da matsi na baya.
5. Yawo yana tsayawa lokacin da aka cire avst_ready fil.
6. Cire avst_ready fil don nuna cewa ba a buƙatar ƙarin bayanai don aikin PR.
7. Mai sarrafa Sake Tsari na Waje na Intel FPGA IP yana kawar da siginar aiki don nuna ƙarshen tsari (na zaɓi).

Sake saitin ɓangaren ta hanyar Fin Kanfigareshan (Mai watsa shiri na waje) Ƙirar Magana

Wannan bayanin kula na aikace-aikacen yana nuna sake fasalin wani yanki ta hanyar fil ɗin daidaitawa (mai masaukin baki na waje) akan kwamitin haɓakawa na Intel® Agilex® F-Series FPGA.

Reference Design Overview

Siffar sake fasalin ɓangaren (PR) tana ba ku damar sake saita wani yanki na FPGA a hankali, yayin da sauran ƙirar FPGA ke ci gaba da aiki. Kuna iya ƙirƙirar mutane da yawa don wani yanki a cikin ƙirar ku waɗanda ba su tasiri aiki a yankunan da ke wajen wannan yanki. Wannan dabarar tana da tasiri a cikin tsarin inda ayyuka da yawa ke raba lokaci-raba albarkatun na'urar FPGA iri ɗaya. Sigar na yanzu na software na Intel Quartus® Prime Pro Edition yana gabatar da sabon kuma sauƙaƙan kwararar tattarawa don sake fasalin wani yanki. Wannan ƙirar ƙira ta Intel Agilex tana amfani da Babban Mai Kula da Kanfigareshan Tsarin Waje na Intel FPGA IP kuma yana da yankin PR mai sauƙi.

Intel Agilex Na'urar Mai watsa shiri na waje Saitin Hardware

Kanfigareshan Mai watsa shiri na waje

A cikin saitin runduna ta waje, dole ne ka fara ƙirƙirar ƙirar mai masaukin baki a cikin na'urar waje don ɗaukar nauyin tsarin PR, kamar yadda Saitin Hardware na Na'ura na Waje na Intel Agilex ya nuna. Ƙirar ƙirar mai watsa shiri tana ba da bayanan saiti zuwa Intel Agilex Avalon ginshiƙan keɓancewar keɓancewa wanda ya dace da siginar musabaha na PR waɗanda suka fito daga Mai sarrafa Tsarin Kanfigareshan Waje na Intel FPGA IP. Filayen PR da kuke amfani da su don haɗa na'urorin biyu na iya zama kowane mai amfani da I/Os.

Jeri mai zuwa yana bayyana sake fasalin wani ɓangare ta hanyar aikin fil ɗin sanyi:

1. Da farko tabbatar da fil ɗin pr_request wanda ke haɗe zuwa Babban Mai Kula da Kanfigareshan Kanfigareshan Waje na Intel FPGA IP.
2. IP ɗin yana tabbatar da siginar aiki don nuna cewa tsarin PR yana kan ci gaba (na zaɓi).
3. Idan tsarin daidaitawa ya shirya don aiwatar da aikin PR, an tabbatar da avst_ready fil yana nuna cewa a shirye yake don karɓar bayanai.
4. Fara jera bayanan daidaitawar PR akan fil ɗin avst_data da avst_valid fil, yayin lura da ƙayyadaddun yawo na Avalon don canja wurin bayanai tare da matsi na baya.
5. Yawo yana tsayawa a duk lokacin da aka cire avst_ready fil.
6. Bayan yawo duk bayanan sanyi, an cire avst_ready fil don nuna cewa ba a buƙatar ƙarin bayanai don aikin PR.
7. Mai sarrafa Sake Tsari na Waje na Intel FPGA IP yana ba da siginar aiki don nuna ƙarshen tsari (na zaɓi).
8. Kuna iya duba pr_done da pr_error fil don tabbatar da ko an kammala aikin PR cikin nasara. Idan kuskure ya faru, kamar gazawa a cikin duba sigar da duba izini, aikin PR ya ƙare.

Bayanai masu alaƙa

• Intel Agilex F-Series FPGA Development Kit Web Shafi
• Intel Agilex F-Series FPGA Jagorar Mai Amfani da Kit ɗin Haɓaka
• Jagorar Mai Amfani da Quartus Prime Pro Edition: Sake Tsari na Sashe

Babban Sake Tsari Mai Kula da Kanfigareshan Waje na Intel FPGA IP
Ana buƙatar Mai Kula da Kanfigareshan Tsare-tsare na Waje don amfani da fil ɗin daidaitawa don jera bayanan PR don aikin PR. Dole ne ku haɗa dukkan manyan tashoshin jiragen ruwa na Partial Reconfiguration External Configuration Controller Intel FPGA IP zuwa pr_request fil don ba da damar musafin mai watsa shiri tare da amintaccen manajan na'ura (SDM) daga ainihin. SDM yana ƙayyade nau'ikan fil ɗin daidaitawa don amfani, bisa ga saitin MSEL ɗin ku.

Babban Sake Tsari Mai Kula da Kanfigareshan Waje na Intel FPGA IP

Saitunan Saitunan Sigar Kanfigareshan Mai Gudanarwa na waje

Siga	Daraja	Bayani
Kunna Interface Mai Aiki	Kunna or A kashe	Yana ba ku damar Kunnawa ko Kashe keɓan hanyoyin sadarwa, wanda ke tabbatar da sigina don nuna cewa ana ci gaba da sarrafa PR yayin daidaitawar waje. Saitin tsoho shine A kashe.

Tashoshin Tashoshin Saitunan Kanfigareshan Kanfigareshan Na Waje

Sunan tashar jiragen ruwa	Nisa	Hanyar	Aiki
pr_request	1	Shigarwa	Yana nuna cewa tsarin PR yana shirye don farawa. Siginar magudanar ruwa ce wacce ba ta aiki tare da kowace siginar agogo.
pr_error	2	Fitowa	Yana nuna kuskuren sake daidaitawa. • 2'b01-kuskuren PR na gaba ɗaya 2'b11-kuskuren bitar da ba ta dace ba Waɗannan sigina na magudanar ruwa ba su daidaita da kowace tushen agogo.
pr_yi	1	Fitowa	Yana nuna cewa tsarin PR ya cika. Siginar magudanar ruwa ce wacce ba ta aiki tare da kowace siginar agogo.
fara_adr	1	Shigarwa	Yana ƙayyade adireshin farkon bayanan PR a cikin Serial Flash Active. Kuna kunna wannan siginar ta zaɓi ɗaya Avalon®-ST or Serial Mai Aiki domin Kunna Finan Avalon-ST ko Serial Finai masu Aiki siga. Siginar magudanar ruwa ce wacce ba ta aiki tare da kowace siginar agogo.
sake saiti	1	Shigarwa	Babban aiki, siginar sake saitin aiki tare.
fita_clk	1	Fitowa	Tushen agogo wanda ke fitowa daga oscillator na ciki.
aiki	1	Fitowa	IP ɗin yana tabbatar da wannan siginar don nuna ana ci gaba da canja wurin bayanan PR. Kuna kunna wannan siginar ta zaɓi Kunna domin Kunna aiki mai aiki siga.

Bukatun Zane Na Magana

Amfani da wannan ƙirar ƙira yana buƙatar masu zuwa:

• Shigar da sigar Intel Quartus Prime Pro Edition 22.3 tare da goyan bayan dangin na'urar Intel Agilex.
• Haɗin kai zuwa Intel Agilex F-Series FPGA kwamitin haɓakawa akan benci.
• Zazzage zanen exampana iya samunsu a wuri mai zuwa: https://github.com/intel/fpga-partial-reconfig.

Don sauke zane exampda:

1. Danna Clone ko zazzagewa.
2. Danna Zazzage ZIP. Cire fpga-partial-reconfig-master.zip file.
3. Kewaya zuwa babban fayil ɗin koyawa/agilex_external_pr_configuration don samun damar ƙirar ƙira.

Tafiyar Tsara Nasiha

Matakan da ke biyowa suna bayyana aiwatar da sake fasalin wani yanki ta hanyar fil ɗin daidaitawa (mai masaukin baki na waje) akan kwamitin haɓakawa na Intel Agilex F-Series FPGA:

• Mataki na 1: Farawa
• Mataki 2: Ƙirƙirar Rarraba Ƙira
• Mataki 3: Bayar da Wuraren Wuta da Yankuna
• Mataki 4: Ƙara Mai Kula da Kanfigareshan Kanfigareshan Waje na IP
• Mataki na 5: Ma'anar Mutane
• Mataki 6: Ƙirƙirar Bita
• Mataki na 7: Haɗa Bitar Tushen
• Mataki na 8: Ana Shirya Bita Bita na Ayyukan PR
• Mataki 9: Shirye-shiryen Hukumar

Mataki 1: Farawa
Don kwafi ƙirar tunani files zuwa yanayin aikin ku kuma ku haɗa ƙirar lebur ɗin blinking_led:

1. Ƙirƙiri adireshi a cikin mahallin aikin ku, agilex_pcie_devkit_blinking_led_pr.
2. Kwafi koyawa da aka zazzage/agilex_pcie_devkit_blinking_led/ babban babban fayil mai lebur zuwa kundin adireshi, agilex_pcie_devkit_blinking_led_pr.
3. A cikin Intel Quartus Prime Pro Edition software, danna File ➤ Buɗe Project kuma zaɓi blinking_led.qpf.
4. Don ƙarin bayani game da tsarin ƙira, danna Gudanarwa ➤ Fara ➤ Fara Analysis & Synthesis. A madadin, a layin umarni, gudanar da umarni mai zuwa: quartus_syn blinking_led -c blinking_led

Ƙirƙirar Rarraba Ƙira

Dole ne ku ƙirƙiri ɓangarorin ƙira don kowane yanki na PR wanda kuke son sake fasalin wani yanki. Matakai masu zuwa suna ƙirƙirar ɓangaren ƙira don misalin u_blinking_led.

Ƙirƙirar Ƙungiyoyin Ƙira

1. Danna dama-dan misali u_blinking_led a cikin Project Navigator kuma danna Partition Design ➤ Reconfigurable. Alamar ɓangaren ƙira yana bayyana kusa da kowane misali wanda aka saita azaman bangare.
2. Danna Ayyuka ➤ Tagan Rarraba Tsara. Tagar tana nuna duk ɓangarorin ƙira a cikin aikin.
3. Shirya sunan bangare a cikin Tagar Rukunin Ƙira ta danna sunan sau biyu. Don wannan ƙirar ƙira, sake suna sunan ɓangaren zuwa pr_partition
   • Lura: Lokacin da ka ƙirƙiri bangare, Intel Quartus Prime software ta atomatik yana haifar da sunan bangare, dangane da sunan misali da hanyar matsayi. Wannan tsoho sunan bangare na iya bambanta da kowane misali.
4. Don fitar da ƙaƙƙarfan yanki a tsaye daga harsashen bita na tushe, danna shigarwa sau biyu don tushen_partition a cikin Fitar da Ƙarshe na Post. File shafi, kuma rubuta blinking_led_static. gdb.

Ana Fitar da Hoton Ƙarshe na Ƙarshe a Tagar Rarraba ƘiraTabbatar da cewa blinking_led.qsf ya ƙunshi ayyuka masu zuwa, daidai da ɓangaren ƙira da za a sake daidaitawa:

Bayanai masu alaƙa
"Ƙirƙirar Ƙirar Ƙira" a cikin Intel Quartus Prime Pro Edition Jagorar Mai amfani: Sake fasalin Sashe

Bayar da Wuri da Yanki don Rarraba PR
Ga kowane bita na tushe da kuka ƙirƙira, ƙirar ƙira ta PR tana sanya ainihin ainihin mutum a cikin yanki na PR ɗin ku. Don ganowa da sanya yankin PR a cikin tsarin bene na na'urar don sake fasalin tushe:

1. Danna dama-dan misali u_blinking_led a cikin Project Navigator kuma danna Logic Lock Region ➤ Ƙirƙiri Sabon Logic Lock Region. Yankin yana bayyana akan Window Logic Lock Regions.
2. Dole ne yankin da aka sanya ku ya ƙunshi ma'anar blinking_led. Zaɓi yankin sanyawa ta hanyar gano kumburi a cikin Tsarin Chip. Danna dama sunan yankin u_blinking_led a cikin Tagar Logic Lock Regions kuma danna

Nemo Node ➤ Gano wuri a cikin Mai tsara Chip. Yankin u_blinking_led mai launi ne

Wurin Node Mai Tsara Chip don blinking_led

1. A cikin taga Logic Lock Regions, saka haɗin haɗin gwiwar yanki a cikin ginshiƙi na asali. Asalin ya yi daidai da ƙananan kusurwar hagu na yankin. Don misaliample, don saita yanki mai daidaitawa tare da (X1 Y1) daidaitawa azaman (163 4), saka Asalin azaman X163_Y4. Software na Intel Quartus Prime yana ƙididdige haɗin kai ta atomatik (X2 Y2) (saman-dama) don yankin sanyawa, dangane da tsayi da faɗin da kuka ayyana.
   • Lura: Wannan koyawa tana amfani da haɗin gwiwar (X1 Y1) - (163 4), da tsawo da faɗin 20 don yankin sanyawa. Ƙayyade kowane ƙima don yankin sanyawa. Tabbatar cewa yankin ya rufe dabarar kyaftawar ido.
2. Kunna Zaɓuɓɓukan Adana da Mahimmanci-kawai.
3. Danna Zaɓin Yankin Hanyar Sau biyu. Akwatin maganganu na Logic Lock Routing Region ya bayyana.
4. Zaɓi Kafaffen tare da faɗaɗa don nau'in Roting. Zaɓin wannan zaɓin yana sanya tsayin faɗaɗa ta atomatik 2.
   • Lura: Dole ne yankin da ake tuƙi ya fi yankin da ake sanyawa girma, don samar da ƙarin sassauci ga Fitter lokacin da injin ke bi da mutane daban-daban.

Tagar Yankunan Logic LogicTabbatar cewa blinking_led.qsf ya ƙunshi ayyuka masu zuwa, daidai da shirin ku na ƙasa:

Bayanai masu alaƙa
"Floorplan the Partial Reconfiguration Design" a cikin Intel Quartus Prime Pro Edition Jagorar Mai amfani: Sake daidaitawa

Ƙara Mai sarrafa Sake Tsara Sashe na Waje Mai Kula da Kanfigareshan Tsarin Intel FPGA IP
Sake fasalin Sake Tsari na Waje Mai Kula da Kanfigareshan Waje na Intel FPGA IP musaya tare da toshe sarrafa Intel Agilex PR don sarrafa tushen bitstream. Dole ne ku ƙara wannan IP zuwa ƙirar ku don aiwatar da saitin waje. Bi waɗannan matakan don ƙara Mai sarrafa Kanfigareshan Tsare-tsare na Waje
Intel FPGA IP zuwa aikin ku:

1. Nau'in Sake daidaitawa na Sashe a cikin filin bincike na Catalog na IP (Kayan aiki ➤ Kasuwar IP).
2. Danna Sau biyu Mai Sarrafa Sake Tsara Sashe na Waje Mai Kula da Kanfigareshan Tsarin Intel FPGA IP.
3. A cikin akwatin maganganu Ƙirƙirar IP Variant, rubuta external_host_pr_ip azaman File suna, sa'an nan kuma danna Create. Editan siga ya bayyana.
4. Don Ƙarfafa ma'auni mai aiki, zaɓi Kashe (tsarin saitin). Lokacin da kuke buƙatar amfani da wannan siginar, zaku iya canza saitin zuwa Kunnawa.

Kunna Ma'aunin Mutuwar Mutuƙar Aiki a cikin Editan Sigar

1. Danna File ➤ Ajiye kuma fita daga editan sigar ba tare da samar da tsarin ba. Editan sigar yana haifar da bambancin IP na waje_host_pr_ip.ip file kuma ya kara da file zuwa aikin kyaftawar ido. AN 991: Sake daidaitawa na ɓangarori ta hanyar Fin ɗin Kanfigareshan (Mai watsa shiri na waje) Tsarin Magana 750856 | 2022.11.14 AN 991:
   • Lura:
   • a. Idan kana kwafin external_host_pr_ip.ip file daga pr directory, da hannu shirya blinking_led.qsf file don haɗa layin mai zuwa: set_global_assignment -name IP_FILE pr_ip.ip
   • b. Sanya IP_FILE aiki bayan SDC_FILE ayyuka (blinking_led. dc) a cikin blinking_led.qsf file. Wannan oda yana tabbatar da takurawa da ya dace na Babban Sake Tsare Tsare-Tsare na IP core.
   • Lura: Don gano agogo, .sdc file don PR IP dole ne ya bi kowane .sdc wanda ke ƙirƙirar agogon da tushen IP ke amfani da shi. Kuna sauƙaƙe wannan odar ta hanyar tabbatar da cewa .ip file don PR IP core yana bayyana bayan kowane .ip files ko .sdc files da kuke amfani da su don ayyana waɗannan agogo a cikin .qsf file don bitar aikin ku na Intel Quartus Prime. Don ƙarin bayani, koma zuwa Jagoran Mai amfani na Magani na Sake Tsara Sashe na IP.

Ana ɗaukaka Ƙirar Babban-Mataki

Don sabunta top.sv file tare da misalin PR_IP:

1. Don ƙara misalin waje_host_pr_ip zuwa ƙirar matakin sama, ba da ra'ayin waɗannan tubalan lambar a saman top.sv file:

Ma'anar Mutane
Wannan ƙirar ƙira ta bayyana mutane daban-daban guda uku don ɓangaren PR guda ɗaya. Don ayyana da haɗa mutane a cikin aikin ku:

1. Ƙirƙiri SystemVerilog guda uku files, blinking_led.sv, blinking_led_slow.sv, da blinking_led_empty.sv a cikin kundin adireshin ku na mutane uku.

Mutane Zane Na Magana

Lura:

• blinking_led.sv ya riga ya kasance a matsayin ɓangare na files ka kwafi daga flat/ sub-directory. Kuna iya sake amfani da wannan kawai file.
• Idan ka ƙirƙiri SystemVerilog files daga Intel Quartus Prime Text Editan, musaki Ƙara file zuwa zaɓin aikin na yanzu, lokacin adanawa files.

Ƙirƙirar Bita

Gudun ƙira na PR yana amfani da fasalin fasalin aikin a cikin Intel Quartus Prime software. Ƙirar ku ta farko ita ce bita ta tushe, inda kuka ayyana iyakoki na yanki a tsaye da yankunan da za a sake daidaita su akan FPGA. Daga bita na tushe, kuna ƙirƙira bita-da-kulli da yawa. Waɗannan sake dubawa sun ƙunshi aiwatarwa daban-daban don yankunan PR. Koyaya, duk bita na aiwatar da PR suna amfani da jeri na sama-sama da sakamako iri ɗaya daga bita na tushe. Don haɗa ƙirar PR, dole ne ku ƙirƙiri bita na aiwatar da PR ga kowane mutum. Bugu da kari, dole ne ku sanya nau'ikan bita ga kowane bita. Nau'o'in bita da ke akwai:

• Sake fasalin ɓangarori - Tushe
• Sake fasalin wani ɓangare - Aiwatar da Mutum

Tebu mai zuwa yana lissafin sunan bita da nau'in bita ga kowane bita:

Bita Sunaye da Nau'o'in

Sunan Bita	Nau'in Bita
kyaftawa_led.qsf	Sake fasalin ɓangarori - Tushe
blinking_led_default.qsf	Sake fasalin wani ɓangare - Aiwatar da Mutum
blinking_led_slow.qsf	Sake fasalin wani ɓangare - Aiwatar da Mutum
kyaftawa_led_empty.qsf	Sake fasalin wani ɓangare - Aiwatar da Mutum

Saita Nau'in Bita na Tushen

1. Danna Project ➤ Bita.
2. A cikin Sunan Bita, zaɓi bita na blinking_led, sannan danna Saita Yanzu.
3. Danna Aiwatar. Bita na blinking_led yana nunawa azaman bita na yanzu.
4. Don saita Nau'in Bita don blinking_led, danna Ayyuka ➤ Saituna ➤ Gaba ɗaya.
5. Don Nau'in Bita, zaɓi Sake daidaitawa - Base, sannan danna Ok.
6. Tabbatar cewa kyaftawar_led.qsf yanzu ya ƙunshi aiki mai zuwa: ###blinking_led.qsf set_assignment_global_assignment -name REVISION_TYPE PR_BASE

Ƙirƙirar Bita Bita

1. Don buɗe akwatin maganganu na Revisions, danna Project ➤ Bita.
2. Don ƙirƙirar sabon bita, danna sau biyu < >.
3. A cikin sunan bita, saka blinking_led_default kuma zaɓi blinking_led don Bisa bita.
4. Don nau'in Bita, zaɓi Sake saitin Sashe - PersonaImplementation.

Ƙirƙirar Bita

1. Hakazalika, saita nau'in Bita don blinking_led_slow da blinking_led_empty bita.
2. Tabbatar cewa kowane .qsf file yanzu yana ƙunshe da aiki mai zuwa: set_global_assignment -name REVISION_TYPE PR_IMPL set_intance_assignment -name ENTITY_REBINDING \ place_holder -to u_blinking_led where, place_holder shine tsoho sunan mahaɗan don sabon ƙirƙira PR aiwatar bita.

Bita na Ayyuka

Ƙirƙirar Bita na Tushen

1. Don haɗa tushen bita, danna Sarrafa ➤ Fara Tari. A madadin, umarni mai zuwa yana tattara tushen bita: quartus_sh –flow compile blinking_led -c blinking_led
2. Duba bitstream fileabubuwan da ke haifarwa a cikin fitarwa_files directory.

An ƙirƙira Files

Suna	Nau'in	Bayani
kyaftawa_led.sof	Shirye-shiryen tushe file	Ana amfani da shi don daidaitawar tushe mai cikakken guntu
blinking_led.pr_partition.rbf	PR bitstream file ga mutum mai tushe	An yi amfani da shi don sake fasalin wani yanki na tushen mutum.
blinking_led_static.qdb	.qdb database file	Ƙarshe bayanan bayanai file da ake amfani da shi wajen shigo da yankin tsaye.

Bayanai masu alaƙa

• "Floorplan the Partial Reconfiguration Design" a cikin Intel Quartus Prime Pro Edition Jagorar Mai amfani: Sake daidaitawa
• "Aiwatar da mawuyacin placeplanctions" a cikin Prinas Prinus Prime Mai Gudanar da Mai Amfani

Ana Shiri Bita Bita na Ayyukan PR
Dole ne ku shirya bita na aiwatar da PR kafin ku iya haɗawa da samar da PR bitstream don shirye-shiryen na'ura. Wannan saitin ya haɗa da ƙara yanki na tsaye .qdb file a matsayin tushe file ga kowane aiwatar da bita. Bugu da ƙari, dole ne ku ƙayyade abin da ya dace na yankin PR.

1. Don saita bita na yanzu, danna Project ➤ Bita, zaɓi blinking_led_default azaman sunan Revision, sannan danna Saita Yanzu.
2. Don tabbatar da madaidaicin tushen kowane bita na aiwatarwa, danna Project ➤ Ƙara/Cire Files in Project. Blinking_led.sv file ya bayyana a cikin file jeri.

Fileshafi

1. Maimaita matakai na 1 zuwa 2 don tabbatar da sauran tushen bita na aiwatarwa files:

Sunan Bita na Aiwatarwa	Source File
blinking_led_default	blinking_led.sv
kyaftawa_led_ba komai	blinking_led_empty.sv
kyaftawa_led_slow	blinking_led_slow.sv

1. Don tabbatar da .qdb file hade da tushen bangare, danna Ayyuka ➤ Design Partitions Window. Tabbatar da cewa Database Partition File Yana ƙayyade blinking_led_static.qdb file, ko danna maballin Database sau biyu File cell don tantance wannan file. A madadin, umarni mai zuwa yana sanya wannan file: saita_intance_assignment -suna QDB_FILE_PARTITION \ blinking_led_static.qdb -zuwa |
2. A cikin tantanin halitta Sake ɗaurewa, saka sunan mahaɗan kowane ɓangaren PR wanda kuka canza a cikin bita na aiwatarwa. Don bitar aiwatar da blinking_led_default, sunan mahallin yana blinking_led. A cikin wannan koyawa, kun sake rubuta misalin u_blinking_led daga tushen bita da sabon mahallin blinking_led.

Lura: Ana ƙara aikin sake ɗaure mahaɗar wuri zuwa aikin bita ta atomatik. Koyaya, dole ne ku canza tsoffin sunan mahaɗan a cikin aikin zuwa sunan mahaɗan da ya dace don ƙirar ku.

Sunan Bita na Aiwatarwa	Sake ɗaurin mahalli
blinking_led_default	kyaftawar ido
kyaftawa_led_slow	kyaftawa_led_slow
kyaftawa_led_ba komai	kyaftawa_led_ba komai

Maida mahallin

1. Don haɗa ƙirar, danna Sarrafa ➤ Fara Tari. A madadin, umarni mai zuwa yana haɗa wannan aikin: quartus_sh -flow compile blinking_led -c blinking_led_default
2. Maimaita matakan da ke sama don shirya blinking_led_slow da blinking_led_empty bita: quartus_sh –flow compile blinking_led –c blinking_led_slow quartus_sh –flow compile blinking_led –c blinking_led_empt

Lura: Kuna iya ƙididdige kowane takamaiman saitunan Fitter waɗanda kuke son aiwatarwa yayin haɗar aiwatar da PR. Saitunan ƙayyadaddun ƙayyadaddun ƙayyadaddun saiti suna tasiri kawai dacewar mutum, ba tare da shafar yankin da aka shigo da shi ba.

Shirye-shiryen Hukumar
Wannan koyawa tana amfani da allon ci gaba na Intel Agilex F-Series FPGA akan benci, a wajen ramin PCIe* a cikin injin ku. Kafin ka tsara allon, tabbatar da cewa kun kammala matakai masu zuwa:

1. Haɗa wutar lantarki zuwa kwamitin haɓakawa na Intel Agilex F-Series FPGA.
2. Haɗa Kebul na Zazzagewar Intel FPGA tsakanin tashar USB na PC ɗinku da tashar USB ta Intel FPGA Zazzagewar USB akan allon haɓakawa.

Don gudanar da ƙira akan kwamitin haɓakawa na Intel Agilex F-Series FPGA:

1. Bude Intel Quartus Prime software kuma danna Tools ➤ Programmer.
2. A cikin Programmer, danna Saitin Hardware kuma zaɓi USB-Blaster.
3. Danna Gane Auto kuma zaɓi na'urar, AGFB014R24AR0.
4. Danna Ok. Software na Intel Quartus Prime yana ganowa kuma yana sabunta Programmer tare da na'urorin FPGA guda uku a kan allo.
5. Zaɓi na'urar AGFB014R24AR0, danna Canja File sannan a ɗora blinking_led_default.sof file.
6. Kunna Shirin/Sanya don blinking_led_default.sof file.
7. Danna Fara kuma jira sandar ci gaba don isa 100%.
8. Lura da fitilun da ke kan allo suna kiftawa a mitar guda ɗaya da ƙirar ƙirar asali na asali.
9. Don tsara yankin PR kawai, danna dama da blinking_led_default.sof file a cikin Programmer kuma danna Add PR Programming File.
10. Zaɓi blinking_led_slow.pr_partition.rbf file.
11. Kashe Shirin/Sanya don blinking_led_default.sof file.
12. Kunna Shirin/Sanya don blinking_led_slow.pr_partition.rbf file kuma danna Fara. A kan allo, lura da LED[0] da LED[1] suna ci gaba da kiftawa. Lokacin da sandar ci gaba ta kai 100%, LED[2] da LED[3] suna kyaftawa a hankali.
13. Don sake tsara yankin PR, danna-dama .rbf file a cikin Programmer kuma danna Canja PR Programing File.
14. Zaɓi .rbf files ga sauran mutane biyu su lura da halin da ake ciki a kan allo. Ana loda blinking_led_default.rbf file yana sa LEDs suyi ƙiftawa a takamaiman mitar, kuma suna loda blinking_led_empty.rbf file yana sa LEDs su tsaya ON.

Shirye-shiryen Intel Agilex F-Series FPGA Development BoardGudun Gwajin Hardware

Jerin masu zuwa suna bayyana kwararar gwajin ƙirar kayan masarufi.
Intel Agilex Na'urar Mai watsa shiri na waje Saitin Hardware

Shirya Mataimakin FPGA (Mai watsa shiri na waje)
Jeri mai zuwa yana bayyana shirye-shiryen FPGA mai taimako wanda ke aiki azaman mai watsa shirye-shiryen PR na waje:

1. Ƙayyade saitin dubawar yawo Avalon wanda yayi daidai da yanayin da kuka zaɓa (x8, x16, ko x32).
2. Ƙaddamar da dandali ta hanyar tsara mataimaki FPGA ta amfani da Intel Quartus Prime Programmer da haɗin haɗin kebul.
3. Yin amfani da FPGA mai taimako, karanta CONF_DONE da AVST_READY sigina. CONF_DONE yakamata ya zama 0, AVST_READY yakamata ya zama 1. Ma'ana mai tsayi akan wannan fil yana nuna SDM a shirye take don karɓar bayanai daga ma'aikacin waje. Wannan fitarwa wani bangare ne na SDM I/O.

Lura: Fitin CONF_DONE yana sigina mai masaukin baki na waje cewa canja wurin bitstream ya yi nasara. Yi amfani da waɗannan sigina kawai don saka idanu cikakken tsarin daidaita guntu. Koma zuwa Jagorar Mai amfani Kan Kanfigareshan Intel Agilex don ƙarin bayani akan wannan fil.

Shirya DUT FPGA tare da Cikakken Chip SOF ta hanyar Mai watsa shiri na Waje. File (.sof) ta amfani da mai watsa shiri Avalon streaming interface:

1. Rubuta cikakken guntu bitstream a cikin ƙwaƙwalwar waje na DDR4 na mataimaki FPGA (mai masaukin waje).
2. Saita DUT FPGA tare da cikakken guntu .sof ta amfani da madaidaicin rafi na Avalon (x8, x16, x32).
3. Karanta halin DUT FPGA siginar daidaitawa. CONF_DONE ya kamata ya zama 1, AVST_READY ya zama 0.

Ƙayyadaddun ƙayyadaddun lokaci: Sashe na sake daidaitawa na waje Mai sarrafa Intel FPGA IP

Shirya DUT FPGA tare da Mutum na Farko ta hanyar Mai watsa shiri na waje

1. Aiwatar da daskare a yankin PR da aka yi niyya a cikin DUT FPGA.
2. Amfani da Intel Quartus Prime System Console, jadadda pr_request don fara sake fasalin ɓangaren. AVST_READY yakamata ya zama 1.
3. Rubuta farkon PR persona bitstream cikin ƙwaƙwalwar waje na DDR4 na mataimaki FPGA (mai masaukin waje).
4. Amfani da Avalon streaming interface (x8, x16, x32), sake saita DUT FPGA tare da farkon mutum bitstream.
5. Don duba halin PR, danna Kayan aiki ➤ System Console don ƙaddamar da Console na System. A cikin System Console, saka idanu da halin PR:
   • pr_error shine 2-sake daidaitawa a cikin tsari.
   • pr_error shine 3 - sake fasalin ya cika.
6. Aiwatar cire daskarewa akan yankin PR a cikin DUT FPGA.

Lura: Idan kuskure ya faru yayin aikin PR, kamar gazawar sigar duba ko duba izini, aikin PR ya ƙare.

Bayanai masu alaƙa

• Jagorar Mai Amfani da Kanfigareshan Intel Agilex
• Jagorar mai amfani da Quartus Prime Pro Edition: Kayan aikin gyara kuskure

Tarihin Bita na Daftarin aiki don AN 991: Sake Tsara Sashe ta hanyar Tsarin Kanfigareshan (Mai watsa shiri na waje) Tsarin Magana don Hukumar Ci gaban FPGA na Intel Agilex F-Series

Sigar Takardu	Intel Quartus Prime Version	Canje-canje
2022.11.14	22.3	• Sakin farko.

AN 991: Sake fasalin ɓangarori ta hanyar Fim ɗin Kanfigareshan (Mai watsa shiri na waje) Tsararren Magana: don Intel Agilex F-Series FPGA Development Board

Amsoshi ga Manyan FAQs:

• Q Menene PR ta hanyar fil ɗin sanyi?
• A Kanfigareshan Mai watsa shiri na waje a shafi na 3
• Q Menene nake buƙata don wannan ƙirar tunani?
• A Bukatun Tsara Nasiha a shafi na 6
• Q A ina zan iya samun ƙirar tunani?
• A Bukatun Tsara Nasiha a shafi na 6
• Q Ta yaya zan yi PR ta hanyar daidaitawa na waje?
• A Tafiyar Tsarin Magana akan shafi na 6
• Q Menene mutum na PR?
• A Ma'anar Mutane a shafi na 11
• Q Ta yaya zan tsara allon?
• A Shirya Hukumar a shafi na 17
• Q Menene abubuwan da aka sani na PR da iyakancewa?
• A Dandalin Taimakon Intel FPGA: PR
• Q Kuna da horo akan PR?
• A Katalogin Koyarwar Fasaha ta Intel FPGA

Sigar Kan layi Aika Amsa

• ID: 750856
• Siga: 2022.11.14

Takardu / Albarkatu

intel 750856 Agilex FPGA Development Board [pdf] Jagorar mai amfani 750856, 750857, 750856 Agilex FPGA Development Board, Agilex FPGA Development Board, FPGA Development Board, Board Development Board, Board.

Magana

• Manual mai amfani