I-F-Tile JESD204C Intel FPGA IP Design Example

Mayelana ne-F-Tile JESD204C Intel® FPGA IP Design Example Umhlahlandlela Womsebenzisi

Lo mhlahlandlela womsebenzisi unikeza izici, imihlahlandlela yokusebenzisa, nencazelo enemininingwane mayelana ne-ex designampi-les ye-F-Tile JESD204C Intel® FPGA IP isebenzisa amadivayisi we-Intel Agilex™.

Izilaleli Ezihlosiwe

Lo mbhalo uhloselwe:

• Umklami wezakhiwo ukwenza ukukhetha kwe-IP phakathi nesigaba sokuhlela ukwakheka kwesistimu
• Abaklami bezingxenyekazi zekhompuyutha lapho behlanganisa i-IP ekwakhiweni kweleveli yesistimu yabo
• Onjiniyela bokuqinisekisa ngesikhathi sokulingisa izinga lesistimu nesigaba sokuqinisekisa ihadiwe

Imibhalo Ehlobene
Ithebula elilandelayo libala eminye imibhalo eyizethenjwa ehlobene ne-F-Tile JESD204C Intel FPGA IP.

Ithebula 1. Imibhalo Ehlobene

Ireferensi	Incazelo
F-Tile JESD204C Intel FPGA IP Umhlahlandlela Womsebenzisi	Ihlinzeka ngolwazi mayelana ne-F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Intel FPGA IP Amanothi okukhishwa	Ifaka kuhlu izinguquko ezenzelwe i-F-Tile JESD204C F-Tile JESD204C ekukhishweni okuthile.
Ishidi ledatha yedivayisi ye-Intel Agilex	Lo mbhalo uchaza izici zikagesi, izici zokushintsha, ukucaciswa kokucushwa, kanye nesikhathi samadivayisi we-Intel Agilex.

Ama-Acronyms kanye neGlossary

Ithebula 2. Uhlu Lwezifinyezo

Isifinyezo	Ukunwetshwa
I-LEMC	Iwashi Le-Multiblock Elandisiwe Yasendaweni
FC	Izinga lewashi lozimele
I-ADC	I-Analog kuya ku-Digital Converter
I-DAC	I-Digital kuya ku-Analog Converter
I-DSP	Iphrosesa Yesiginali Yedijithali
TX	I-Transmitter
RX	Umamukeli

Isifinyezo	Ukunwetshwa
I-DLL	Isendlalelo sesixhumanisi sedatha
I-CSR	Irejista yokulawula nesimo
I-CRU	Iwashi futhi Setha Kabusha Iyunithi
I-ISR	Ukuphazanyiswa Kwenqubo Yesevisi
I-FIFO	Okokuqala-In-First-out
I-SERDES	I-serializer ye-Deserializer
ECC	Iphutha Lokulungisa Ikhodi
I-FEC	Phambili Iphutha Ukulungiswa
I-SERR	Ukutholwa Kwephutha Elilodwa (ku-ECC, kuyalungiseka)
I-DERR	Ukutholwa Kwephutha Eliphindwe Kabili (ku-ECC, kuyabulala)
I-PRBS	I-Pseudorandom ukulandelana kanambambili
I-MAC	Isilawuli Sokufinyelela Kwemidiya. I-MAC ifaka i-sublayer yephrothokholi, isendlalelo sezokuthutha, nesendlalelo sesixhumanisi sedatha.
I-PHY	Ungqimba Lomzimba. I-PHY ngokuvamile ihlanganisa isendlalelo esibonakalayo, i-SERDES, abashayeli, abamukeli kanye ne-CDR.
PCS	Isendlalelo esingaphansi sekhodi ebonakalayo
I-PMA	Okunamathiselwe Okumaphakathi Okungokomzimba
I-RBD	Ukulibaziseka kwe-RX Buffer
UI	Isikhawu seyunithi = ubude be-serial bit
Inani le-RBD	I-RX Buffer Ukubambezeleka kwakamuva komzila wokufika
Ukushintsha kwe-RBD	Ithuba lokukhululwa kwe-RX Buffer Libambezelekile
SH	Vumelanisa unhlokweni
TL	Isendlalelo sezokuthutha
I-EMIB	Ibhuloho elishumekiwe le-Multi-die Interconnect

Ithebula 3. Uhlu Lwamagama Amagama

Ithemu	Incazelo
Idivayisi yokuguqula	I-ADC noma i-DAC converter
Idivayisi Enengqondo	I-FPGA noma i-ASIC
Octet	Iqembu lamabhithi angu-8, asebenza njengokufakwayo kusifaki khodi esingu-64/66 kanye nokuphuma kusikhiphi khodi.
Nibble	Isethi yamabhithi angu-4 okuyiyunithi eyisisekelo yokusebenza kwezicaciso ze-JESD204C
Vimba	Uphawu lwe-66-bit olukhiqizwe uhlelo lombhalo wekhodi we-64/66
Isilinganiso Somugqa	Izinga ledatha elisebenzayo lesixhumanisi somkhiqizo Izinga Lomugqa Womzila = (Mx Sx N'x 66/64 x FC) / L
Xhumanisa Iwashi	Iwashi Lesixhumanisi = Izinga Lomugqa Womzila/66.
Uhlaka	Isethi yama-octet alandelanayo lapho indawo ye-octet ngayinye ingabonakala khona ngokubhekisela kusignali yokuqondisa uhlaka.
Iwashi lozimele	Iwashi lesistimu elisebenza ngenani lozimele, okufanele libe iwashi lesixhumanisi elingu-1x no-2x.

Ithemu	Incazelo
Sampkancane ngewashi lozimele	Sampkancane ngewashi ngalinye, inani elingu-sampiwashi elincane lewashi ledivayisi yokuguqula.
I-LEMC	Iwashi langaphakathi elisetshenziselwa ukuqondanisa umngcele we-multiblock enwetshiwe phakathi kwemizila kanye nezithenjwa zangaphandle (SYSREF noma i-Subclass 1).
Isikhwanyana 0	Akukho usekelo lwe-deterministic latency. Idatha kufanele ikhishwe ngokushesha kulayini ukuze kulayini wedeski kumamukeli.
Isikhwanyana 1	Ukubambezeleka kokunquma kusetshenziswa i-SYSREF.
Isixhumanisi se-Multipoint	Izixhumanisi eziphakathi kwedivayisi enamadivayisi angu-2 noma ngaphezulu okuguqula.
64B / 66B Encoding	Ikhodi yomugqa emepha idatha yamabhithi angu-64 kuya kumabhithi angu-66 ukuze kwakheke ibhulokhi. Isakhiwo sedatha yezinga lesisekelo siyibhulokhi eqala ngesihloko sokuvumelanisa esingu-2-bit.

Ithebula 4. Izimpawu

Ithemu	Incazelo
L	Inombolo yemigqa ngedivayisi ngayinye yokuguqula
M	Inombolo yeziguquli ngedivayisi ngayinye
F	Inombolo yama-octet kuhlaka ngalunye emzileni owodwa
S	Inombolo ye-sampkudluliswa kancane ngesiguquli esisodwa ngomjikelezo wozimele
N	Ukulungiswa kokuguqula
N'	Isamba senani lamabhithi ngesample ngefomethi yedatha yomsebenzisi
CS	Inani lamabhithi okulawula ukuguqulwa ngakunye sample
CF	Inombolo yamagama okulawula ngesikhathi sewashi lozimele ngesixhumanisi ngasinye
HD	Ifomethi yedatha yomsebenzisi Eminingi Ephakeme
E	Inombolo yama-multiblock ku-multiblock enwetshiwe

I-F-Tile JESD204C Intel FPGA IP Design Exampne-Quick Start Guide

Umklamo we-F-Tile JESD204C Intel FPGA IP exampi-les yamadivayisi we-Intel Agilex ifaka ibhentshi elilingisayo kanye nedizayini yehadiwe esekela ukuhlanganiswa nokuhlolwa kwehadiwe.
Ungakwazi ukukhiqiza i-F-Tile JESD204C exampkancane ngekhathalogi ye-IP kusofthiwe ye-Intel Quartus® Prime Pro Edition.

Umfanekiso 1. Ukuthuthukiswa Stages ye-Design Example

I-Design Example Block Diagram

Umfanekiso 2. F-Tile JESD204C Design Example High-level Block Diagram

Umklamo example iqukethe amamojula alandelayo:

• Uhlelo Lomklami Wenkundla
  • I-F-Tile JESD204C Intel FPGA IP
  • JTAG ukuya ebhulohweni le-Avalon Master
  • Isilawuli se-Parallel I/O (PIO).
  • I-Serial Port Interface (SPI)—imoduli eyinhloko— IOPLL
  • Ijeneretha ye-SYSREF
  • Example Design (ED) Control CSR
  • Setha kabusha izilandeleli
• Isistimu ye-PLL
• Ijeneretha yephethini
• Isihloli sephethini

Ithebula 5. Idizayini Example Amamojula

Izingxenye	Incazelo
Uhlelo Lomklami Wenkundla	Uhlelo Lomklami Wengxenyekazi luqinisekisa indlela yedatha ye-F-Tile JESD204C IP kanye nama-peripherals asekelayo.
I-F-Tile JESD204C Intel FPGA IP	Lolu hlelo olungaphansi lwe-Platform Designer luqukethe i-TX kanye ne-RX F-Tile JESD204C IPs ehlanganiswe ne-duplex PHY.
JTAG ukuya ebhulohweni le-Avalon Master	Leli bhuloho linikeza ukufinyelela komsingathi wekhonsoli yesistimu ku-IP efakwe kumephu yenkumbulo ekwakhiweni nge-JTAG esibonakalayo.
Isilawuli se-Parallel I/O (PIO).	Lesi silawuli sinikeza isixhumi esibonakalayo esinemephu yememori ye-sampamachweba we-Li/O wenhloso ejwayelekile yokushayela.
SPI master	Le mojula iphatha ukudluliswa kwe-serial kwedatha yokumisa kusixhumi esibonakalayo se-SPI ekugcineni kwesiguquli.
Ijeneretha ye-SYSREF	Ijeneretha ye-SYSREF isebenzisa iwashi lokuxhumanisa njengewashi lesithenjwa futhi ikhiqiza ama-SYSREF pulses ye-F-Tile JESD204C IP. Qaphela: Lo mklamo exampI-le isebenzisa ijeneretha ye-SYSREF ukuze ibonise ukuqaliswa kwesixhumanisi se-IP esiyiduplex se-F-Tile JESD204C. Kuhlelo lokusebenza lweleveli yesistimu ye-F-Tile JESD204C subclass 1, kufanele ukhiqize i-SYSREF emthonjeni ofanayo njengewashi ledivayisi.
I-IOPLL	Lo mklamo exampI-le isebenzisa i-IOPLL ukuze ikhiqize iwashi lomsebenzisi lokudlulisa idatha ku-F-Tile JESD204C IP.
I-ED Control CSR	Le mojula inikeza ukulawula kokutholwa kwe-SYSREF nesimo, nokulawula iphethini yokuhlola kanye nesimo.
Setha kabusha izilandeleli	Lo mklamo example iqukethe abalandelanayo abangu-2: Setha kabusha Ukulandelana 0—Iphatha ukusetha kabusha kusizinda sokusakaza-bukhoma se-TX/RX Avalon®, isizinda esinemephu yememori ye-Avalon, i-core PLL, TX PHY, TX core, kanye nejeneretha ye-SYSREF. Setha Kabusha Uchungechunge 1—Iphatha ukusetha kabusha ku-RX PHY kanye ne-RX core.
Isistimu ye-PLL	Umthombo wewashi oyinhloko we-F-tile hard IP kanye nokuwela i-EMIB.
Ijeneretha yephethini	Ijeneretha yephethini ikhiqiza i-PRBS noma i-ramp iphethini.
Isihloli sephethini	Isihloli sephethini siqinisekisa i-PRBS noma i-ramp iphethini itholiwe, futhi ihlaba umkhosi iphutha uma ithola ukungafani kwedatha sample.

Izidingo Zesoftware

I-Intel isebenzisa isofthiwe elandelayo ukuhlola i-ex designampOkulandelayo ohlelweni lwe-Linux:

• Isoftware ye-Intel Quartus Prime Pro Edition
• Questa*/ModelSim* noma VCS*/VCS MX isifanisi

Ikhiqiza Umklamo

Ukukhiqiza i-design example kusuka kusihleli sepharamitha ye-IP:

1. Dala iphrojekthi eqondise umndeni wedivayisi ye-Intel Agilex F-tile bese ukhetha idivayisi oyifunayo.
2. Kukhathalogi ye-IP, Amathuluzi ➤ Ikhathalogi ye-IP, khetha i-F-Tile JESD204C Intel FPGA IP.
3. Cacisa igama lezinga eliphezulu kanye nefolda yokuhluka kwakho kwe-IP yangokwezifiso. Chofoza okuthi KULUNGILE. Umhleli wepharamitha wengeza izinga eliphezulu elithi .ip file kuphrojekthi yamanje ngokuzenzakalela. Uma ucelwa ukuthi ungeze ngokwakho i-.ip file kuphrojekthi, chofoza Iphrojekthi ➤ Engeza/Susa Files kuphrojekthi yokwengeza i file.
4. Ngaphansi kwe-Example Design ithebhu, cacisa umklamo exampamapharamitha njengoba kuchazwe ku-Design Example Amapharamitha.
5. Chofoza okuthi Khiqiza Isibample Design.

Isoftware ikhiqiza yonke imiklamo files kuma-sub-directory. Lezi files ziyadingeka ukuqalisa ukulingisa nokuhlanganiswa.

I-Design Example Amapharamitha
Umhleli wepharamitha we-F-Tile JESD204C Intel FPGA IP uhlanganisa i-Example Dizayini ithebhu ukuze ucacise amapharamitha athile ngaphambi kokukhiqiza i-ex yokuklamaample.

Ithebula 6. Amapharamitha ku-ExampIthebhu Yokuklama

Ipharamitha	Izinketho	Incazelo
Khetha i-Design	Ukulawulwa Kwekhonsoli Yesistimu Lutho	Khetha isilawuli sekhonsoli yesistimu ukuze ufinyelele i-ex yedizayiniample idatha ngokusebenzisa ikhonsoli yesistimu.
Ukulingisa	Khanyisa cisha	Vula ukuze i-IP ikhiqize okudingekayo files yokulingisa umklamo example.
I-synthesis	Khanyisa cisha	Vula ukuze i-IP ikhiqize okudingekayo files yokuhlanganiswa kwe-Intel Quartus Prime kanye nokuboniswa kwehadiwe.
Ifomethi ye-HDL (okulingisa)	I-Verilog I-VDHL	Khetha ifomethi ye-HDL ye-RTL files sokulingiswa.
Ifomethi ye-HDL (okwe-synthesis)	I-Verilog kuphela	Khetha ifomethi ye-HDL ye-RTL files for synthesis.

Ipharamitha	Izinketho	Incazelo
Khiqiza imojuli ye-SPI enezintambo ezi-3	Khanyisa cisha	Vula ukuze unike amandla isixhumi esibonakalayo se-SPI yezintambo ezi-3 esikhundleni sezintambo ezi-4.
Imodi ye-Sysref	Isibhamu esisodwa Izikhathi ezithile I-Gapped periodic	Khetha ukuthi ingabe ufuna ukuqondanisa kwe-SYSREF kube imodi yokushaya okukodwa, ngezikhathi ezithile, noma izikhathi ezinegebe, ngokusekelwe ezidingweni zakho zedizayini kanye nokuguquguquka kwesikhathi. Ukushutha okukodwa—Khetha le nketho ukuze unike amandla i-SYSREF ukuthi ibe imodi yokushaya okukodwa. Inani lebhithi yerejista ye-sysref_ctrl[17] ngu-0. Ngemva kwe-F-Tile JESD204C IP yokusetha kabusha amadesethi, shintsha inani lerejista ye-sysref_ctrl[17] isuke ku-0 iye ku-1, bese iye ku-0, ukuze uthole ukushaya kwe-SYSREF yeshothi eyodwa. I-Periodic—SYSREF kumodi yezikhathi inomjikelezo womsebenzi ongu-50:50. Isikhathi se-SYSREF ngu-E*SYSREF_MULP. I-Gapped periodic—SYSREF inomjikelezo womsebenzi ohlelekayo we-granularity womjikelezo wewashi wesixhumanisi ongu-1. Isikhathi se-SYSREF ngu-E*SYSREF_MULP. Ngokulungiselelwa komjikelezo womsebenzi ongaphandle kwebanga, ibhulokhi yokukhiqiza ye-SYSREF kufanele ilinganise ngokuzenzakalelayo umjikelezo womsebenzi ongu-50:50. Bheka ku- I-SYSREF Ijeneretha ukuze uthole ulwazi olwengeziwe mayelana ne-SYSREF isikhathi.
Khetha ibhodi	Lutho	Khetha ibhodi ye-ex designample. Lutho—Le nketho ayifaki izici zehadiwe ye-ex yedizayiniample. Yonke imisebenzi yephinikhodi izosethwa kumaphini abonakalayo.
Iphethini yokuhlola	I-PRBS-7 I-PRBS-9 I-PRBS-15 I-PRBS-23 Ramp	Khetha iphethini yejeneretha kanye nephethini yokuhlola yokuhlola. Ijeneretha yephethini—JESD204C isekela i-PRBS iphethini generator ngedatha ngayinyeample. Lokhu kusho ukuthi ububanzi bedatha yinketho ye-N+CS. I-PRBS iphethini generator nesihloli ziwusizo ekudaleni idatha sample stimulus yokuhlola futhi ayihambisani nemodi yokuhlola ye-PRBS kusiguquli se-ADC/DAC. Ramp Isikhiqizi Sephethini—Isendlalelo sesixhumanisi se-JESD204C sisebenza ngokujwayelekile kodwa ezokuthutha kamuva ziyakhutshazwa futhi okokufaka okuvela kufomethi kuyazitshwa. Umzila ngamunye udlulisa umfudlana we-octet ofanayo okhuphuka usuka ku-0x00 uye ku-0xFF bese uyaphinda. Ramp ukuhlolwa kwephethini kunikwe amandla yi-prbs_test_ctl. Isihloli Sephethini se-PRBS—JESD204C PRBS scrambler siyazivumelanisa ngokwaso futhi kulindeleke ukuthi uma i-IP core ikwazi ukunquma ukuxhumanisa, imbewu enyakazayo isivele ivumelanisiwe. Imbewu ye-PRBS yokuphenya izothatha ama-octet angu-8 ukuze iqalise yona ngokwayo. Ramp Isihloli Sephethini—I-JESD204C ukuklwebha kuyazivumelanisa ngokwakho futhi kulindeleke ukuthi uma i-IP core ikwazi ukunquma ukuxhumanisa, imbewu enyakazayo isivele ivumelanisiwe. I-octet yokuqala evumelekile ilayishwa njenge-ramp inani lokuqala. Idatha elandelayo kufanele ikhuphuke ifike ku-0xFF futhi idlulele ku-0x00. Ramp isihloli sephethini kufanele sihlole iphethini efanayo kuyo yonke imizila.
Nika amandla i-loopback ye-serial yangaphakathi	Khanyisa cisha	Khetha i-loopback ye-serial yangaphakathi.
Nika amandla i-Command Channel	Khanyisa cisha	Khetha iphethini yesiteshi yomyalo.

Ukwakheka Kwemibhalo
Umklamo we-F-Tile JESD204C example lwemibhalo aqukethe elakhiwe files ye-design exampLes.

Umfanekiso 3. Isakhiwo sohlu lwemibhalo ye-F-Tile JESD204C Intel Agilex Design Example

Ithebula 7. Uhla lwemibhalo Files

Amafolda	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
ukulingisa/umeluleki	modelim_sim.tcl tb_top_waveform.do
ukulingisa/ama-synopsy	vcs vcs_sim.sh tb_top_wave_ed.do vcsmx vcsmx_sim.sh tb_top_wave_ed.do

Ukulingisa i-Design Example Testbench

Umklamo exampI-testbench ilingisa umklamo wakho owenziwe.

Umfanekiso 4. Inqubo

Ukuze ulingise umklamo, yenza lezi zinyathelo ezilandelayo:

1. Shintsha uhla lwemibhalo olusebenzayo lubeample_design_directory>/simulation/ .
2. Emgqeni womyalo, sebenzisa iskripthi sokulingisa. Ithebula elingezansi libonisa imiyalo yokusebenzisa izifanisi ezisekelwayo.

Isifanisi	Umyalo
Questa/ModelSim	vsim -do modelim_sim.tcl
	i-vsim -c -do modelsim_sim.tcl (ngaphandle kwe-Questa/ ModelSim GUI)
I-VCS	sh vcs_sim.sh
I-VCS MX	sh vcsmx_sim.sh

Ukulingisa kugcina ngemilayezo ekhombisa ukuthi ukuqalisa kube yimpumelelo noma cha.

Umfanekiso 5. Ukulingisa Okuphumelelayo
Lesi sibalo sibonisa umlayezo wokulingisa oyimpumelelo wesifanisi se-VCS.

Ukuhlanganisa i-Design Example

Ukuhlanganisa isib sokuhlanganiswa kuphelaample phrojekthi, landela lezi zinyathelo:

1. Qinisekisa ukuhlanganisa idizayini exampisizukulwane sesiphelile.
2. Kuhlelo lwe-Intel Quartus Prime Pro Edition, vula iphrojekthi ye-Intel Quartus Prime Pro Editionample_ design_ directory>/ed/quartus.
3. Kumenyu Yokucubungula, chofoza Qala Ukuhlanganisa.

Incazelo Eningiliziwe Ye-F-Tile JESD204C Design Example

Umklamo we-F-Tile JESD204C exampI-le ibonisa ukusebenza kokusakaza idatha kusetshenziswa imodi ye-loopback.
Ungacacisa izilungiselelo zamapharamitha ozikhethele futhi ukhiqize i-ex yokuklamaample.
Umklamo exampi-le itholakala kuphela ngemodi eyi-duplex kukho kokubili okuhlukile kwe-Base ne-PHY. Ungakhetha i-Base kuphela noma i-PHY kuphela kodwa i-IP izokhiqiza i-ex yomklamoample yakho kokubili i-Base ne-PHY.

Qaphela:  Okunye ukulungiselelwa kwesilinganiso sedatha ephezulu kungase kuhluleke isikhathi. Ukuze ugweme ukwehluleka kwesikhathi, cabanga ukucacisa inani eliphansi lokuphindaphinda iwashi lozimele (FCLK_MULP) kuthebhu yokucushwa yesihleli sepharamitha ye-F-Tile JESD204C Intel FPGA IP.

Izingxenye Zesistimu

Umklamo we-F-Tile JESD204C exampi-le ihlinzeka ngokugeleza kokulawula okusekelwe kusofthiwe esebenzisa iyunithi yokulawula okuqinile ngokusekelwa kwekhonsoli yesistimu noma ngaphandle kwayo.

Umklamo exampi-le inika amandla isixhumanisi esizenzakalelayo kumamodi we-loopback wangaphakathi nangaphandle.

JTAG ukuya e-Avalon Master Bridge
I-JTAG ukuya e-Avalon Master Bridge inikeza ukuxhumana phakathi kwesistimu yokusingatha ukufinyelela i-F-Tile JESD204C IP ebhalwe ngememori kanye nokulawulwa kwe-IP okuzungezile kanye namarejista wesimo nge-J.TAG esibonakalayo.

Umfanekiso 6. Isistimu ene-JTAG ku-Avalon Master Bridge Core

Qaphela:  Iwashi lesistimu kufanele okungenani libe ngu-2X ngokushesha kune-JTAG iwashi. Iwashi lesistimu ngu-mgmt_clk (100MHz) kulesi sib somklamoample.

I-Parallel I/O (PIO) Core
I-parallel input/output (PIO) core ene-interface ye-Avalon inikeza ukusebenzelana kwemephu yenkumbulo phakathi kwembobo yezigqila efakwe kumephu yememori ye-Avalon kanye nezimbobo ze-I/O zenhloso evamile. Izimbobo ze-I/O zixhumeka kumqondo womsebenzisi we-chip, noma kumaphini we-I/O axhumeka kumadivayisi angaphandle kwe-FPGA.

Umfanekiso 7. I-PIO Core enezimbobo zokufaka, izimbobo zokuphuma, kanye nokusekelwa kwe-IRQ
Ngokuzenzakalelayo, ingxenye ye-Platform Designer ikhubaza Ulayini Wokuphazamiseka Kwesevisi (IRQ).

Izimbobo ze-PIO I/O zinikezwa ezingeni eliphezulu le-HDL file (io_ isimo sezimbobo zokufaka, io_ control yezimbobo zokuphuma).

Ithebula elingezansi lichaza ukuxhumana kwesignali yesimo nokulawula izimbobo ze-I/O ekushintsheni kwe-DIP kanye ne-LED kukhithi yokuthuthukisa.

Ithebula 8. Amachweba we-PIO Core I/O

Itheku	Kancane	Isiginali
Imbobo_yangaphandle	0	USER_LED SPI ukuhlela kwenziwe
	31:1	Igodliwe
Ethekwini	0	USER_DIP i-serial loopback yangaphakathi inika amandla Valiwe = 1 Ivuliwe = 0
	1	I-USER_DIP ekhiqizwe yi-FPGA inika amandla i-SYSREF Valiwe = 1 Ivuliwe = 0
	31:2	Igodliwe.

Umphathi we-SPI
Imojuli eyinhloko ye-SPI iyingxenye yoMklami Wenkundla ejwayelekile kumtapo wezincwadi ojwayelekile Wekhathalogi ye-IP. Le mojula isebenzisa iphrothokholi ye-SPI ukwenza lula ukumiswa kweziguquli zangaphandle (ngokwesiboneloample, ADC, DAC, namajeneretha ewashi angaphandle) ngesikhala esihleliwe sokubhalisa ngaphakathi kwalawa madivayisi.

Inkosi ye-SPI ine-interface ye-Avalon enemephu yenkumbulo exhuma ku-Avalon master (JTAG ukuya ebhulohweni eliyinhloko le-Avalon) ngoxhumano lwemephu ye-Avalon lwemephu. Inkosi ye-SPI ithola imiyalelo yokumisa evela kunkosi ye-Avalon.

Imojuli eyinhloko ye-SPI ilawula izigqila ezizimele ze-SPI ezifika kwezingu-32. Izinga le-baud ye-SCLK lilungiselelwe ukuthi libe ngu-20 MHz (lihlukaniswa ngo-5).
Le mojula ilungiselelwe ukuthi ibe nesixhumi esibonakalayo esinezintambo ezingu-4, nobubanzi obungamabhithi angu-24. Uma inketho ye-Generate 3-Wire SPI Module ikhethiwe, imojula eyengeziwe iyafakwa ukuze kuguqulwe ukuphuma kwezintambo ezi-4 ze-SPI master kuya kuzintambo ezi-3.

I-IOPLL
I-IOPLL ikhiqiza iwashi elidingekayo ukuze kukhiqizwe i-frame_clk ne-link_clk. Iwashi eliyireferensi ku-PLL liyalungiseka kodwa lilinganiselwe kuzinga ledatha/isici esingu-33.

• Okokuklama example esekela izinga ledatha elingu-24.33024 Gbps, izinga lewashi le-frame_clk ne-link_clk lingu-368.64 MHz.
• Okokuklama example esekela izinga ledatha elingu-32 Gbps, izinga lewashi le-frame_clk ne-link_clk lingu-484.848 MHz.

Ijeneretha ye-SYSREF
I-SYSREF iyisiginali yesikhathi ebalulekile yeziguquli zedatha ezine-interface ye-F-Tile JESD204C.

Ijeneretha ye-SYSREF ku-ex designampi-le isetshenziselwa injongo yokubonisa yokuqalisa isixhumanisi se-JESD204C IP kuphela. Kuhlelo lokusebenza lweleveli yesistimu ye-JESD204C subclass 1, kufanele ukhiqize i-SYSREF emthonjeni ofanayo njengewashi ledivayisi.

Ku-F-Tile JESD204C IP, isiphindaphindi se-SYSREF (SYSREF_MULP) serejista yokulawula ye-SYSREF sichaza isikhathi se-SYSREF, okuyinani eliphindwe kabili le-n-integer yepharamitha engu-E.

Kufanele uqinisekise i-E*SYSREF_MULP ≤16. Okwesiboneloample, uma u-E=1, ukulungiselelwa okusemthethweni kwe-SYSREF_MULP kufanele kube phakathi kuka-1–16, futhi uma u-E=3, ukulungiselelwa okusemthethweni kwe-SYSREF_MULP kufanele kube phakathi kuka-1–5.

Qaphela:  Uma usetha i-SYSREF_MULP engaphandle kobubanzi, ijeneretha ye-SYSREF izolungisa ukulungiselelwa kokuthi SYSREF_MULP=1.
Ungakhetha ukuthi uyafuna yini ukuthi uhlobo lwe-SYSREF lube i-pulse ye-shot eyodwa, i-periodic, noma i-gapped periodic ngokusebenzisa i-Ex.ample Design ithebhu kusihleli sepharamitha ye-F-Tile JESD204C Intel FPGA IP.

Ithebula 9. ExampIzingxenye ze-Periodic kanye ne-Gapped Periodic SYSREF Counter

E	SYSREF_MULP	ISIKHATHI SE-SYSREF (E*SYSREF_MULP* 32)	Duty Cycle	Incazelo
1	1	32	1..31 (Kuyahlelwa)	I-Gapped Periodic
1	1	32	16 (Kulungisiwe)	Izikhathi ezithile
1	2	64	1..63 (Kuyahlelwa)	I-Gapped Periodic
1	2	64	32 (Kulungisiwe)	Izikhathi ezithile
1	16	512	1..511 (Kuyahlelwa)	I-Gapped Periodic
1	16	512	256 (Kulungisiwe)	Izikhathi ezithile
2	3	19	1..191 (Kuyahlelwa)	I-Gapped Periodic
2	3	192	96 (Kulungisiwe)	Izikhathi ezithile
2	8	512	1..511 (Kuyahlelwa)	I-Gapped Periodic
2	8	512	256 (Kulungisiwe)	Izikhathi ezithile
2	9 (Akukho emthethweni)	64	32 (Kulungisiwe)	I-Gapped Periodic
2	9 (Akukho emthethweni)	64	32 (Kulungisiwe)	Izikhathi ezithile

 

Ithebula 10. Amarejista okulawula e-SYSREF
Ungakwazi ukuphinda ulungiselele kabusha amarejista okulawula e-SYSREF uma isilungiselelo serejista sihlukile kunesilungiselelo osishilo ngenkathi ukhiqiza i-ex design.ample. Lungiselela amarejista e-SYSREF ngaphambi kokuthi i-F-Tile JESD204C Intel FPGA IP iphelelwe ukusethwa kabusha. Uma ukhetha i-generator ye-SYSREF yangaphandle ngokusebenzisa i-
sysref_ctrl[7] irejista bit, ungakwazi ukuziba izilungiselelo zohlobo lwe-SYSREF, isiphindaphinda, umjikelezo wemisebenzi kanye nesigaba.

Amabhithi	Inani elizenzakalelayo	Incazelo
sysref_ctrl[1:0]	2'b00: Isibhamu esisodwa 2'b01: Ngezikhathi I-2'b10: Isikhathi esinezikhala	Uhlobo lwe-SYSREF. Inani elizenzakalelayo lincike ekusethweni kwemodi ye-SYSREF ku- Example Design ithebhu kumhleli wepharamitha ye-F-Tile JESD204C Intel FPGA IP.
sysref_ctrl[6:2]	5 b00001	Isiphindaphindi se-SYSREF. Le nkambu ye-SYSREF_MULP iyasebenza ohlotsheni lwe-SYSREF lwezikhathi ezithile nolunegebe. Kumelwe ulungiselele inani lokuphindaphinda ukuze uqinisekise ukuthi inani le-E*SYSREF_MULP liphakathi kuka-1 kuya ku-16 ngaphambi kokuthi i-F-Tile JESD204C IP iphelelwe ukusetha kabusha. Uma inani elingu-E*SYSREF_MULP lingaphandle kwalobu bubanzi, inani lesiphindaphinda lishintsha ngokuzenzakalelayo libe ngu-5'b00001.
sysref_ctrl[7]	I-Duplex datapath: 1'b1 I-Simplex TX noma i-RX idathapath: 1'b0	Khetha i-SYSREF. Inani elizenzakalelayo lincike esimisweni sendlela yedatha ku-Example Design ithebhu kusihleli sepharamitha ye-F-Tile JESD204C Intel FPGA IP. 0: I-Simplex TX noma i-RX (I-SYSREF Yangaphandle) 1: I-Duplex (I-SYSREF yangaphakathi)
sysref_ctrl[16:8]	9h0	Umjikelezo womsebenzi we-SYSREF lapho uhlobo lwe-SYSREF luyizikhathi ezithile noma lunegebe ngezikhathi ezithile. Kufanele ulungiselele umjikelezo womsebenzi ngaphambi kokuthi i-F-Tile JESD204C IP iphelelwe ukusetha kabusha. Inani eliphakeme = (E*SYSREF_MULP*32)-1 Ngokwesibample: 50% umjikelezo womsebenzi = (E*SYSREF_MULP*32)/2 Umjikelezo wemisebenzi uzenzakalela ube ngu-50% uma ungayilungisi le nkambu yokubhalisa, noma uma ulungiselela inkambu yokubhalisa ibe ngu-0 noma ngaphezulu kwenani eliphakeme elivunyelwe.
sysref_ctrl[17]	1 b0	Ukulawula mathupha uma uhlobo lwe-SYSREF luyishothi eyodwa. Bhala oku-1 ukuze usethe isignali ye-SYSREF phezulu. Bhala u-0 ukuze usethe isignali ye-SYSREF phansi. Udinga ukubhala u-1 bese u-0 ukuze udale ukushaya kwe-SYSREF kumodi yokushutha okukodwa.
sysref_ctrl[31:18]	22h0	Igodliwe.

Setha kabusha Izilandeleli
Lo mklamo example iqukethe abalandelanayo ababili bokusetha kabusha:

• Setha Kabusha Uchungechunge 0—Iphatha ukusetha kabusha kusizinda sokusakaza se-TX/RX Avalon, isizinda esinemephu yememori ye-Avalon, i-core PLL, TX PHY, TX core, kanye nejeneretha ye-SYSREF.
• Setha kabusha Uchungechunge 1—Iphatha ukusetha kabusha ku-RX PHY ne-RX Core.

3-Wire SPI
Le mojula ingakhethwa ukuguqula isixhumi esibonakalayo se-SPI sibe izintambo ezi-3.

Isistimu ye-PLL
I-F-tile inama-PLL amathathu e-on-board system. Lawa ma-PLL esistimu awumthombo wewashi oyinhloko we-IP eqinile (MAC, PCS, ne-FEC) kanye nokuwela kwe-EMIB. Lokhu kusho ukuthi, uma usebenzisa imodi yewashi yesistimu ye-PLL, amabhlogo awawashi iwashi le-PMA futhi awanciki ewashini eliphuma kumongo we-FPGA. Isistimu ngayinye ye-PLL ikhiqiza iwashi elihlotshaniswa nesixhumi esibonakalayo esisodwa sefrikhwensi. Okwesiboneloample, udinga ama-PLL esistimu amabili ukuze usebenzise isixhumi esibonakalayo esisodwa ku-1 GHz nesixhumi esibonakalayo esisodwa ku-500 MHz. Ukusebenzisa isistimu ye-PLL ikuvumela ukuthi usebenzise yonke imizila ngokuzimela ngaphandle koshintsho lwewashi lomzila oluthinta umzila ongumakhelwane.
Uhlelo ngalunye lwe-PLL lungasebenzisa noma yiliphi iwashi elilodwa kwayisishiyagalombili ereferensi ye-FGT. Ama-System PLL angabelana ngewashi lesithenjwa noma abe namawashi ereferensi ahlukile. Isixhumi esibonakalayo ngasinye singakhetha ukuthi iyiphi i-PLL esisebenzisayo, kodwa, uma sesikhethiwe, siyalungiswa, asilungiseki kabusha kusetshenziswa ukumiswa kabusha okuguquguqukayo.

Ulwazi Oluhlobene
I-F-tile Architecture kanye ne-PMA kanye ne-FEC Direct PHY IP User Guide

Ulwazi olwengeziwe mayelana nemodi yewashi yesistimu ye-PLL kumadivayisi we-Intel Agilex F-tile.

Iphethini Generator kanye Checker
Ijeneretha yephethini nesihloli ziwusizo ekudaleni idatha samples kanye nokuqapha ngezinjongo zokuhlola.
Ithebula 11. Ijeneretha Yephethini Esekelwe

Iphethini Generator	Incazelo
PRBS iphethini generator	Umklamo we-F-Tile JESD204C exampI-le PRBS iphethini generator isekela idigri elandelayo yama-polynomials: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp iphethini generator	I-ramp inani lephethini likhuphuka ngo-1 kuwo wonke ama-s alandelayoample ngobubanzi bejeneretha engu-N, futhi igingqika iye ku-0 lapho wonke amabhithi ku-sampngi 1. Nika amandla i-ramp ijeneretha yephethini ngokubhala u-1 kuya kwebhithi 2 werejista ye-tst_ctl yebhulokhi yokulawula ye-ED.
Umyalo wesiteshi ramp iphethini generator	Umklamo we-F-Tile JESD204C example isekela ishaneli yomyalo ramp iphethini generator ngomzila. I-ramp inani lephethini likhuphuka ngo-1 ngamabhithi angu-6 omyalo wamagama. Imbewu yokuqala iyiphethini yokukhula kuyo yonke imizila.

Ithebula 12. Isihloli Sephethini Esisekelwe

Isihloli Sephethini	Incazelo
Isihloli sephethini se-PRBS	Imbewu enyakazayo kusihloli sephethini iyazivumelanisa ngokwayo lapho i-F-Tile JESD204C IP ifinyelela ukuqondanisa kwedeskew. Isihloli sephethini sidinga ama-octet angu-8 ukuze imbewu enyakazayo izivumelanise.
Ramp umhloli wephethini	Idatha yokuqala evumelekile sampI-le yesiguquli ngasinye (M) ilayishwa njengenani lokuqala lika-ramp iphethini. Idatha elandelayo sampamavelu ama-les kufanele akhuphuke ngo-1 kumjikelezo wewashi ngamunye aze afike ezingeni eliphezulu abese egingqika aye ku-0.

Isihloli Sephethini	Incazelo
	Okwesiboneloample, lapho S=1, N=16 kanye WIDTH_MULP = 2, ububanzi bedatha isiguquli ngasinye singu-S * WIDTH_MULP * N = 32. Idatha enkulu sampinani le-le ngu-0xFFFF. I-ramp isihloli sephethini siqinisekisa ukuthi amaphethini afanayo atholwa kuzo zonke iziguquli.
Umyalo wesiteshi ramp umhloli wephethini	Umklamo we-F-Tile JESD204C example isekela ishaneli yomyalo ramp umhloli wephethini. Igama lomyalo wokuqala (amabhithi angu-6) elitholiwe lilayishwa njengenani lokuqala. Amagama womyalo alandelayo emzileni ofanayo kufanele akhuphuke aze afike ku-0x3F bese egingqika aye ku-0x00. Ishaneli yomyalo ramp isihloli sephethini sihlola u-ramp amaphethini kuzo zonke izindlela.

I-F-Tile JESD204C TX ne-RX IP
Lo mklamo exampI-le ikuvumela ukuthi ulungiselele i-TX/RX ngayinye kumodi ye-simplex noma imodi ye-duplex.
Ukulungiselelwa kwe-Duplex kuvumela ukuboniswa kokusebenza kwe-IP kusetshenziswa i-serial loopback yangaphakathi noma yangaphandle. Ama-CSR angaphakathi kwe-IP awathuthukiswanga ukuze avumele ukulawulwa kwe-IP nokubhekwa kwesimo.

I-F-Tile JESD204C Design Example Clock futhi Setha Kabusha

Umklamo we-F-Tile JESD204C exampI-le inesethi yewashi futhi isetha kabusha amasignali.

Ithebula 13.I-Design Example Amawashi

Isiginali yewashi	Isiqondiso	Incazelo
mgmt_clk	Okokufaka	Iwashi elihlukile le-LVDS elinemvamisa ye-100 MHz.
refclk_xcvr	Okokufaka	Iwashi lereferensi le-Transceiver elinemvamisa yesilinganiso sedatha/isici esingu-33.
refclk_core	Okokufaka	Iwashi eliyisithenjwa elinobuningi obufana ne refclk_xcvr.
ku_sysref	Okokufaka	Isignali ye-SYSREF. Imvamisa enkulu ye-SYSREF isilinganiso sedatha/(66x32xE).
sysref_out	Okukhiphayo
txlink_clk rxlink_clk	Ngaphakathi	Iwashi le-TX ne-RX elixhumanisa imvamisa yesilinganiso sedatha/66.
txframe_clk rxframe_clk	Ngaphakathi	Iwashi lozimele le-TX ne-RX elinemvamisa yesilinganiso sedatha/33 (FCLK_MULP=2) Iwashi lozimele le-TX ne-RX elinemvamisa yesilinganiso sedatha/66 (FCLK_MULP=1)
tx_fclk rx_fclk	Ngaphakathi	Iwashi lesigaba le-TX ne-RX elinobuningi besilinganiso sedatha/66 (FCLK_MULP=2) Iwashi lesigaba le-TX nele-RX lihlala liphezulu (1'b1) uma i-FCLK_MULP=1
spi_SCLK	Okukhiphayo	Iwashi le-SPI baud rate nemvamisa engu-20 MHz.

Uma ulayisha i-ex designample kudivayisi ye-FPGA, umcimbi wangaphakathi ninit_done uqinisekisa ukuthi i-JTAG ukuya e-Avalon Master bridge isethwe kabusha kanye nawo wonke amanye amabhulokhi.

Ijeneretha ye-SYSREF inokusetha kabusha kwayo okuzimele ukuze kujove ubudlelwano obungavumelani namawashi we-txlink_clk kanye ne-rxlink_clk. Le ndlela iphelele ekulingiseni isignali ye-SYSREF kusuka ku-chip yewashi yangaphandle.

Ithebula 14. I-Design Example Setha kabusha

Setha kabusha Isiginali	Isiqondiso	Incazelo
global_rst_n	Okokufaka	Inkinobho yokucisha yokusetha kabusha umhlaba wonke kuwo wonke amabhulokhi, ngaphandle kwe-JTAG ukuya ebhulohweni le-Avalon Master.
kwenziwe_kwenziwe	Ngaphakathi	Okuphumayo kokuthi Setha Kabusha Ukukhishwa Kwe-IP ye-JTAG ukuya ebhulohweni le-Avalon Master.
edctl_rst_n	Ngaphakathi	Ibhulokhi ye-ED Control isethwe kabusha ngu-JTAG ukuya ebhulohweni le-Avalon Master. Izimbobo ze-hw_rst ne-global_rst_n azisethi kabusha ibhulokhi ye-ED Control.
hw_kuqala	Ngaphakathi	Faka futhi udayise okuthi hw_rst ngokubhalela kurejista ye-rst_ctl yebhulokhi ye-ED Control. mgmt_rst_in_n uyagomela lapho u-hw_rst egonyelwa.
mgmt_rst_in_n	Ngaphakathi	Setha kabusha ukuxhumana okufakwe kumephu yenkumbulo ye-Avalon yama-IP ahlukahlukene nokokufaka kokusetha kabusha okulandelanayo:  j20c_reconfig_reset for F-Tile JESD204C IP duplex Native PHY spi_rst_n ye-SPI master pio_rst_n yesimo se-PIO nokulawula reset_in0 port of reset sequencer 0 kanye 1 Imbobo ye-global_rst_n, hw_rst, noma i-edctl_rst_n port isethwe kabusha ku-mgmt_rst_in_n.
sysref_rst_n	Ngaphakathi	Setha kabusha ibhulokhi yokukhiqiza ye-SYSREF kubhulokhi Yokulawula ye-ED usebenzisa isilandeleli sokusetha kabusha 0 reset_out2 port. Isilandeleli sokusetha kabusha esingu-0 reset_out2 port sisusa ukusetha kabusha uma i-PLL eyinhloko ikhiyiwe.
core_pll_kuqala	Ngaphakathi	Isetha kabusha i-PLL ewumgogodla ngesilandeleli sokusetha kabusha 0 reset_out0 port. I-PLL eyinhloko isethwa kabusha lapho ukusetha kabusha kwe-mgmt_rst_in_n kushiwo.
j204c_tx_avs_rst_n	Ngaphakathi	Isetha kabusha isixhumi esibonakalayo esinemephu yenkumbulo ye-F-Tile JESD204C TX Avalon ngokusebenzisa isilandeleli sokusetha kabusha 0. Isixhumi esibonakalayo esinemephu yenkumbulo ye-TX Avalon igomela lapho i-mgmt_rst_in_n igonyelwa.
j204c_rx_avs_rst_n	Ngaphakathi	Isetha kabusha isixhumi esibonakalayo esinemephu yenkumbulo ye-F-Tile JESD204C TX Avalon ngokusebenzisa isilandeleli sokusetha kabusha 1. Isixhumi esibonakalayo esinemephu yenkumbulo ye-RX Avalon igomela lapho i-mgmt_rst_in_n igonyelwa.
j204c_tx_rst_n	Ngaphakathi	Isetha kabusha isixhumanisi se-F-Tile JESD204C TX nezendlalelo zokuthutha ku-txlink_clk, kanye ne-txframe_clk, ezizindeni. Isilandeleli sokusetha kabusha 0 reset_out5 port sisetha kabusha i-j204c_tx_rst_n. Lokhu kusetha kabusha ama-dessert uma i-PLL eyinhloko ikhiyiwe, futhi amasiginali we-tx_pma_ready kanye ne-tx_ready ayagonyelwa.
j204c_rx_rst_n	Ngaphakathi	Isetha kabusha isixhumanisi se-F-Tile JESD204C RX kanye nezendlalelo zokuthutha kusizinda, rxlink_clk, kanye ne-rxframe_clk.

Setha kabusha Isiginali	Isiqondiso	Incazelo
		Imbobo yokusetha kabusha engu-1 reset_out4 isetha kabusha imbobo ethi j204c_rx_rst_n. Lokhu kusetha kabusha ama-dessert uma i-PLL eyinhloko ikhiyiwe, futhi amasiginali we-rx_pma_ready kanye ne-rx_ready ayagonyelwa.
j204c_tx_rst_ack_n	Ngaphakathi	Setha kabusha isignali yokuxhawula nge-j204c_tx_rst_n.
j204c_rx_rst_ack_n	Ngaphakathi	Setha kabusha isignali yokuxhawula nge-j204c_rx_rst_n.

Umfanekiso 8. Umdwebo Wesikhathi We-Design Example Setha kabusha

I-F-Tile JESD204C Design Example Signals

Ithebula 15. Amasignali e-System Interface

Isiginali	Isiqondiso	Incazelo
Amawashi Nokusetha Kabusha
mgmt_clk	Okokufaka	Iwashi le-100 MHz lokuphatha uhlelo.
refclk_xcvr	Okokufaka	Iwashi eliyisethenjwa le-F-tile UX QUAD ne-System PLL. Ilingana nezinga ledatha/isici esingu-33.
refclk_core	Okokufaka	Iwashi lereferensi le-Core PLL. Isebenzisa imvamisa yewashi efana ne-refclk_xcvr.
ku_sysref	Okokufaka	Isiginali ye-SYSREF evela kujeneretha yangaphandle ye-SYSREF yokusetshenziswa kwe-JESD204C I-Subclass 1.
sysref_out	Okukhiphayo	Isiginali ye-SYSREF yokusetshenziswa kwe-JESD204C I-Subclass 1 ekhiqizwe idivayisi ye-FPGA ye-design exampinhloso yokuxhumanisa kuphela.

 

Isiginali	Isiqondiso	Incazelo
SPI
spi_SS_n[2:0]	Okukhiphayo	Iphansi esebenzayo, isignali yokukhetha isigqila se-SPI.
spi_SCLK	Okukhiphayo	Iwashi le-serial le-SPI.
i-spi_sdio	Okokufaka/Okukhiphayo	Idatha yokuphumayo isuka kunkosi iye kwisigqila sangaphandle. Idatha yokufaka isuka kusigqila sangaphandle iye kumphathi.

Isiginali	Isiqondiso	Incazelo
Qaphela:Lapho Khiqiza i-3-Wire SPI Module inketho inikwe amandla.
spi_MISO Qaphela: Uma Khiqiza i-3-Wire SPI Module inketho ayivunyelwe.	Okokufaka	Idatha yokufaka isuka kusigqila sangaphandle iye kumphathi we-SPI.
spi_MOSI Qaphela: Uma Khiqiza i-3-Wire SPI Module inketho ayivunyelwe.	Okukhiphayo	Idatha yokuphumayo kusuka kumphathi we-SPI kuya kusigqila sangaphandle.

 

Isiginali	Isiqondiso	Incazelo
I-ADC / DAC
tx_serial_data[LINK*L-1:0]	Okukhiphayo	Umehluko wedatha ye-serial ephumayo yesivinini esiphezulu ku-DAC. Iwashi lishumekwe ekusakazweni kwedatha ye-serial.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]	Okokufaka	Umehluko wedatha yokufaka ye-serial yesivinini esiphezulu evela ku-ADC. Iwashi litholwa ekusakazweni kwedatha ye-serial.
rx_serial_data_n[LINK*L-1:0]

 

Isiginali	Isiqondiso	Incazelo
Inhloso Ejwayelekile I/O
umsebenzisi_uholwa[3:0]	Okukhiphayo	Ibonisa isimo salezi zimo ezilandelayo: [0]: Ukuhlela kwe-SPI kwenziwe [1]: Iphutha lesixhumanisi se-TX [2]: Iphutha lesixhumanisi se-RX [3]: Iphutha lokuhlola iphethini ledatha yokusakaza ye-Avalon
umsebenzisi_dip[3:0]	Okokufaka	Okokufaka kwe-DIP yemodi yomsebenzisi: [0]: Nika amandla i-loopback ye-serial yangaphakathi [1]: Nika amandla i-SYSREF ekhiqizwe yi-FPGA [3:2] agodliwe

 

Isiginali	Isiqondiso	Incazelo
Ngaphandle kwebhendi (OOB) kanye Nesimo
rx_patchk_data_error[LINK-1:0]	Okukhiphayo	Uma le signali igonyelwa, ikhombisa ukuthi isihloli sephethini sithole iphutha.
rx_link_error[LINK-1:0]	Okukhiphayo	Uma le signali igonyelwa, ikhombisa ukuthi i-JESD204C RX IP igomele ngokuphazamiseka.
tx_link_error[LINK-1:0]	Okukhiphayo	Uma le signali igonyelwa, ikhombisa ukuthi i-JESD204C TX IP igomele ngokuphazamiseka.
emb_lock_out	Okukhiphayo	Uma le signali igonyelwa, ibonisa ukuthi i-JESD204C RX IP izuze ukukhiya kwe-EMB.
sh_vala_ngaphandle	Okukhiphayo	Uma le signali igonyelwa, ikhombisa unhlokweni wokuvumelanisa we-JESD204C RX IP ukhiyiwe.

 

Isiginali	Isiqondiso	Incazelo
Ukusakaza kwe-Avalon
rx_avst_valid[LINK-1:0]	Okokufaka	Ibonisa ukuthi isiguquli sampidatha yesendlalelo sohlelo lokusebenza ivumelekile noma ayivumelekile. 0: Idatha ayivumelekile 1: Idatha ivumelekile
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Okokufaka	Isiguquli sample idatha kusendlalelo sohlelo lokusebenza.

I-F-Tile JESD204C Design Example Control Registers

Umklamo we-F-Tile JESD204C exampirejista ku-ED Control block isebenzisa i-byte-addressing (32 bits).

Ithebula 16. I-Design Example Imephu Yekheli
Lawa marejista ebhulokhi ye-32-bit ED akusizinda se-mgmt_clk.

Isakhi	Ikheli
I-F-Tile JESD204C TX IP	0x000C_0000 – 0x000C_03FF
I-F-Tile JESD204C RX IP	0x000D_0000 – 0x000D_03FF
Ukulawulwa kwe-SPI	0x0102_0000 – 0x0102_001F
Ukulawulwa kwe-PIO	0x0102_0020 – 0x0102_002F
Isimo se-PIO	0x0102_0040 – 0x0102_004F
Setha kabusha Isilandeleli 0	0x0102_0100 – 0x0102_01FF
Setha kabusha Isilandeleli 1	0x0102_0200 – 0x0102_02FF
I-ED Control	0x0102_0400 – 0x0102_04FF
I-F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Ithebula 17. Uhlobo Lokufinyelela Lokubhalisa Nencazelo
Leli thebula lichaza uhlobo lokufinyelela lwerejista lwe-Intel FPGA IPs.

Uhlobo Lokufinyelela	Incazelo
I-RO/V	Isoftware efundwayo kuphela (akukho mphumela ekubhaleni). Inani lingahluka.
RW	Isoftware ifunda futhi ibuyise inani lamanje lebhithi. I-software ibhala futhi isethe kancane inani elifiswayo.
I-RW1C	Isoftware ifunda futhi ibuyise inani lamanje lebhithi. Isoftware ibhala 0 futhi ayinawo umthelela. Isoftware ibhala oku-1 futhi isuse ibhithi iye ku-0 uma ibhithi isethwe ku-1 ngehadiwe. I-Hardware isetha kancane ku-1. Isoftware ecacile ibaluleke kakhulu kunesethi yehadiwe.

Ithebula 18. Imephu Yekheli Lokulawula ED

I-Offset	Bhalisa Igama
0x00	Okokuqala_ctl
0x04	Okokuqala_oku0
waqhubeka...

I-Offset	Bhalisa Igama
0x10	rst_sts_detected0
0x40	sysref_ctl
0x44	sysref_sts
0x80	tst_ctl
I-0x8c	tst_err0

Ithebula 19. ED Control Block Control and Status Registers

Byte I-Offset	Bhalisa	Igama	Ukufinyelela	Setha kabusha	Incazelo
0x00	Okokuqala_ctl	qinisekisa_wokuqala	RW	0x0	Setha kabusha isilawuli. [0]: Bhala oku-1 ukuze uqinisekise ukusethwa kabusha. (hw_rst) Bhala u-0 futhi ukuze usethe kabusha i-dessert. [31:1] Reserved.
0x04	Okokuqala_oku0	isimo_sokuqala	I-RO/V	0x0	Setha kabusha isimo. [0]: Isimo esikhiyiwe se-Core PLL. [31:1] agodliwe.
0x10	rst_sts_dete cted0	rst_sts_set	I-RW1C	0x0	Isimo sokutholwa konqenqema se-SYSREF sejeneretha ye-SYSREF yangaphakathi noma yangaphandle. [0]: Inani loku-1 Libonisa unqenqema olukhuphukayo lwe-SYSREF lutholwa ekusebenzeni kwe-subclass 1. Isofthiwe ingase ibhale oku-1 ukuze isule le bit ukuze inike amandla ukutholwa konqenqema kwe-SYSREF entsha. [31:1] Reserved.
0x40	sysref_ctl	sysref_contr ol	RW	I-Duplex idathapath Ukudubula okukodwa: 0x00080	Ukulawulwa kwe-SYSREF. Bukela ku Ithebula 10 ekhasini 17 ukuze uthole ulwazi olwengeziwe mayelana nokusetshenziswa kwale rejista.
				Izikhathi:	Qaphela: Inani lokusetha kabusha lincike
				0x00081	uhlobo lwe-SYSREF kanye ne-F-Tile
				I-Gapped- periodic:	Izilungiselelo zepharamitha yedatha ye-JESD204C IP.
				0x00082
				Idatha ye-TX noma ye-RX
				indlela
				Isithombe esisodwa:
				0x00000
				Izikhathi:
				0x00001
				Kunegebe-
				ngezikhathi ezithile:
				0x00002
0x44	sysref_sts	sysref_statu s	I-RO/V	0x0	Isimo se-SYSREF. Le rejista iqukethe isikhathi sakamuva se-SYSREF nezilungiselelo zomjikelezo wemisebenzi yejeneretha yangaphakathi ye-SYSREF. Bukela ku Ithebula 9 ekhasini 16 ngevelu esemthethweni yesikhathi se-SYSREF kanye nomjikelezo womsebenzi.
waqhubeka...

Byte I-Offset	Bhalisa	Igama	Ukufinyelela	Setha kabusha	Incazelo
					[8:0]: isikhathi se-SYSREF. Uma inani lingu-0xFF, i- Isikhathi se-SYSREF = 255 Uma inani uma 0x00, isikhathi se-SYSREF = 256. [17:9]: Umjikelezo womsebenzi we-SYSREF. [31:18] agodliwe.
0x80	tst_ctl	tst_control	RW	0x0	Ukulawula ukuhlolwa. Sebenzisa le rejista ukuze unike amandla amaphethini okuhlola ahlukene ejeneretha yephethini nesihloli. [1:0] = Inkambu egodliwe [2] = ramp_test_ctl 1'b0 = Inika amandla ijeneretha yephethini ye-PRBS nesihloli 1'b1 = Inika amandla u-ramp iphethini generator kanye okuhlola [31:3] Reserved.
I-0x8c	tst_err0	tst_iphutha	I-RW1C	0x0	Ukuhlaba umkhosi kwephutha kusixhumanisi esingu-0. Uma ibhithi elingu-1'b1, libonisa ukuthi kwenzeke iphutha. Kufanele uxazulule iphutha ngaphambi kokubhala okuthi 1'b1 engxenyeni efanele ukuze usule ifulegi lephutha. [0] = Iphutha lesihloli sephethini [1] = tx_link_error [2] = rx_link_error [3] = Iphutha lesihloli sephethini yomyalo [31:4]: Igodliwe.

Umlando Wokubuyekezwa Kombhalo we-F-Tile JESD204C Intel FPGA IP Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2021.10.11	21.3	1.0.0	Ukukhishwa kokuqala.

Amadokhumenti / Izinsiza

intel F-Tile JESD204C Intel FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-F-Tile JESD204C Intel FPGA IP Design Example, F-Tile JESD204C, Intel FPGA IP Design Example, IP Design Example, Design Example

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