I-DisplayPort Agilex F-Tile FPGA IP Design Example
Umhlahlandlela Womsebenzisi
Ibuyekezelwe i-Intel® Quartus® Prime Design Suite: 21.4
Inguqulo ye-IP: 21.0.0

I-DisplayPort Intel FPGA IP Design Exampne-Quick Start Guide

Umklamo we-DisplayPort Intel® FPGA IP exampi-les yamadivayisi we-Intel Agilex™ F-tile afaka ibhentshi lokuhlola elilingisayo kanye nedizayini yezingxenyekazi zekhompuyutha esekela ukuhlanganisa nokuhlolwa kwezingxenyekazi zekhompuyutha.
I-DisplayPort Intel FPGA IP inikeza i-ex design elandelayoampkancane:

• I-DisplayPort SST parallel loopback ngaphandle kwemojuli ye-Pixel Clock Recovery (PCR) ngesilinganiso esimile

Uma udala i-ex designample, umhleli wepharamitha udala ngokuzenzakalelayo i filekudingekile ukulingisa, ukuhlanganisa, nokuhlola idizayini kuhadiwe.
Qaphela: Inguqulo yesofthiwe ye-Intel Quartus® Prime 21.4 isekela kuphela i-Preliminary Design Example ngezinjongo Zokulingisa, Ukuhlanganiswa, Ukuhlanganisa, kanye Nesikhathi. Ukusebenza kwezingxenyekazi zekhompuyutha akuqinisekisiwe ngokugcwele.
Umfanekiso 1. Ukuthuthukiswa Stages

Ulwazi Oluhlobene

• I-DisplayPort Intel FPGA IP User Guide
• Ithuthela ku-Intel Quartus Prime Pro Edition

1.1. Ukwakheka Kwemibhalo
Umfanekiso 2. Ukwakheka Kwemibhalo

Ithebula 1. Idizayini Example Components

Amafolda	Files
i-rtl/core	dp_core.ip
	dp_rx.ip
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((ibhulokhi yokwakha ye-DP PMA UX)
	dp_rx_data_fifo.ip
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((ibhulokhi yokwakha ye-DP PMA UX)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Izingxenyekazi zekhompuyutha nezidingo zeSoftware
I-Intel isebenzisa izingxenyekazi zekhompuyutha ezilandelayo nesofthiwe ukuhlola i-ex yedizayiniample:
Izingxenyekazi zekhompuyutha

• I-Intel Agilex I-Series Development Kit

Isofthiwe

• I-Intel Quartus Prime
• Synopsy* VCL Simulator

1.3. Ikhiqiza Umklamo
Sebenzisa isihleli sepharamitha ye-DisplayPort Intel FPGA IP ku-Intel Quartus Prime software ukuze ukhiqize i-ex yomklamoample.
Umfanekiso 3. Ukukhiqiza Ukugeleza Komklamo

1. Khetha Amathuluzi ➤ Ikhathalogi ye-IP, bese ukhetha i-Intel Agilex F-tile njengomndeni wedivayisi okuqondiswe kuyo.
   Qaphela: I-ex designampi-le isekela kuphela amadivayisi we-Intel Agilex F-tile.
2. Kukhathalogi ye-IP, thola bese uchofoza kabili i-DisplayPort Intel FPGA IP. Iwindi le-New IP Variation liyavela.
3. Cacisa igama lezinga eliphezulu lokuhluka kwakho kwe-IP yangokwezifiso. Umhleli wepharamitha ugcina izilungiselelo zokuhlukahluka kwe-IP ku-a file okuthiwa .ip.
4. Ungase ukhethe idivayisi ethile ye-Intel Agilex F-tile kunkambu yeDivayisi, noma ugcine ukukhethwa kwedivayisi yesofthiwe ye-Intel Quartus Prime.
5. Chofoza okuthi KULUNGILE. Umhleli wepharamitha uyavela.
6. Lungiselela imingcele oyifunayo yakho kokubili i-TX ne-RX
7. Ku-Design Exampkuthebhu, khetha i-DisplayPort SST Parallel Loopback Ngaphandle kwe-PCR.
8. Khetha Ukulingisa ukuze ukhiqize ibhentshi lokuhlola, bese ukhetha i-Synthesis ukuze ukhiqize i-ex ye-hardware designample. Kufanele ukhethe okungenani eyodwa yalezi zinketho ukuze ukhiqize i-ex yokuklamaample files. Uma ukhetha kokubili, isikhathi sokukhiqiza siba side.
9. Chofoza okuthi Khiqiza Isibample Design.

1.4. Ukulingisa Umklamo
I-DisplayPort Intel FPGA IP design exampI-le testbench ilingisa ukwakheka kwe-serial loopback kusuka kusibonelo se-TX kuya kusibonelo se-RX. Imojuli yangaphakathi yokukhiqiza iphethini yevidiyo ishayela isibonelo se-DisplayPort TX futhi okokukhiphayo kwevidiyo okuyisibonelo se-RX kuxhumeka kuzihloli ze-CRC kubhentshi lokuhlola.
Umfanekiso 4. Ukugeleza Kokulingisa Komklamo

1. Iya kufolda yesilingisi se-Synopsys bese ukhetha i-VCS.
2. Qalisa isikripthi sokulingisa.
   Umthombo vcs_sim.sh
3. Iskripthi senza i-Quartus TLG, sihlanganise futhi sisebenzise ibhentshi lokuhlola kusifanisi.
4. Hlaziya umphumela.
   Ukulingisa okuyimpumelelo kugcina ngokuqhathanisa Umthombo kanye neSink SRC.

1.5. Ukuhlanganisa kanye Nokulingisa Umklamo
Umfanekiso 5. Ukuhlanganisa kanye Nokulingisa Umklamo

Ukuhlanganisa nokusebenzisa ukuhlolwa kokubonisa ku-hardware example design, landela lezi zinyathelo:

1. Qinisekisa i-hardware exampi-design generation iqedile.
2. Yethula isofthiwe ye-Intel Quartus Prime Pro Edition futhi uvule /quartus/agi_dp_demo.qpf.
3. Chofoza Ukucubungula ➤ Qala Ukuhlanganisa.
4. Linda kuze kuqedwe Ukuhlanganisa.

Qaphela: Umklamo exampi-le ayiqinisekisi ngokusebenza i-Preliminary Design Example ku-hardware kulokhu kukhululwa kwe-Quartus.
Ulwazi Oluhlobene
Intel Agilex I-Series FPGA Development Kit Umhlahlandlela Womsebenzisi

1.6. I-DisplayPort Intel FPGA IP Design Example Amapharamitha
Ithebula 2. I-DisplayPort Intel FPGA IP Design Example Amapharamitha we-Intel Agilex F-tile Device

Ipharamitha	Inani	Incazelo
Idizayini Etholakalayo Example
Khetha i-Design	• Akukho • I-DisplayPort SST Parallel I-Loopback ngaphandle kwe-PCR	Khetha i-ex designample ezokwenziwa. • Lutho: Ayikho i-ex designampi-le iyatholakala ekukhethweni kwepharamitha yamanje • I-DisplayPort SST Parallel Loopback ngaphandle kwe-PCR: Lo mklamo exampI-le ibonisa i-loopback ehambisanayo isuka kusinki ye-DisplayPort iye emthonjeni we-DisplayPort ngaphandle kwemojuli ye-Pixel Clock Recovery (PCR) lapho uvula ipharamitha yokunika amandla Imbobo yesithombe sokufaka ividiyo.
I-Design Example Files
Ukulingisa	Khanyisa cisha	Vula le nketho ukuze ukhiqize okudingekayo files okwebhentshi lokulinganisa lokulingisa.
I-synthesis	Khanyisa cisha	Vula le nketho ukuze ukhiqize okudingekayo files yokuhlanganiswa kwe-Intel Quartus Prime kanye nokwakhiwa kwehadiwe.
Kwenziwe Ifomethi ye-HDL
Khiqiza File Ifomethi	I-Verilog, i-VHDL	Khetha ifomethi oyithandayo ye-HDL ye-ex yedizayini ekhiqiziweample filesetha. Qaphela: Le nketho inquma kuphela ifomethi yeleveli ephezulu ye-IP ekhiqiziwe files. Konke okunye files (isbample testbenches kanye nezinga eliphezulu files yokuboniswa kwezingxenyekazi zekhompyutha) zikufomethi ye-Verilog HDL.
Ikhithi Yokuthuthukisa Okuqondisiwe
Khetha Ibhodi	• Ayikho Ikhithi Yokuthuthukisa • I-Intel Agilex I-Series Ikhithi Yokuthuthukisa	Khetha ibhodi ye-ex yedizayini eqondisiweample. • Ayikho Ikhithi Yokuthuthukisa: Le nketho ayifaki zonke izici zehadiwe ye-ex yedizayiniample. I-IP core isetha yonke imisebenzi yephinikhodi kumaphinikhodi abonakalayo. • I-Intel Agilex I-Series FPGA Development Kit: Le nketho ikhetha ngokuzenzakalela idivayisi eqondiwe yephrojekthi ukuze ifane nedivayisi kule khithi yokuthuthukisa. Ungashintsha idivayisi eqondiwe usebenzisa ipharamitha yedivayisi eqondisiwe uma ukubuyekezwa kwebhodi lakho kunokwehlukile kwedivayisi. I-IP core isetha yonke imisebenzi yephinikhodi ngokuya ngekhithi yokuthuthukisa. Qaphela: Idizayini Yokuqala Isibampi-le ayiqinisekiswanga ngokusebenza kwehadiwe kulokhu kukhishwa kwe-Quartus. • Ikhithi Yokuthuthukisa Ngokwezifiso: Le nketho ivumela i-ex yedizayiniample izohlolwa kukhithi yokuthuthukisa yenkampani yangaphandle nge-Intel FPGA. Ungase udinge ukusetha imisebenzi yephinikhodi uwedwa.
	Idivayisi eqondiwe
Shintsha Idivayisi Eqondisiwe	Khanyisa cisha	Vula le nketho bese ukhetha ukwahluka kwedivayisi okuncamelayo kwekhithi yokuthuthukisa.

I-Parallel Loopback Design ExampLes

I-DisplayPort Intel FPGA IP design exampLes sibonise i-loopback ehambisanayo kusukela kusibonelo se-DisplayPort RX kuya kusibonelo se-DisplayPort TX ngaphandle kwemojula ye-Pixel Clock Recovery (PCR) ngenani elimile.
Ithebula 3. I-DisplayPort Intel FPGA IP Design Example ye-Intel Agilex F-tile Device

I-Design Example	Ukuqokwa	Isilinganiso Sedatha	Imodi Yesiteshi	Uhlobo lwe-Loopback
I-DisplayPort SST parallel loopback ngaphandle kwe-PCR	I-DisplayPort SST	I-HBR3	I-Simplex	Ihambisana ngaphandle kwe-PCR

2.1. I-Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Izici
I-SST parallel loopback design exampfuthi sibonise ukudluliswa kokusakaza okukodwa kwevidiyo kusuka kusinki e-DisplayPort kuya emthonjeni we-DisplayPort ngaphandle kwe-Pixel Clock Recovery (PCR) ngenani elimile.

Umfanekiso 6. I-Intel Agilex F-tile DisplayPort SST Parallel Loopback ngaphandle kwe-PCR

• Kulokhu okuhlukile, ipharamitha yomthombo we-DisplayPort, TX_SUPPORT_IM_ENABLE, iyavulwa futhi kusetshenziswa okusetshenziswa kubonwa isithombe sevidiyo.
• Isinki se-DisplayPort sithola ividiyo kanye noma ukusakazwa komsindo okuvela emthonjeni wamavidiyo wangaphandle njenge-GPU futhi iyihlukanise ibe isixhumi esibonakalayo sevidiyo esihambisanayo.
• I-DisplayPort sinki ephumayo yevidiyo ishayela ngokuqondile isixhumi esibonakalayo sevidiyo yomthombo we-DisplayPort futhi ibhale ngekhodi kusixhumanisi esikhulu se-DisplayPort ngaphambi kokuyidlulisela kusiqaphi.
• I-IOPLL ishayela womabili usinki we-DisplayPort kanye namawashi evidiyo yomthombo ngefrikhwensi engashintshi.
• Uma usinki we-DisplayPort kanye nepharamitha ye-MAX_LINK_RATE yomthombo ilungiselelwe ukuthi ibe yi-HBR3 futhi i-PIXELS_PER_CLOCK ilungiselelwe ukuthi ibe yi-Quad, iwashi levidiyo lisebenza ku-300 MHz ukuze lisekele izinga lamaphikiseli angu-8Kp30 (1188/4 = 297 MHz).

2.2. Uhlelo Lokuvala
Uhlelo lwewashi lubonisa izizinda zewashi kumklamo we-DisplayPort Intel FPGA IP example.
Umfanekiso 7. Isikimu sewashi se-Intel Agilex F-tile DisplayPort Transceiver

Ithebula 4. Izimpawu Zohlelo Lokuvala

Iwashi kumdwebo	Incazelo
I-SysPLL ifaka kabusha	Iwashi lereferensi le-F-tile System PLL okungaba yinoma iyiphi ifrikhwensi yewashi ehlukaniseka nge-System PLL yaleyo frikhwensi yokuphumayo. Kulo mklamo example, system_pll_clk_link kanye ne-rx/tx refclk_link yabelana nge-SysPLL refclk efanayo engu-150Mhz. Kumelwe kube iwashi eligijima lamahhala elixhunywe kwiphinikhodi yereferensi ye-transceiver ezinikele embobeni yewashi yokufaka ye-Reference kanye ne-System PLL Clocks IP, ngaphambi kokuxhuma imbobo yokukhiphayo ehambisanayo ne-DisplayPort Phy Top.
system_pll_clk_link	Ubuncane bemvamisa yokuphuma kweSistimu ye-PLL ukusekela lonke izinga le-DisplayPort ngu-320Mhz. Lo mklamo exampI-le isebenzisa i-900 Mhz (ephakeme kakhulu) imvamisa yokuphumayo ukuze i-SysPLL refclk yabelwane ne-rx/tx refclk_link engu-150 Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	I-Rx CDR kanye ne-Tx PLL Link refclk ehlanganiswe ku-150 Mhz ukuze isekele lonke izinga ledatha ye-DisplayPort.
rx_ls_clkout/tx I-clkout	Iwashi lesivinini se-DisplayPort ukuze uwashi i-DisplayPort IP core. Imvamisa elilingana Nesilinganiso Sedatha hlukanisa ngobubanzi bedatha obuhambisanayo. Example: Imvamisa = isilinganiso sedatha/ububanzi bedatha = 8.1G (HBR3) / 40bits = 202.5 Mhz

2.3. Ukulingisa Testbench
Ibhentshi lesivivinyo sokulingisa lilingisa i-DisplayPort TX serial loopback ku-RX.
Umfanekiso 8. I-DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram

Ithebula 5. Izingxenye ze-Testbench

Isakhi	Incazelo
Isiqophi Iphethini Generator	Le generator ikhiqiza amaphethini ebha yombala ongawalungiselela. Ungakwazi ukuhlukanisa isikhathi sefomethi yevidiyo.
I-Testbench Control	Leli bhulokhi lilawula ukulandelana kokuhlolwa kokulingisa futhi likhiqize amasiginali adingekayo e-TX core. Ibhulokhi yokulawula ye-testbench iphinda ifunde inani le-CRC kusuka kukho kokubili umthombo nosinki ukwenza iziqhathaniso.
I-RX Link Speed ​​Clock Frequency Checker	Lesi sihloli siqinisekisa ukuthi i-transceiver ye-RX etholiwe imvamisa yewashi ifana yini nezinga ledatha elifiswayo.
I-TX Link Speed ​​Clock Frequency Checker	Lesi sihloli siqinisekisa ukuthi i-TX transceiver etholiwe imvamisa yewashi ifana yini nenani ledatha elifunekayo.

I-testbench yokulingisa yenza lokhu okulandelayo:
Ithebula 6. Ukuqinisekiswa Kwe-Testbench

Imibandela Yokuhlola	Ukuqinisekisa
• Xhumanisa Ukuqeqeshwa Ngesilinganiso Sedatha HBR3 • Funda amarejista e-DPCD ukuze uhlole ukuthi Isimo se-DP siyasetha futhi sikala kokubili i-TX kanye ne-RX Link Speed ​​frequency.	Ihlanganisa i-Frequency Checker ukuze ilinganise ukuphuma kwefrikhwensi yewashi le-Link Speed ​​​​kusukela ku-TX kanye ne-RX transceiver.
• Sebenzisa iphethini yevidiyo usuka ku-TX uye ku-RX. • Qinisekisa i-CRC yakho kokubili umthombo nosinki ukuze uhlole ukuthi ayahambisana yini	• Ixhuma ijeneretha yephethini yevidiyo kuMthombo we-DisplayPort ukuze ukhiqize iphethini yevidiyo. • Ukulawula kwe-Testbench ngokulandelayo kufunda kokubili i-Source ne-Sink CRC evela kumarejista e-DPTX kanye ne-DPRX futhi kuqhathaniswe ukuze kuqinisekiswe ukuthi womabili amanani e-CRC ayefana. Qaphela: Ukuze uqinisekise ukuthi i-CRC ibalwa, kufanele unike amandla ipharamitha yokuzenzakalelayo yokuhlola ye-CTS.

Umlando Wokubuyekezwa Kwedokhumenti we-DisplayPort Intel

I-Agilex F-tile FPGA IP Design Example Umhlahlandlela Womsebenzisi

Inguqulo Yedokhumenti	Inguqulo ye-Intel Quartus Prime	Inguqulo ye-IP	Izinguquko
2021.12.13	21.4	21.0.0	Ukukhishwa kokuqala.

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo ye-semiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi.
*Amanye amagama namabhrendi angafunwa njengempahla yabanye.
I-ISO 9001: 2015 Ubhalisiwe

I-Online Version
Thumela Impendulo
UG-20347
I-ID: 709308
Inguqulo: 2021.12.13

Amadokhumenti / Izinsiza

intel DisplayPort Agilex F-Tile FPGA IP Design Example [pdf] Umhlahlandlela Womsebenzisi I-DisplayPort Agilex F-Tile FPGA IP Design Example, DisplayPort Agilex, F-Tile FPGA IP Design Example, F-Tile FPGA IP Design, FPGA IP Design Example, IP Design Example, IP Design, UG-20347, 709308

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