FPGA IP
Uyilo Eksample Isikhokelo somsebenzisi
I-F-Tile 25G Ethernet Intel®
Ihlaziywe i-Intel® Quartus®
I-Prime Design Suite: 22.3
IP Version: 1.0.0

Isikhokelo sokuQalisa ngokukhawuleza

I-F-tile 25G Ethernet Intel FPGA IP yezixhobo ze-Intel Agilex™ ibonelela ngesakhono sokuvelisa uyilo ex.amples kuqwalaselo olukhethiweyo.
Umzobo 1. Uyilo Eksample Ukusetyenziswa

Ulwakhiwo lukavimba weefayili

Umzobo 2. 25G Ethernet Intel FPGA IP Design Example Ulwakhiwo lukavimba weefayili

• Ukulinganisa files (testbench yokulinganisa kuphela) zikwindawoample_dir>/example_testbench.
• Uqulunqo-kuphela uyilo example ibekwe kwiample_dir>/ compilation_test_design.
• Ubumbeko lwehardware kunye novavanyo files (uyilo umzample in hardware) zikwindawoample_dir>/hardware_test_design.

Uluhlu 1. Uluhlu kunye File Iinkcazelo

File Amagama	Inkcazo
eth_ex_25g.qpf	Intel Quartus® Prime project file.
eth_ex_25g.qsf	Intel Quartus Prime useto lweprojekthi file.
eth_ex_25g.sdc	Izithintelo zoYilo lwe-Synopsy file. Ungakopa kwaye ulungise oku file yeyakho i-25GbE Intel FPGA IP yoyilo olungundoqo.
eth_ex_25g.v	Umgangatho ophezulu weVerilog HDL uyilo example file. Uyilo lwetshaneli enye lisebenzisa iVerilog file.
eqhelekileyo/	Uyilo lwehardware example inkxaso files.
hwtest/main.tcl	Engundoqo file yokufikelela kwiNkqubo yeConsole.

Ukuvelisa i-Design Example

Umzobo 4. Example Tab yoYilo kwi-F-tile 25G Ethernet Intel FPGA IP Parameter Editor

Landela la manyathelo ukuvelisa uyilo lwehardware example kunye ne-testbench:

1. Kwi-Intel Quartus Prime Pro Edition, cofa File ➤ IWizard yeProjekthi eNtsha yokudala iprojekthi entsha yeQuartus Prime, okanye File ➤ Vula iProjekthi yokuvula iprojekthi esele ikho yeQuartus Prime. Iwizard ikwenza ukuba uchaze isixhobo.
2. KwiKhathalogi ye-IP, fumana kwaye ukhethe i-25G Ethernet Intel FPGA IP ye-Agilex. Iwindow entsha yoKwahluka kwe-IP iyavela.
3. Cacisa igama elikwinqanaba eliphezulu lokwahluka kwe-IP yakho kwaye ucofe u-Kulungile. Umhleli weparameter wongeza inqanaba eliphezulu .ip file kwiprojekthi yangoku ngokuzenzekelayo. Ukuba uyacelwa ukuba wongeze ngesandla i.ip file kwiprojekthi, cofa iProjekthi ➤ Yongeza/ Susa Files kwiProjekthi yokongeza i file.
4. Kwi-software ye-Intel Quartus Prime Pro Edition, kufuneka ukhethe isixhobo esithile se-Intel Agilex kwintsimi yeSixhobo, okanye ugcine isixhobo esingagqibekanga i-Intel Quartus Prime software iphakamisa.
   Phawula: Uyilo lwehardware example ibhala ngaphezulu ukhetho kunye nesixhobo kwibhodi ekujoliswe kuyo. Ukhankanya ibhodi ekujoliswe kuyo kwi menu yoyilo example iinketho kwi ExampLe thebhu yoYilo.
5. Cofa u-Kulungile. Umhleli weparameter uyavela.
6. Kwi-IP ithebhu, khankanya iiparamitha zokwahluka kondoqo we-IP yakho.
7. KwiEksampLe thebhu yoYilo, yoMzeample Design Files, khetha i Ufaniso ukhetho ukuvelisa ibhentshi yovavanyo, kwaye khetha i Udibaniso ukhetho ukuvelisa uyilo lwe hardware ex.ample. Kuphela Verilog HDL files ziyaveliswa.
   Phawula: Undoqo we-VHDL IP osebenzayo awufumaneki. Chaza i-HDL ye-Verilog kuphela, ye-IP yakho yoyilo loyilo example.
8. KwiKhiti yoPhuhliso ekujoliswe kuyo, khetha i-Agilex I-series Transceiver-SoC Dev Kit
9. Cofa uVelisa Example Design iqhosha. Khetha Eksample Dizayini kavimba weefayili iwindow iyavela.
10. Ukuba unqwenela ukulungisa uyilo example ndlela yolawulo okanye igama elivela kokungagqibekanga okubonisiweyo (alt_e25_f_0_example_design), khangela kwindlela entsha kwaye uchwetheze uyilo olutsha exampigama lolawulo (ample_dir>).
11. Cofa u-Kulungile.

1.2.1. Uyilo Eksample Parameters
Uluhlu loku-2. Iiparamitha kwiEksample Tab yoYilo

Ipharamitha	Inkcazo
Example Design	Ifumaneka example uyilo lwe IP parameter useto. Kuphela isitishi esinye example uyilo ixhaswa kule IP.
Example Design Files	I fileukuvelisa kwisigaba esahlukileyo sophuhliso. • Ukulinganisa—kuvelisa okuyimfuneko files yokulinganisa i-exampuyilo. • I-Synthesis-yenza i-synthesis files. Sebenzisa ezi files ukuqokelela uyilo kwisoftware ye-Intel Quartus Prime Pro Edition yovavanyo lwehardware kunye nokwenza uhlalutyo lwexesha elimileyo.
Veza File Ifomathi	Ubume be-RTL files yokulinganisa-Verilog.
Khetha iBhodi	I-hardware exhaswayo yokuphunyezwa koyilo. Xa ukhetha ibhodi yophuhliso lwe-Intel FPGA, sebenzisa isixhobo AGIB027R31B1E2VRO njengeSixhobo ekujoliswe kuso kuyilo ex.ample generation. Agilex I-series Transceiver-SoC Dev Kit: Olu khetho likuvumela ukuba uvavanye uyilo example kwi ekhethiweyo Intel FPGA IP ikhithi yophuhliso. Olu khetho lukhetha ngokuzenzekelayo iSixhobo ekujoliswe kuso se-AGIB027R31B1E2VRO. Ukuba uhlaziyo lwebhodi yakho inomgangatho wesixhobo esahlukileyo, ungatshintsha isixhobo ekujoliswe kuso. Akukho: Olu khetho alubandakanyi imiba yehardware yoyilo example.

1.3. Ukuvelisa iThayile Files

I-Support-Logic Generation linyathelo langaphambili le-synthesis elisetyenziselwa ukuvelisa ezinxulumene ne-tile files ezifunekayo kukulinganisa kunye noyilo lwehardware. Ukuveliswa kweethayile kuyafuneka kubo bonke
Ufaniso loyilo olusekwe kwi-F-tile. Kufuneka ugqibezele eli nyathelo phambi kokulinganisa.

1. Kwi-prompt yomyalelo, yiya kwifolda_yovavanyo_yoyilo kwi-ex yakhoample uyilo: cd /compilation_test_design.
2. Yenza lo myalelo ulandelayo: quartus_tlg alt_eth_25g

1.4. Ukulinganisa i-F-tile 25G Ethernet Intel FPGA IP Design 
Example Testbench
Ungaqokelela kwaye ulinganise uyilo ngokuqhuba iskripthi sokulinganisa ukusuka kumyalelo womyalelo.

1. Kwi-prompt yomyalelo, tshintsha i-testbench yokufanisa i-directory yokusebenza: cdample_dir>/ex_25g/sim.
2. Sebenzisa i-IP yokumisela ukulinganisa:ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Itheyibhile 3. Amanyathelo okulinganisa i-Testbench

Isifanisi	Imiyalelo
VCS*	Kumgca womyalelo, chwetheza sh run_vcs.sh
QuestaSim*	Kumgca womyalelo, chwetheza i-vsim -do run_vsim.do -logfile vsim.log Ukuba ukhetha ukulinganisa ngaphandle kokuzisa i-QuestaSim GUI, chwetheza i-vsim -c -do run_vsim.do -logfile vsim.log
Cadence -Xcelium*	Kumgca womyalelo, chwetheza sh run_xcelium.sh

Ufaniso oluyimpumelelo luphela ngomyalezo olandelayo:
Ukulinganisa Kugqithisiwe. okanye Testbench igqityiwe.
Emva kokugqiba ngempumelelo, unokuhlalutya iziphumo.
1.5. Ukuqulunqa kunye nokuqwalasela i-Design Example kwi-Hardware
I-25G Ethernet Intel FPGA IP core parameter editor ikuvumela ukuba uqokelele kwaye uqwalasele uyilo ex.ample kwikhithi yophuhliso ekujoliswe kuyo.

Ukuqokelela kunye nokuqwalasela uyilo exampkwi-hardware, landela la manyathelo:

1. Qalisa isoftwe ye-Intel Quartus Prime Pro Edition kwaye ukhethe Ukusetyenzwa ➤ Qalisa ukuHlanganisa ukuqulunqa uyilo.
2. Emva kokuba wenze into ye-SRAM file .sof, landela la manyathelo ukucwangcisa uyilo lwehardware exampkwisixhobo se-Intel Agilex:
   a. Kwimenyu yeZixhobo, cofa uMlungisi.
   b. KuMdwelisi weNkqubo, cofa uSeto lweHardware.
   c. Khetha isixhobo sokucwangcisa.
   d. Khetha kwaye wongeze ibhodi ye-Intel Agilex kwiseshoni yakho ye-Intel Quartus Prime Pro Edition.
   e. Qinisekisa ukuba iMowudi isetelwe ku-JTAG.
   f. Khetha isixhobo se-Intel Agilex kwaye ucofe Yongeza isixhobo. Umdwebi wenkqubo uyabonisa
   Umzobo webhloko woqhagamshelo phakathi kwezixhobo ezikwibhodi yakho.
   g. Kumqolo neyakho .sof, khangela ibhokisi ye .sof.
   h. Khangela ibhokisi kwiNkqubo/Qwalasela ikholam.
   i. Cofa uQalisa.

1.6. Ukuvavanya i-F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
Emva kokuba uqokelele i-F-tile 25G Ethernet Intel FPGA IP core design example kwaye uyiqwalasele kwisixhobo sakho se-Intel Agilex, ungasebenzisa iSistim Console ukucwangcisa undoqo we-IP.
Ukuvula iNkqubo yeConsole kwaye uvavanye uyilo lwehardware exampLe, landela la manyathelo:

1. Kwisoftware yeIntel Quartus Prime Pro Edition, khetha iziXhobo ➤ Inkqubo
   Izixhobo zokulungisa iimpazamo ➤ Ikhonsoli yeNkqubo yokumisela inkqubo yekhonsoli.
2. Kwipheyini yeConsole ye-Tcl, chwetheza i-cd hwtest ukutshintsha ulawulo ukuya kwi-hardware_test_design/hwtest.
3. Chwetheza umthombo main.tcl ukuvula umdibaniso kwi-JTAG inkosi.

Landela inkqubo yovavanyo kwicandelo loVavanyo lwe-Hardware yoyilo example kwaye ujonge iziphumo zovavanyo kwi-System Console.

I-F-tile 25G Ethernet Design Example yeIntel Agilex Devices

Uyilo lwe-F-tile 25G Ethernet example ibonisa isisombululo se-Ethernet sezixhobo ze-Intel Agilex usebenzisa i-25G Ethernet Intel FPGA IP core.
Veza uyilo example ukusuka kwiEksample Yila ithebhu ye-25G Ethernet Intel FPGA IP ipharamitha yomhleli. Unokukhetha kwakhona ukuvelisa uyilo kunye okanye ngaphandle
iReed-Solomon Forward Error Correction (RS-FEC) isici.
2.1. Iimpawu

• Ixhasa itshaneli enye ye-Ethernet esebenza kwi-25G.
• Ivelisa iex yoyiloample kunye RS-FEC isici.
• Ibonelela nge-testbench kunye neskripthi sokulinganisa.
• Iqinisekisa i-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP esekelwe kuqwalaselo lwe-IP.

2.2. IiMfuno zeHardware kunye neSoftware
I-Intel isebenzisa i-hardware elandelayo kunye nesofthiwe yokuvavanya i-design example kwinkqubo yeLinux:

• Intel Quartus Prime Pro Edition software.
• Siemens* EDA QuestaSim, Synopsys* VCS, kunye neCadence Xcelium simulator.
• I-Intel Agilex I-series Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) yokuvavanya i-hardware.

2.3. Inkcazo esebenzayo
Uyilo lwe-F-tile 25G Ethernet example iqulathe MAC+PCS+PMA core ezahlukeneyo. Imizobo yebhloko elandelayo ibonisa amacandelo oyilo kunye neempawu ezikumgangatho ophezulu we-MAC + PCS + PMA engundoqo eyahlukileyo kwi-F-tile 25G Ethernet design ex.ample.
Umzobo 5. Block Diagram-F-tile 25G Ethernet Design Example (MAC+PCS+PMA Core Variant)

2.3.1. Uyilo lwamacandelo
Uluhlu loku-4. Amacandelo oyilo

Icandelo	Inkcazo
I-F-tile 25G Ethernet Intel FPGA IP	Iqulathe i-MAC, i-PCS, kunye ne-Transceiver PHY, enobumbeko lulandelayo: • Umahluko ongundoqo: MAC+PCS+PMA • Vumela ulawulo lokuhamba: Ngokuzithandela • Vumela ukuveliswa kwempazamo kwikhonkco: Ngokuzithandela • Yenza ugqithiso lwentshayelelo: Ngokuzithandela • Yenza ingqokelela yeenkcukacha-manani: Ngokuzithandela • Vula izibalo zokubala ze-MAC: Ngokuzithandela • Reference clock frequency: 156.25 Kuyilo exampLe ngophawu lweRS-FEC, le parameter ilandelayo iqwalaselwe: • Yenza i-RS-FEC isebenze: Ngokuzithandela
I-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP	I-F-Tile Reference kunye neNkqubo ye-PLL Iiwashi ze-Intel FPGA IP iparameter ye-parameter setting ihambelana neemfuno ze-F-tile 25G Ethernet Intel FPGA IP. Ukuba uvelisa uyilo exampusebenzisa Veza Example Design iqhosha kumhleli weparameter ye-IP, i-IP yenza ngokuzenzekelayo. Ukuba udala owakho uyilo exampLe, kufuneka uyenze ngesandla le IP kwaye uqhagamshele onke amazibuko e-I/O. Ngolwazi malunga nale IP, bhekisa ku I-F-Tile Architecture kunye ne-PMA kunye ne-FEC Direct PHY IP User Guide.
Ingqiqo yomthengi	Ine: • Ijenereyitha yeTrafikhi, eyenza iipakethi ezigqabhukileyo kwi-25G Ethernet Intel FPGA IP core yokuhanjiswa. • Imonitha yendlela, ebeka iliso kwiipakethi ezigqabhukileyo ezivela kwi-25G Ethernet Intel FPGA IP core.
Umthombo kunye noPhando	Umthombo kunye nemiqondiso yokuphonononga, kubandakanywa isignali yokuseta ngokutsha kwenkqubo, ongayisebenzisa ukulungisa ingxaki.

Ulwazi olunxulumeneyo
I-F-Tile Architecture kunye ne-PMA kunye ne-FEC Direct PHY IP User Guide

Ukulinganisa

I-testbench ithumela i-traffic ngokusebenzisa i-IP core, isebenzisa icala lokuhambisa kunye nokufumana icala le-IP core.
2.4.1. Testbench
Umzobo 6. I-Block Diagram ye-F-tile 25G Ethernet Intel FPGA IP Design Example Ukulinganisa Testbench

Itheyibhile 5. Izixhobo zeTestbench

Icandelo	Inkcazo
Isixhobo siphantsi kovavanyo (DUT)	I-25G Ethernet Intel FPGA IP core.
I-Ethernet Packet Generator kunye nePacket Monitor	• Ipakethe yejenereyitha yenza izakhelo kwaye igqithiselwe e-DUT. • I-Packet Monitor ihlola i-TX kunye ne-RX yedatha yedatha kwaye ibonise iifreyimu kwi-console ye-simulator.
I-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP	Ivelisa iiwotshi zesalathiso ze-PLL kunye ne-transceiver.

2.4.2. Uyilo lokulinganisa Eksample Components
Itheyibhile 6. F-tile 25G Ethernet Design Example Testbench File Iinkcazelo

File Igama	Inkcazo
Testbench kunye Ukulinganisa Files
basic_avl_tb_top.v	Inqanaba eliphezulu testbench file. I-testbench iqinisekisa i-DUT, yenza i-Avalon® i-memod-mapped configuration kumacandelo oyilo kunye nengqiqo yomxhasi, kwaye ithumela kwaye ifumane ipakethi ukuya okanye kwi-25G Ethernet Intel FPGA IP.
Izikripthi zeTestbench
iqhubekile...

File Igama	Inkcazo
run_vsim.do	Iskripthi seModelSim sokusebenzisa i-testbench.
run_vcs.sh	Iskripthi se-Synopsys VCS sokusebenzisa i-testbench.
run_xcelium.sh	Iskripthi seCadence Xcelium sokusebenzisa i-testbench.

2.4.3. Ityala lovavanyo
Imeko yovavanyo lokulinganisa yenza ezi zenzo zilandelayo:

1. I-Instatiates F-tile 25G Ethernet Intel FPGA IP kunye ne-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP.
2. Ilinda ikloko ye-RX kunye nesignali yesimo se-PHY ukuba izinze.
3. Iprinta ubume be-PHY.
4. Ithumela kwaye ifumane i-10 yedatha esebenzayo.
5. Uhlalutya iziphumo. I-testbench ephumeleleyo ibonisa "i-Testbench epheleleyo.".

Oku kulandelayo sampimveliso ibonisa impumelelo yovavanyo lokulinganisa:

Ukuhlanganisa

Landela inkqubo ekuHlanganiseni nasekuqwalaseleni uYilo Example kwi Hardware ukuqokelela nokuqwalasela uyilo example kwihardware ekhethiweyo.
Ungaqikelela ukusetyenziswa kobutyebi kunye neFmax usebenzisa uyilo loqulunqo kuphela example. Ungaqulunqa uyilo lwakho usebenzisa umyalelo wokuQala wokuQolelwa kwi
Ukucubungula imenyu kwi-software ye-Intel Quartus Prime Pro Edition. Uqulunqo oluyimpumelelo luvelisa isishwankathelo sengxelo yoqulunqo.
Ngolwazi oluthe kratya, bhekisa kuLuhlu loYilo kwiSikhokelo soMsebenzisi seIntel Quartus Prime Pro Edition.
Ulwazi olunxulumeneyo

• Ukuqulunqa kunye nokuqwalasela i-Design Example kwi-Hardware kwiphepha lesi-7
• Ukuqulunqwa koYilo kwi-Intel Quartus Prime Pro Edition IsiKhokelo somsebenzisi

2.6. Uvavanyo lwe-Hardware
Kuyilo lwehardware exampLe, ungacwangcisa undoqo we-IP kwimowudi yangaphakathi yesiriyali loopback kwaye uvelise itrafikhi kwicala lokuhambisa elijika ngasemva kwicala lokwamkela.
Landela inkqubo kwikhonkco elinikiweyo lolwazi olunxulumeneyo ukuvavanya i-design example kwihardware ekhethiweyo.
Ulwazi olunxulumeneyo
Ukuvavanya i-F-tile 25G Ethernet Intel FPGA IP Hardware Design Exampkwiphepha le-8
Inkqubo yovavanyo
Landela la manyathelo ukuvavanya uyilo exampkwihardware:

1. Phambi kokuba uqhube uvavanyo lwehardware kolu yilo exampLe, kufuneka usete ngokutsha inkqubo:
   a. Cofa iziXhobo ➤ Imithombo yeSistim kunye nesixhobo soMhleli weProbes kuMthombo ongagqibekanga kunye neProbe GUI.
   b. Guqula isignali yokusetha kwakhona inkqubo (Umthombo [3: 0]) ukusuka kwi-7 ukuya kwi-8 ukuze usebenzise ukusetha kwakhona kwaye ubuyisele isignali yokusetha kwakhona inkqubo kwi-7 ukukhulula inkqubo ukusuka kwimeko yokusetha kwakhona.
   c. Beka iliso kwiimpawu zeProbe kwaye uqinisekise ukuba imeko isemthethweni.
2. Kwinkqubo yekhonsoli, jonga kwi hwtest incwadi kwaye usebenzise umyalelo: umthombo main.tcl ukukhetha i JTAG inkosi. Ngokuzenzekelayo, eyokuqala kaJTAG master kwiJTAG ikhonkco ikhethiwe. Ukukhetha iJTAG inkosi yezixhobo ze-Intel Agilex, sebenzisa lo myalelo: set_jtag <number of appropriate JTAG inkosi>. Eksample: seti_jtag 1.
3. Yenza le miyalelo ilandelayo kwikhonsoli yesixokelelwano ukuqalisa uvavanyo lothotho lweloopback:

Itheyibhile 7. IiParameters zomyalelo

Ipharamitha	Inkcazo	Example Ukusetyenziswa
chkphy_imo	Ibonisa amaza ewotshi kunye nemo ye-PHY yokutshixa.	% chkphy_status 0 # Jonga imeko yekhonkco 0
chkmac_stats	Ibonisa amaxabiso kwiikhawunta zezibalo ze-MAC.	% chkmac_stats 0 # Ijonga izibalo zokubala ze-mac zekhonkco 0
cacisa_zonke_izibalo	Icoca ii-IP zokubala zezibalo ezingundoqo.	% clear_all_stats 0 # Icima izibalo zokubala zekhonkco 0
qala_gen	Iqala ipakethe generator.	% start_gen 0 # Qalisa ukuvelisa ipakethi kwikhonkco 0
yeka_gen	Ukumisa ipakethe generator.	% stop_gen 0 # Misa ukuveliswa kwepakethi kwikhonkco 0
iluphu_kwi	Ivula i-loopback yesiriyali yangaphakathi.	% loop_on 0 # Vula i-loop yangaphakathi kwikhonkco 0
loop_off	Icima iluphu yesiriyali yangaphakathi.	% loop_off 0 # Cima i-loop yangaphakathi kwikhonkco 0
reg_funda	Ibuyisela ixabiso lerejista engundoqo ye-IP .	% reg_read 0x402 # Funda irejista ye-IP CSR kwidilesi 402 yekhonkco 0
reg_bhala	Uyabhala kwirejista engundoqo ye-IP kwidilesi .	% reg_write 0x401 0x1 # Bhala 0x1 kwi-IP CSR irejista yokukrala kwidilesi 401 yekhonkco 0

a. Chwetheza i-loop_on ukuvula uthotho lwangaphakathi lwemowudi loopback.
b. Chwetheza chkphy_status ukujonga ubume be-PHY. Ubume be-TXCLK, i-RXCLK, kunye ne-RX kufuneka zibe namaxabiso afanayo aboniswe ngezantsi kwikhonkco elizinzileyo:

c. Chwetheza clear_all_stats ukucima iirejista zezibalo ze-TX kunye ne-RX.
d. Chwetheza start_gen ukuqalisa ukwenza ipakethi.
e. Chwetheza stop_gen ukumisa ukuveliswa kweepakethi.
f. Chwetheza chkmac_stats ukufunda izibalo zokubala ze-TX kunye ne-RX. Qinisekisa ukuba:
i. Izakhelo zeepakethi ezithunyelwayo zihambelana nezakhelo zepakethi ezifunyenweyo.
ii. Akukho zikhokelo zempazamo ezifunyenweyo.
g. Chwetheza i-loop_off ukucima i-loopback yesiriyali yangaphakathi.
Umzobo 7. Sample Iziphumo zoVavanyo-TX kunye neRX Statistics Counters

Imbali yoHlaziyo yoXwebhu lwe-F-tile 25G Ethernet FPGA IP Design Example Isikhokelo somsebenzisi

Inguqulelo yoXwebhu	Intel Quartus Prime Version	IP Version	Iinguqu
2022.10.14	22.3	1.0.0	Ukukhutshwa kokuqala.

Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
ISO
9001:2015
Ibhalisiwe

Version Online
Ukuzisa impendulo
I-ID: 750200
Inguqulelo: 2022.10.14

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intel F-Tile 25G Ethernet FPGA IP Design Example [pdf] Isikhokelo somsebenzisi F-Tile 25G Ethernet FPGA IP Design Example, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Design Example, IP Design Exampnjalo, 750200

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