DisplayPort Agilex F-Tile FPGA IP Design Example
Isikhokelo somsebenzisi
Ihlaziywe kwi-Intel® Quartus® Prime Design Suite: 21.4
IP Version: 21.0.0

DisplayPort Intel FPGA IP Design Example Quick Start Guide

Uyilo lweDisplayPort Intel® FPGA IP exampIzixhobo ze-Intel Agilex™ ze-F-tile zibandakanya ibhentshi yokulinganisa yokulinganisa kunye noyilo lwehardware oluxhasa ukuqulunqwa kunye novavanyo lwehardware.
IDisplayPort Intel FPGA IP ibonelela ngoyilo lulandelayo exampngaphantsi:

• I-DisplayPort SST parallel loopback ngaphandle kwemodyuli yePixel Clock yoBuyiselo (PCR) kwinqanaba elimileyo

Xa uvelisa i-ex yoyiloampLe, umhleli weparameter yenza ngokuzenzekelayo i files iyimfuneko ukulinganisa, ukuqulunqa, kunye nokuvavanya uyilo kwihardware.
Phawula: I-Intel Quartus® Prime 21.4 inguqulelo yesoftware ixhasa kuphela i-Preliminary Design Example yokulinganisa, ukuHlanganisa, ukuHlanganisa, kunye neenjongo zohlalutyo lwexesha. Ukusebenza kwe-Hardware akuqinisekiswanga ngokupheleleyo.
Umfanekiso 1. Uphuhliso Stages

Ulwazi olunxulumeneyo

• DisplayPort Intel FPGA IP User Guide
• Ukufudukela kwi-Intel Quartus Prime Pro Edition

1.1. Ulwakhiwo lukavimba weefayili
Umzobo 2. Ulwakhiwo lukavimba weefayili

Uluhlu 1. Uyilo Eksample Components

Iifolda	Files
rtl/core	dp_core.ip
	dp_rx.ip
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((ibhloko yesakhiwo seDP PMA UX)
	dp_rx_data_fifo.ip
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((ibhloko yesakhiwo seDP PMA UX)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. IiMfuno zeHardware kunye neSoftware
I-Intel isebenzisa i-hardware elandelayo kunye nesofthiwe yokuvavanya i-design example:
Hardware

• Intel Agilex I-Series Development Kit

Isoftware

• Intel Quartus Prime
• I-Synopsy* Isifanisi se-VCL

1.3. Ukuvelisa uYilo
Sebenzisa iDisplayPort Intel FPGA IP parameter umhleli kwi-Intel Quartus Prime software ukuvelisa uyilo example.
Umzobo 3. Ukuvelisa i-Design Flow

1. Khetha iZixhobo ➤ Ikhathalogu ye-IP, kwaye ukhethe i-Intel Agilex F-tile njengesixhobo sosapho ekujoliswe kuso.
   Qaphela: Uyilo example ixhasa kuphela izixhobo ze-Intel Agilex F-tile.
2. KwiKhathalogi ye-IP, fumana kwaye ucofe kabini i-DisplayPort Intel FPGA IP. Iwindow entsha yoKwahluka kwe-IP iyavela.
3. Chaza igama elikwinqanaba eliphezulu lokwahluka kwe-IP yakho. Umhleli weparameter ugcina useto loguqulo lwe IP kwi file igama .ip.
4. Unokukhetha isixhobo esithile se-Intel Agilex F-tile kwintsimi yeSixhobo, okanye ugcine ukukhethwa kwesixhobo se-Intel Quartus Prime software.
5. Cofa u-Kulungile. Umhleli weparameter uyavela.
6. Qwalasela iiparamitha ezifunekayo kuzo zombini i-TX kunye ne-RX
7. Kuyilo Eksampkwi-tab, khetha i-DisplayPort SST Parallel Loopback Ngaphandle kwePCR.
8. Khetha Ukulinganisa ukuvelisa ibhentshi yovavanyo, kwaye ukhethe uHlaziyo ukuvelisa uyilo lwehardware example. Kufuneka ukhethe enye kwezi iinketho ukuvelisa uyilo example files. Ukuba ukhetha zombini, ixesha lesizukulwana lide.
9. Cofa uVelisa Example Design.

1.4. Ukulinganisa Uyilo
Uyilo lweDisplayPort Intel FPGA IP example testbench ilinganisa uyilo lwe-loopback olulandelelanayo ukusuka kumzekelo we-TX ukuya kumzekelo we-RX. Imodyuli yangaphakathi yokuvelisa ipateni yevidiyo iqhuba umzekelo weDisplayPort TX kunye nemveliso yevidiyo ye-RX idibanisa nabahloli be-CRC kwi-testbench.
Umzobo 4. Ukuhamba kokulinganisa uYilo

1. Yiya kwi-Synopsys simulator ifolda kwaye ukhethe i-VCS.
2. Qhuba ukulinganisa okushicilelweyo.
   Umthombo vcs_sim.sh
3. Iskripthi senza i-Quartus TLG, iqulunqa kwaye iqhube i-testbench kwi-simulator.
4. Hlalutya umphumo.
   Ukulinganisa okuyimpumelelo kuphetha ngoMthombo kunye neSink SRC uthelekiso.

1.5. Ukuqulunqa kunye nokulinganisa uYilo
Umzobo 5. Ukuqulunqa kunye nokulinganisa uYilo

Ukuqokelela kunye nokuqhuba uvavanyo lokubonisa kwi-hardware exampkuyilo, landela la manyathelo:

1. Qinisekisa i-hardware example mveliso yoyilo igqityiwe.
2. Qalisa isoftware ye-Intel Quartus Prime Pro Edition kwaye uvule /quartus/agi_dp_demo.qpf.
3. Cofa Ukusetyenzwa ➤ Qalisa Ukuhlanganisa.
4. Linda de kugqitywe ukuHlanganisa.

Phawula: Uyilo example ayiqinisekisi ngokusebenzayo uYilo lwaNgaphambi kokuample kwihardware kolukhupho lweQuartus.
Ulwazi olunxulumeneyo
Intel Agilex I-Series FPGA Development Kit Isikhokelo somsebenzisi

1.6. DisplayPort Intel FPGA IP Design Example Parameters
Itheyibhile 2. DisplayPort Intel FPGA IP Design Example Parameters for Intel Agilex F-tile Isixhobo

Ipharamitha	Ixabiso	Inkcazo
Uyilo olukhoyo Eksample
Khetha uyilo	• Akukho nanye • I-DisplayPort SST Parallel I-Loopback ngaphandle kwePCR	Khetha uyilo example izakwenziwa. • Akukho nanye: Akukho mzekelo woyiloample ikhona kukhetho lwangoku lweparameter • I-DisplayPort SST Parallel Loopback ngaphandle kwe-PCR: Olu luyilo example ibonisa i-loopback enxuseneyo ukusuka kwisinki yeDisplayPort ukuya kumthombo weDisplayPort ngaphandle kwemodyuli yePixel Clock yoBuyiselo (PCR) xa ulayita iFayimitha yeFayimitha yoFakelo loNgeniso lweVidiyo.
Uyilo Eksample Files
Ukulinganisa	Layita icima	Layita olu khetho ukwenza okuyimfuneko files yokulinganisa testbench.
Ukudibanisa	Layita icima	Layita olu khetho ukwenza okuyimfuneko files for Intel Quartus Prime ukuhlanganiswa kunye noyilo hardware.
Yenziwe ifomathi yeHDL
Veza File Ifomathi	Verilog, VHDL	Khetha ifomathi oyikhethayo yeHDL yoyilo olwenziweyo example fileiseti. Phawula: Olu khetho lumisela kuphela ifomathi yomgangatho ophezulu we IP ovelisiweyo files. Zonke ezinye files (umz. umzample testbenches kunye nenqanaba eliphezulu files yomboniso wehardware) zikwifomati yeVerilog HDL.
Ikhithi yoPhuhliso ekujoliswe kuyo
Khetha iBhodi	• Akukho Khithi yoPhuhliso • Intel Agilex I-Series Ikhithi yoPhuhliso	Khetha ibhodi yoyilo ekujoliswe kulo example. • Akukho Khithi yoPhuhliso: Olu khetho alubandakanyi yonke imiba yehardware yoyilo example. Undoqo we-IP umisela zonke izabelo ze-pin kwizikhonkwane zenyani. • I-Intel Agilex I-Series FPGA Development Kit: Olu khetho lukhetha ngokuzenzekelayo isixhobo ekujoliswe kuso seprojekthi ukutshatisa isixhobo kule khithi yophuhliso. Ungatshintsha isixhobo ekujoliswe kuso usebenzisa Guqula iDivayisi ekujoliswe kuyo iparamitha ukuba uhlaziyo lwebhodi yakho inomahluko wesixhobo esahlukileyo. I-IP engundoqo ibeka zonke izabelo ze-pin ngokwekhithi yophuhliso. Phawula: Uyilo lwangaphambili EksampLe ayiqinisekiswanga ngokusebenza kwihardware kolukhupho lweQuartus. • Custom Development Kit: Olu khetho luvumela uyilo example iya kuvavanywa kwikhithi yophuhliso lomntu wesithathu kunye ne-Intel FPGA. Kusenokufuneka usete izabelo zepin uwedwa.
	Isixhobo ekujoliswe kuso
Guqula isixhobo ekuJoliswe kuso	Layita icima	Layita olu khetho kwaye ukhethe uhlobo olukhethiweyo lwesixhobo sophuhliso lwekhithi.

Uyilo oluDityanisiweyo lweLoopback ExampLes

Uyilo lweDisplayPort Intel FPGA IP exampLes bonisa i-parallel loopback ukusuka kumzekelo weDisplayPort RX ukuya kumzekelo weDisplayPort TX ngaphandle kwemodyuli yePixel yoBuyiselo lweClock (PCR) ngesantya esingatshintshiyo.
Itheyibhile 3. DisplayPort Intel FPGA IP Design Example for Intel Agilex F-tile Isixhobo

Uyilo Eksample	Ukutyunjwa	Data Rate	Indlela yesiteshi	Uhlobo lweLoopback
I-DisplayPort SST parallel loopback ngaphandle kwePCR	I-DisplayPort SST	HBR3	Simplex	IParallel ngaphandle kwePCR

2.1. Intel Agilex F-ithayile DisplayPort SST Parallel Loopback Design Iimpawu
Uyilo lwe-loopback ye-SST ehambelanayo exampLes bonisa ukuhanjiswa kwevidiyo enye ukusuka kwisinki ye-DisplayPort ukuya kumthombo we-DisplayPort ngaphandle koBuyiselo lweClock yePixel (PCR) ngesantya esingatshintshiyo.

Umzobo 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback ngaphandle PCR

• Kolu tshintsho, iparamitha yomthombo weDisplayPort, TX_SUPPORT_IM_ENABLE, ivuliwe kwaye ujongano lomfanekiso wevidiyo luyasetyenziswa.
• Isinki seDisplayPort sifumana ividiyo kunye okanye ukusasazwa kweaudio kumthombo wevidiyo wangaphandle onje ngeGPU kwaye iyibeke kwi-interface yevidiyo ehambelanayo.
• Imveliso yevidiyo yeDisplayPort iqhubela ngokuthe ngqo ujongano lwevidiyo yomthombo weDisplayPort kunye neekhowudi kwikhonkco eliphambili leDisplayPort ngaphambi kokuba idluliselwe esweni.
• I-IOPLL iqhuba zombini isinki yeDisplayPort kunye neewotshi zevidiyo zomthombo ngamaxesha amiselweyo.
• Ukuba iDisplayPort isinki kunye nomthombo we-MAX_LINK_RATE iparameter ibunjwe ukuba ibe yi-HBR3 kunye ne-PIXELS_PER_CLOCK iqwalaselwe ukuya kwi-Quad, iwotshi yevidiyo ibaleka ku-300 MHz ukuxhasa i-8Kp30 ye-pixel rate (1188/4 = 297 MHz).

2.2. iClock Scheme
Iskimu sewotshi sibonisa imimandla yewotshi kwiDisplayPort Intel FPGA IP yoyilo example.
Umzobo 7. I-Intel Agilex F-tile ye-DisplayPort Transceiver clocking scheme

Itheyibhile 4. Iimpawu zeSkimu sokuValela

Iwotshi kumzobo	Inkcazo
I-SysPLL irefclk	Iwotshi yereferensi yeNkqubo ye-F-tile ye-PLL enokuba yiyo nayiphi na ifrikhwensi yewotshi eyahlulwahlulwa yiNkqubo ye-PLL yaloo maza aphumayo. Kulo mzekelo woyiloample, inkqubo_pll_clk_link kunye ne-rx/tx refclk_link yabelana nge-SysPLL refclk eyi-150Mhz. Kufuneka ibe yiwotshi esebenza simahla edityaniswe kwiqhosha lewotshi yesalathisi ezinikeleyo ukuya kwizibuko lewotshi yegalelo le-Reference kunye neNkqubo ye-PLL Iiwotshi ze-IP, ngaphambi kokudibanisa i-port ephumayo ehambelanayo ne-DisplayPort Phy Top.
inkqubo_pll_clk_link	Ubuncinci benkqubo yePLL yokuphuma rhoqo ukuxhasa yonke ireyithi yeDisplayPort yi-320Mhz. Lo mzekelo woyiloample isebenzisa i-900 Mhz (ephezulu) i-frequency ye-output frequency ukwenzela ukuba i-SysPLL refclk ibe nokwabelana nge-rx/tx refclk_link eyi-150 Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	I-Rx CDR kunye ne-Tx PLL Link refclk elungiswe kwi-150 Mhz ukuxhasa yonke ireyithi yedatha ye-DisplayPort.
rx_ls_clkout/tx Yi-clkout	I-DisplayPort Link Isantya sewotshi kwiwotshi ye-DisplayPort engundoqo we-IP. Amaxesha alingana neRayithi yeDatha yahlula ngobubanzi bedatha obunxuseneyo. Example: Ubuninzi = izinga ledatha / ububanzi bedatha = 8.1G (HBR3) / 40bits = 202.5 Mhz

2.3. Ukulinganisa Testbench
I-testbench yokulinganisa ilinganisa i-DisplayPort TX ye-serial loopback kwi-RX.
Umzobo 8. I-DisplayPort Intel FPGA IP ye-Simplex Mode yokulinganisa i-Testbench Block Diagram

Itheyibhile 5. Izixhobo zeTestbench

Icandelo	Inkcazo
Ijenereyitha yeepateni zeVidiyo	Le jenereyitha ivelisa iipatheni zebha yombala onokuthi uyiqwalasele. Unokwenza iparameterize yefomathi yexesha levidiyo.
Ulawulo lweTestbench	Le bhloko ilawula ukulandelelana kovavanyo lokulinganisa kwaye ivelise iimpawu ezifunekayo zokuvuselela kwi-core TX. Ibhloko yokulawula i-testbench iphinda ifunde ixabiso le-CRC ukusuka kwimithombo yomibini kunye ne-sink ukwenza uthelekiso.
RX Link Isantya Clock Clock umhloli	Lo mkhangeli uyaqinisekisa ukuba i-RX transceiver efunyenweyo iwashi iyahambelana na nesantya sedatha esifunwayo.
TX Link Isantya Clock Clock umhloli	Lo mkhangeli uqinisekisa ukuba i-TX transceiver efunyenweyo iphinda-phinda ihambelana nesantya sedatha esifunwayo.

I-testbench yokulinganisa yenza ezi zingqinisiso zilandelayo:
Itheyibhile 6. Testbench Verifications

Iikhrayitheriya zoVavanyo	Ukuqinisekisa
• Qhagamshelana noQeqesho kwiNqanaba leDatha HBR3 • Funda iirejista ze-DPCD ukujonga ukuba i-DP Status iseti kwaye ilinganisa zombini i-TX kunye ne-RX Link Speed ​​frequency.	Idibanisa i-Frequency Checker ukulinganisa ukuphuma kwesantya sewotshi ye-Link kwi-TX kunye ne-RX transceiver.
• Sebenzisa ipateni yevidiyo ukusuka ku-TX ukuya kwi-RX. • Qinisekisa i-CRC kuzo zombini umthombo kunye nesinki ukujonga ukuba ziyahambelana na	• Dibanisa ipateni yevidiyo kwiMthombo weDisplayPort ukuvelisa ipateni yevidiyo. • Ulawulo lwe-Testbench ngokulandelayo lufunda zombini i-Source kunye ne-Sink CRC esuka kwi-DPTX kunye neerejista ze-DPRX kwaye zithelekise ukuqinisekisa ukuba zombini ixabiso le-CRC liyafana. Phawula: Ukuqinisekisa ukuba i-CRC ibalwa, kufuneka uvule ipharamitha ye-automation ye-CTS yeNkxaso.

Imbali yoHlaziyo yoXwebhu lweDisplayPort Intel

Agilex F-tile FPGA IP Design Example Isikhokelo somsebenzisi

Inguqulelo yoXwebhu	Intel Quartus Prime Version	IP Version	Iinguqu
2021.12.13	21.4	21.0.0	Ukukhutshwa kokuqala.

Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo.
*Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
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Version Online
Ukuzisa impendulo
UG-20347
Isazisi: 709308
Inguqulelo: 2021.12.13

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intel DisplayPort Agilex F-Tile FPGA IP Design Example [pdf] Isikhokelo somsebenzisi DisplayPort Agilex F-Tile FPGA IP Design Example, DisplayPort Agilex, F-Tile FPGA IP Design Example, F-Tile FPGA IP Design, FPGA IP Design Example, IP Design Example, IP Design, UG-20347, 709308

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