FPGA IP
Design Example User Guide
F-Tile 25G Ethernet Intel®
Yakagadziridzwa Intel® Quartus®
Prime Dhizaini Suite: 22.3
IP Shanduro: 1.0.0

Quick Start Guide

Iyo F-tile 25G Ethernet Intel FPGA IP yeIntel Agilex ™ zvishandiso inopa kugona kwekugadzira dhizaini ex.amples yezvirongwa zvakasarudzwa.
Mufananidzo 1. Dhizaini Example Usage

Directory Structure

Mufananidzo 2. 25G Ethernet Intel FPGA IP Dhizaini Example Directory Structure

• The simulation files (testbench yekufananidza chete) iri mukatiample_dir>/example_testbench.
• Iyo yekuunganidza-chete dhizaini example iri muample_dir>/ compilation_test_design.
• Iyo hardware kumisikidza uye bvunzo files (iyo dhizaini example in hardware) vari mukatiample_dir>/hardware_test_design.

Tafura 1. Dhairekitori uye File Tsanangudzo

File Mazita	Tsanangudzo
eth_ex_25g.qpf	Intel Quartus® Prime project file.
eth_ex_25g.qsf	Intel Quartus Prime purojekiti marongero file.
eth_ex_25g.sdc	Synopsys Design Constraints file. Unogona kukopa uye kugadzirisa izvi file kune yako wega 25GbE Intel FPGA IP musimboti dhizaini.
eth_ex_25g.v	Yepamusoro-chikamu Verilog HDL dhizaini example file. Imwe-chiteshi dhizaini inoshandisa Verilog file.
zvakajairika/	Hardware design example support files.
hwtest/main.tcl	Main file yekuwana System Console.

Kugadzira iyo Dhizaini Example

Mufananidzo 4. Exampuye Dhizaini Tab muF-tile 25G Ethernet Intel FPGA IP Parameter Mharidzo

Tevedza nhanho idzi kugadzira iyo hardware dhizaini example uye testbench:

1. MuIntel Quartus Prime Pro Edition, tinya File ➤ New Project Wizard kugadzira itsva Quartus Prime project, kana File ➤ Vhura Project kuvhura iripo Quartus Prime project. Iyo wizard inokukurudzira kuti utaure mudziyo.
2. Mune IP Catalog, tsvaga uye sarudza 25G Ethernet Intel FPGA IP yeAgilex. The New IP Variation hwindo rinoonekwa.
3. Rondedzera zita repamusoro-soro reiyo IP musiyano uye tinya OK. Iyo parameter editor inowedzera yepamusoro-level .ip file kune purojekiti yazvino otomatiki. Kana ukakumbirwa kuti uwedzere nemaoko .ip file kuchirongwa, tinya Chirongwa ➤ Wedzera/ Bvisa Files muProjekti yekuwedzera iyo file.
4. MuIntel Quartus Prime Pro Edition software, iwe unofanirwa kusarudza chaiyo Intel Agilex mudziyo mumudziyo weChishandiso, kana chengetedza mudziyo wakasarudzika uyo Intel Quartus Prime software inokurudzira.
   Cherechedza: Iyo hardware dhizaini example anonyora kusarudzwa nemudziyo pabhodhi rinotarisirwa. Iwe unotsanangura bhodhi rinonangwa kubva kumenyu yedhizaini exampsarudzo mune Example Design tab.
5. Dzvanya OK. Iyo parameter editor inooneka.
6. PaI IP tab, tsanangura maparamita eiyo IP yako musimboti musiyano.
7. Pamusoro peExample Dhizaini tab, yeExample Dhizaini Files, sarudza iyo Simulation sarudzo yekugadzira testbench, uye sarudza iyo Synthesis sarudzo yekugadzira iyo hardware dhizaini ex.ample. Verilog HDL chete files inogadzirwa.
   Cherechedza: Iyo inoshanda VHDL IP musimboti haisi kuwanikwa. Nyora Verilog HDL chete, kune yako IP musimboti dhizaini example.
8. YeTarget Development Kit, sarudza iyo Agilex I-series Transceiver-SoC Dev Kit
9. Dzvanya iyo Gadzira Example Dhizaini bhatani. Sarudza Example Dhizaini Dhairekitori hwindo rinoonekwa.
10. Kana iwe uchida kugadzirisa iyo dhizaini example dhairekitori nzira kana zita kubva kune defaults inoratidzwa (alt_e25_f_0_example_design), tsvaga kunzira nyowani uye nyora iyo nyowani dhizaini exampzita rezita (ample_dir>).
11. Dzvanya OK.

1.2.1. Dhizaini Example Parameters
Tafura 2. Parameters muExampuye Design Tab

Parameter	Tsanangudzo
Example Dhizaini	Aripo example magadzirirwo eiyo IP parameter marongero. Imwe chete chiteshi example dhizaini inotsigirwa neiyi IP.
Example Dhizaini Files	The files kugadzira chikamu chebudiriro chakasiyana. • Kutevedzera—kunoita zvinodiwa files yekutevedzera example design. • Synthesis-inogadzira synthesis files. Shandisa izvi files kuunganidza dhizaini muIntel Quartus Prime Pro Edition software yekuyedza Hardware uye kuita static nguva yekuongorora.
Gadzira File Format	Iyo fomati yeRTL files yekufananidza- Verilog.
Sarudza Bhodhi	Yakatsigirwa hardware yekugadzira dhizaini. Paunosarudza Intel FPGA yekuvandudza bhodhi, shandisa mudziyo AGIB027R31B1E2VRO seChishandiso Chinotariswa chekugadzira ex.ample generation. Agilex I-yakatevedzana Transceiver-SoC Dev Kit: Iyi sarudzo inobvumidza iwe kuti uedze dhizaini ex.ample pane yakasarudzwa Intel FPGA IP yekuvandudza kit. Iyi sarudzo inosarudza otomatiki Target Device yeAGIB027R31B1E2VRO. Kana yako bhodhi revision ine akasiyana mudziyo giredhi, unogona kuchinja chinangwa mudziyo. Hapana: Iyi sarudzo haisanganisi zvinhu zvehardware zveiyo dhizaini example.

1.3. Kugadzira Tile Files

Iyo Tsigiro-Logic Generation inhanho yekutanga-synthesis inoshandiswa kugadzira ine hukama nematairi files inodiwa pakuenzanisa uye dhizaini yehardware. Chizvarwa che tile chinodiwa kune vese
F-tile based design simulations. Iwe unofanirwa kupedzisa danho iri pamberi pekufananidza.

1. Pakuraira kwekukurumidza, famba uchienda kune compilation_test_design folda mune yako yekareample dhizaini: cd /compilation_test_design.
2. Mhanya unotevera kuraira: quartus_tlg alt_eth_25g

1.4. Kutevedzera iyo F-tile 25G Ethernet Intel FPGA IP Dhizaini 
Example Testbench
Iwe unogona kuunganidza uye kutevedzera dhizaini nekumhanyisa script yekufananidza kubva kune yekuraira yekukurumidza.

1. Pakuraira kwekukurumidza, shandura testbench simulating yekushanda dhairekitori: cdample_dir>/ex_25g/sim.
2. Mhanya iyo IP setup simulation:ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Tafura 3. Matanho ekutevedzera Testbench

Simulator	Mirayiridzo
VCS*	Mumutsara wekuraira, nyora sh run_vcs.sh
QuestaSim*	Mumutsara wekuraira, nyora vsim -do run_vsim.do -logfile vsim.log Kana ukasarudza kutevedzera pasina kuunza QuestaSim GUI, nyora vsim -c -do run_vsim.do -logfile vsim.log
Cadence -Xcelium*	Mumutsara wekuraira, nyora sh run_xcelium.sh

Simulation yakabudirira inopera neshoko rinotevera:
Simulation Yakapfuura. kana Testbench yakakwana.
Mushure mekubudirira kupedzisa, unogona kuongorora mhedzisiro.
1.5. Kunyora uye Kugadzirisa Dhizaini Example mu Hardware
Iyo 25G Ethernet Intel FPGA IP yakakosha parameter mupepeti inobvumidza iwe kuunganidza uye kugadzirisa dhizaini ex.ample pane chinangwa chekuvandudza kit.

Kuunganidza uye kugadzirisa dhizaini examppane Hardware, tevera matanho aya:

1. Tangisa Intel Quartus Prime Pro Edition software uye sarudza Kugadzirisa ➤ Tanga Kuunganidza kuunganidza dhizaini.
2. Mushure mekugadzira chinhu cheSRAM file .sof, tevera matanho aya kuronga hardware design examppane iyo Intel Agilex mudziyo:
   a. PaZvishandiso menyu, tinya Programmer.
   b. MuPurogiramu, tinya Hardware Setup.
   c. Sarudza chigadzirwa chepurogiramu.
   d. Sarudza uye wedzera iyo Intel Agilex bhodhi kune yako Intel Quartus Prime Pro Edition chikamu.
   e. Ita shuwa kuti Mode yakaiswa kuna JTAG.
   f. Sarudza iyo Intel Agilex mudziyo uye tinya Wedzera Chishandiso. Iyo Programmer inoratidza
   dhizaini yebhuroka yekubatana pakati pemidziyo iri pabhodhi rako.
   g. Mumutsara ne .sof yako, tarisa bhokisi re .sof.
   h. Tarisa bhokisi riri muPurogiramu/Gadzirisa column.
   i. Click Start.

1.6. Kuedza iyo F-tile 25G Ethernet Intel FPGA IP Hardware Dhizaini Example
Mushure mekunyora iyo F-tile 25G Ethernet Intel FPGA IP musimboti dhizaini example uye gadzirisa pane yako Intel Agilex mudziyo, unogona kushandisa iyo System Console kuronga iyo IP musimboti.
Kuvhura iyo System Console uye kuyedza iyo hardware dhizaini example, tevera matanho aya:

1. MuIntel Quartus Prime Pro Edition software, sarudza Zvishandiso ➤ Sisitimu
   Debugging Zvishandiso ➤ System Console kuvhura iyo system console.
2. MuTcl Console pane, nyora cd hwtest kuti uchinje dhairekitori ku / hardware_test_design/hwtest.
3. Type source main.tcl kuti uvhure chinongedzo kuJTAG master.

Tevedza maitiro ekuedzwa muHardware Testing chikamu cheiyo dhizaini example uye tarisa mhinduro dzebvunzo muSystem Console.

F-tile 25G Ethernet Dhizaini Example yeIntel Agilex Devices

Iyo F-tile 25G Ethernet dhizaini example inoratidza mhinduro yeEthernet yeIntel Agilex zvishandiso uchishandisa iyo 25G Ethernet Intel FPGA IP musimboti.
Gadzira iyo dhizaini exampkubva kuExample Dhizaini tebhu ye25G Ethernet Intel FPGA IP parameter mupepeti. Iwe unogona zvakare kusarudza kugadzira iyo dhizaini ine kana isina
iyo Reed-Solomon Forward Error Correction (RS-FEC) chimiro.
2.1. Zvimiro

• Inotsigira imwe Ethernet chiteshi inoshanda pa25G.
• Inogadzira dhizaini example ine RS-FEC chimiro.
• Inopa testbench uye simulation script.
• Inosimbisa F-Tile Reference uye System PLL Mawachi Intel FPGA IP yakavakirwa paIP kumisikidza.

2.2. Hardware uye Software Zvinodiwa
Intel inoshandisa iyi inotevera Hardware uye software kuyedza iyo dhizaini exampuye mune Linux system:

• Intel Quartus Prime Pro Edition software.
• Siemens* EDA QuestaSim, Synopsys* VCS, uye Cadence Xcelium simulator.
• Intel Agilex I-series Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) yekuedzwa kwehardware.

2.3. Tsanangudzo Inoshanda
Iyo F-tile 25G Ethernet dhizaini example ine MAC+PCS+PMA musimboti musiyano. Aya anotevera block diagraphs anoratidza magadzirirwo emukati uye epamusoro-level masaini eMAC + PCS + PMA musimboti akasiyana muF-tile 25G Ethernet design ex.ample.
Mufananidzo 5. Dhizaini Dhizaini-F-tile 25G Ethernet Dhizaini Example (MAC+PCS+PMA Core Variant)

2.3.1. Dhizaini Zvikamu
Tafura 4. Dhizaini Zvikamu

Chikamu	Tsanangudzo
F-tile 25G Ethernet Intel FPGA IP	Inosanganisira MAC, PCS, uye Transceiver PHY, ine gadziriro inotevera: • Core Variant: MAC+PCS+PMA • Gonesa kudzora kuyerera: Optional • Gonesa chinokanganisa kugadzira: Optional • Gonesa nhanganyaya: Optional • Bvumira kuunganidzwa kwenhamba: Optional • Vhura zviverengero zveMAC zviverengero: Optional • Reference wachi frequency: 156.25 Zvekugadzira example ine RS-FEC chimiro, inotevera yekuwedzera parameter inogadziriswa: • Gonesa RS-FEC: Optional
F-Tile Reference uye System PLL Mawachi Intel FPGA IP	Iyo F-Tile Reference uye System PLL Mawachi Intel FPGA IP parameter edhita marongero anoenderana nezvinodiwa zveF-tile 25G Ethernet Intel FPGA IP. Kana iwe ukagadzira iyo dhizaini example kushandisa Gadzira Example Dhizaini bhatani muIP parameter mupepeti, iyo IP inomisikidza otomatiki. Kana iwe ukagadzira yako dhizaini example, iwe unofanirwa kumisa iyi IP uye ubatanidze ese I/O ports. Kuti uwane ruzivo nezve IP iyi, tarisa kune F-Tile Architecture uye PMA uye FEC Yakananga PHY IP User Guide.
Client logic	Zvinosanganisira: • Traffic jenareta, iyo inogadzira kuputika mapaketi ku25G Ethernet Intel FPGA IP musimboti wekutumira. • Traffic monitor, iyo inoongorora kuputika mapaketi ari kuuya kubva ku25G Ethernet Intel FPGA IP core.
Source uye Probe	Kunobva uye masaini masaini, kusanganisira system reset yekuisa chiratidzo, iyo yaunogona kushandisa kugadzirisa.

Related Information
F-Tile Architecture uye PMA uye FEC Yakananga PHY IP User Guide

Simulation

Iyo testbench inotumira traffic kuburikidza neiyo IP musimboti, ichiita yekufambisa divi uye inogashira divi reiyo IP musimboti.
2.4.1. Testbench
Mufananidzo 6. Block Diagram yeF-tile 25G Ethernet Intel FPGA IP Design Exampuye Simulation Testbench

Tafura 5. Testbench Zvikamu

Chikamu	Tsanangudzo
Mudziyo urikuedzwa (DUT)	Iyo 25G Ethernet Intel FPGA IP musimboti.
Ethernet Packet jenareta uye Packet Monitor	• Packet jenareta inogadzira mafuremu uye ichiendesa kuDUT. • Packet Monitor monitors TX uye RX datapaths uye inoratidza mafuremu mune simulator console.
F-Tile Reference uye System PLL Mawachi Intel FPGA IP	Inogadzira transceiver uye system PLL referensi wachi.

2.4.2. Simulation Dhizaini Example Components
Tafura 6. F-tile 25G Ethernet Dhizaini Example Testbench File Tsanangudzo

File Zita	Tsanangudzo
Testbench uye Simulation Files
basic_avl_tb_top.v	Top-level testbench file. Testbench inosimbisa iyo DUT, inoita Avalon® memory-mapped configuration pane zvigadzirwa zvekugadzira uye mutengi logic, uye inotumira uye inogamuchira pakiti kuenda kana kubva ku25G Ethernet Intel FPGA IP.
Testbench Scripts
akaenderera…

File Zita	Tsanangudzo
run_vsim.do	Iyo ModelSim script yekumhanyisa testbench.
run_vcs.sh	Iyo Synopsys VCS script yekumhanyisa testbench.
run_xcelium.sh	Iyo cadence Xcelium script yekumhanyisa testbench.

2.4.3. Test Case
Iyo simulation test kesi inoita zvinotevera zviito:

1. Instatiates F-tile 25G Ethernet Intel FPGA IP uye F-Tile Reference uye System PLL Mawachi Intel FPGA IP.
2. Inomirira RX wachi uye PHY chimiro chiratidzo kuti igadzirise.
3. Inodhinda chimiro chePHY.
4. Inotumira uye inogamuchira 10 data inoshanda.
5. Anoongorora zvabuda. Iyo yakabudirira testbench inoratidza "Testbench yakakwana.".

Inotevera sample output inoratidza yakabudirira simulation test run:

Compilation

Tevedza maitiro muKunyora uye Kugadzira iyo Dhizaini Example in Hardware kuunganidza uye kugadzirisa iyo dhizaini example mune yakasarudzwa hardware.
Iwe unogona kufungidzira mashandisirwo ezviwanikwa uye Fmax uchishandisa yekuunganidza-chete dhizaini example. Iwe unogona kuunganidza dhizaini yako uchishandisa iyo Start Compilation command pane
Kugadzirisa menyu muIntel Quartus Prime Pro Edition software. Kuunganidzwa kwakabudirira kunoburitsa pfupiso yemushumo wekubatanidza.
Kuti uwane rumwe ruzivo, tarisa kuKugadzira Kubatanidza muIntel Quartus Prime Pro Edition Mushandisi Wekushandisa.
Related Information

• Kunyora uye Kugadzirisa Dhizaini Example in Hardware iri papeji 7
• Dhizaini Kubatanidza MuIntel Quartus Prime Pro Edition Mushandisi Wekushandisa

2.6. Hardware Testing
Mukugadzirwa kwehardware example, unogona kuronga iyo IP musimboti mune yemukati serial loopback modhi uye kugadzira traffic padivi rekutumira iro rinodzokera kumashure kuburikidza nedivi rekugamuchira.
Tevedza maitiro pane yakapihwa inoenderana ruzivo link kuti uedze dhizaini example mune yakasarudzwa hardware.
Related Information
Kuedza iyo F-tile 25G Ethernet Intel FPGA IP Hardware Dhizaini Exampiri papeji 8
2.6.1. Maitiro Ekuyedza
Tevedza matanho aya kuti uedze dhizaini exampmune hardware:

1. Usati wamhanya kuyedza hardware yeiyi dhizaini exampuye, iwe unofanirwa kuseta zvakare system:
   a. Dzvanya Zvishandiso ➤ Mu-System Source & Probes Edhita chishandiso cheiyo default Source uye Probe GUI.
   b. Shandura iyo system reset chiratidzo (Source [3: 0]) kubva 7 kusvika 8 kuti uise reset uye udzorere iyo system reset chiratidzo kudzoka ku7 kuti usunungure sisitimu kubva kumamiriro ekugadzirisa.
   c. Tarisa masaini eProbe uye ona kuti chimiro chiri kushanda.
2. Musystem console, famba uchienda kuhwtest forodha womhanya kuraira: source main.tcl kusarudza J.TAG master. Nekusagadzikana, yekutanga JTAG master paJTAG cheni inosarudzwa. Kusarudza JTAG tenzi weIntel Agilex zvishandiso, mhanyisa uyu murairo: set_jtag <number of appropriate JTAG tenzi>. Example: set_jtag 1.
3. Mhanya iyo inotevera mirairo mune system console kuti utange serial loopback bvunzo:

Tafura 7. Command Parameters

Parameter	Tsanangudzo	Example Usage
chkphy_status	Inoratidza wachi frequency uye PHY kukiya mamiriro.	% chkphy_status 0 # Tarisa chimiro chekubatanidza 0
chkmac_stats	Inoratidza kukosha muMAC statistics counters.	% chkmac_stats 0 # Inotarisa mac statistics counter ye link 0
clear_ all_stats	Inodzima IP core statistics counters.	% clear_all_stats 0 # Inobvisa zviverengero counter ye link 0
start_gen	Inotanga jenareta yepakiti.	% start_gen 0 # Tanga kugadzirwa kwepaketi pane link 0
stop_gen	Inomisa jenareta yepakiti.	% stop_gen 0 # Misa pakiti chizvarwa pane chinongedzo 0
loop_on	Inobatidza mukati serial loopback.	% loop_on 0 # Batidza mukati loopback pane chinongedzo 0
loop_off	Inodzima mukati serial loopback.	% loop_off 0 # Dzima mukati loopback pane chinongedzo 0
reg_read	Inodzosa iyo IP core rerejista kukosha pa .	% reg_read 0x402 # Verenga IP CSR rejista pakero 402 yekubatanidza 0
reg_write	Anonyora kune iyo IP core register pakero .	% reg_write 0x401 0x1 # Nyora 0x1 kuIP CSR scratch rejista pakero 401 yekubatanidza 0

a. Nyora loop_on kuvhura iyo yemukati serial loopback modhi.
b. Nyora chkphy_status kutarisa mamiriro ePHY. Iyo TXCLK, RXCLK, uye RX mamiriro anofanirwa kuve nehumwe hunhu hunoratidzwa pazasi kune yakagadzikana link:

c. Nyora clear_all_stats kubvisa TX uye RX manhamba marejista.
d. Nyora start_gen kutanga packet generation.
e. Nyora stop_gen kumisa kugadzirwa kwepaketi.
f. Nyora chkmac_stats kuverenga iyo TX uye RX nhamba dzekuverenga. Iva nechokwadi chokuti:
i. Mafuremu epaketi anofambiswa anofanana nemafuremu epaketi akagamuchirwa.
ii. Hapana mafuremu ekukanganisa anotambirwa.
g. Nyora loop_off kudzima yemukati serial loopback.
Mufananidzo 7. Sample Test Output-TX uye RX Statistics Counters

Gwaro Revision Nhoroondo yeF-tile 25G Ethernet FPGA IP Dhizaini Example User Guide

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2022.10.14	22.3	1.0.0	Kusunungurwa kwekutanga.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.
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Intel F-Tile 25G Ethernet FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi F-Tile 25G Ethernet FPGA IP Dhizaini Example, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Dhizaini Example, IP Dhizaini Exampuye, 750200

References

• User Manual