F-Tile JESD204C Intel FPGA IP Design Example

Za F-Tile JESD204C Intel® FPGA IP Design Exampndi User Guide

Bukuli limapereka mawonekedwe, malangizo ogwiritsira ntchito, ndi kufotokozera mwatsatanetsatane za kapangidwe kakaleamples za F-Tile JESD204C Intel® FPGA IP pogwiritsa ntchito zida za Intel Agilex™.

Omvera Ofuna

Chikalatachi ndi cha:

• Wopanga mapulani kuti apange chisankho cha IP panthawi yokonzekera dongosolo la dongosolo
• Opanga zida zamagetsi akaphatikiza IP mu kapangidwe kawo kadongosolo
• Mainjiniya otsimikizira panthawi yoyeserera mulingo wamakina ndi gawo lovomerezeka la hardware

Zolemba Zogwirizana
Gome lotsatirali likulemba zolemba zina zomwe zikugwirizana ndi F-Tile JESD204C Intel FPGA IP.

Table 1. Zolemba Zogwirizana

Buku	Kufotokozera
F-Tile JESD204C Intel FPGA IP User Guide	Imapereka zambiri za F-Tile JESD204C Intel FPGA IP.
F-Tile JESD204C Zolemba Zotulutsidwa za Intel FPGA IP	Imalemba zosintha za F-Tile JESD204C F-Tile JESD204C pakutulutsa kwina.
Intel Agilex Device Data Sheet	Chikalatachi chikufotokozera mawonekedwe amagetsi, mawonekedwe osinthira, mafotokozedwe a kasinthidwe, ndi nthawi ya zida za Intel Agilex.

Acronyms ndi Glossary

Table 2. Acronym List

Mwachidule	Kukula
Mtengo wa LEMC	Local Extended Multiblock Clock
FC	Mtengo wa wotchi ya chimango
ADC	Analogi kuti Digital Converter
DAC	Digital to Analogi Converter
DSP	Digital Signal processor
TX	Wotumiza
RX	Wolandira

Mwachidule	Kukula
DLL	Chingwe cholumikizira deta
Mtengo CSR	Control and status register
CRU	Wotchi ndi Bwezerani Unit
ISR	Kusokoneza Nthawi Zonse
FIFO	Choyamba-choyamba-chotuluka
SERDES	Seriizer Deserializer
Mtengo wa ECC	Khodi Yokonza Zolakwika
Mtengo wa FEC	Chotsutsa Cholakwika Chokonzekera
SERR	Kuzindikira Kolakwika Kumodzi (mu ECC, koyenera)
DERR	Kuzindikira Zolakwa Pawiri (mu ECC, zakupha)
PRBS	Pseudorandom binary sequence
MAC	Media Access Controller. MAC imaphatikizapo sublayer ya protocol, gawo la zoyendera, ndi ulalo wa data.
PHY	Physical Gulu. PHY nthawi zambiri imaphatikizapo zosanjikiza zakuthupi, SERDES, madalaivala, olandila ndi CDR.
PCS	Physical Coding Sub-sayer
PMA	Physical Medium Chomangira
Mtengo RBD	Kuchedwa kwa RX Buffer
UI	Unit Interval = nthawi ya serial bit
Mtengo wa RBD	RX Buffer Kuchedwa kufika kwaposachedwa
Kusintha kwa mtengo wa RBD	RX Buffer Kuchedwa kutulutsa mwayi
SH	Gwirizanitsani chamutu
TL	Transport wosanjikiza
EMIB	Mlatho wa Multi-die Interconnect Bridge

Gulu 3. Mndandanda wa Mawu

Nthawi	Kufotokozera
Converter Chipangizo	ADC kapena DAC converter
Logic Chipangizo	FPGA kapena ASIC
Octet	Gulu la ma bits 8, omwe amagwira ntchito ngati cholowera ku 64/66 encoder ndikutulutsa kuchokera ku decoder.
Nibble	Seti ya 4 bits yomwe ndi gawo loyambira la JESD204C
Block	Chizindikiro cha 66-bit chopangidwa ndi 64/66 encoding scheme
Mzere wa Mzere	Kuchuluka kwa data kwa serial link Mzere wa Mzere = (Mx Sx N'x 66/64 x FC) / L
Link Clock	Link Clock = Lane Line Rate/66.
Chimango	Seti ya ma octets otsatizana momwe malo a octet iliyonse amatha kudziwika potengera chizindikiro cholumikizira chimango.
Wotchi ya chimango	Wotchi yamakina yomwe imayenda molingana ndi liwiro la chimango, iyenera kukhala yolumikizira 1x ndi 2x.

Nthawi	Kufotokozera
Sampzochepa pa wotchi ya chimango	Sampkuchepera pa koloko, chiwerengero chonse cha samples mu chimango wotchi kwa Converter chipangizo.
Mtengo wa LEMC	Wotchi yamkati yomwe imagwiritsidwa ntchito kugwirizanitsa malire a multiblock yotalikirapo pakati pa mayendedwe ndi zolozera zakunja (SYSREF kapena Subclass 1).
Gawo 0	Palibe chithandizo cha deterministic latency. Deta iyenera kutulutsidwa nthawi yomweyo pamseu kupita ku deskew pa wolandila.
Gawo 1	Kuzindikira latency pogwiritsa ntchito SYSREF.
Multipoint Link	Imalumikizana ndi zida ziwiri kapena zingapo zosinthira.
Kulemba kwa 64B / 66B	Khodi ya mzere yomwe imayika data ya 64-bit ku 66 bits kuti ipange chipika. Mapangidwe a data yoyambira ndi chipika chomwe chimayamba ndi mutu wa 2-bit sync.

Gulu 4. Zizindikiro

Nthawi	Kufotokozera
L	Chiwerengero cha mayendedwe pa chipangizo chosinthira
M	Chiwerengero cha otembenuza pa chipangizo chilichonse
F	Chiwerengero cha octets pa chimango panjira imodzi
S	Nambala ya sampLes imafalitsidwa pa chosinthira chimodzi pa chimango chozungulira
N	Kusintha kwakusintha
N'	Chiwerengero chonse cha ma bits pa sample mu mawonekedwe a data
CS	Chiwerengero cha zowongolera pa kutembenuka sample
CF	Chiwerengero cha mawu owongolera pa nthawi ya wotchi pa ulalo
HD	High Density user data format
E	Chiwerengero cha multiblock mu multiblock yowonjezera

F-Tile JESD204C Intel FPGA IP Design Exampndi Quick Start Guide

Mapangidwe a F-Tile JESD204C Intel FPGA IP examples pazida za Intel Agilex zimakhala ndi testbench yoyeserera komanso kapangidwe ka Hardware komwe kamathandizira kuphatikiza ndi kuyesa kwa hardware.
Mutha kupanga mawonekedwe a F-Tile JESD204C exampimadutsa pagulu la IP mu pulogalamu ya Intel Quartus® Prime Pro Edition.

Chithunzi 1. Chitukuko Stagndi za Design Example

Design Exampndi Block Diagram

Chithunzi 2. F-Tile JESD204C Design Example High-level Block Diagram

Mapangidwe example ili ndi ma module awa:

• Platform Designer System
  • F-Tile JESD204C Intel FPGA IP
  • JTAG kupita ku Avalon Master Bridge
  • Wolamulira wa Parallel I/O (PIO).
  • Serial Port Interface (SPI)—gawo la master— IOPLL
  • SYSREF jenereta
  • Example Design (ED) Control CSR
  • Bwezerani zotsatizana
• System PLL
• Chitsanzo jenereta
• Chowunikira chitsanzo

Table 5. Design Exampndi ma modules

Zigawo	Kufotokozera
Platform Designer System	Dongosolo la Platform Designer limakhazikitsa njira ya data ya F-Tile JESD204C IP ndikuthandizira zotumphukira.
F-Tile JESD204C Intel FPGA IP	Dongosolo la Platform Designer ili lili ndi ma TX ndi RX F-Tile JESD204C IPs okhazikitsidwa pamodzi ndi duplex PHY.
JTAG kupita ku Avalon Master Bridge	Mlathowu umapereka mwayi wopezera ma IP omwe amakumbukiridwa pamapangidwe kudzera pa JTAG mawonekedwe.
Wolamulira wa Parallel I/O (PIO).	Wowongolera uyu amapereka mawonekedwe okumbukira kukumbukira kwa sampkukhazikika komanso kuyendetsa madoko a I/O.
SPI bwana	Module iyi imayang'anira kusamutsa deta yosinthika ku mawonekedwe a SPI pamapeto osinthira.
SYSREF jenereta	Jenereta ya SYSREF imagwiritsa ntchito wotchi yolumikizira ngati wotchi yolozera ndipo imapanga ma SYSREF amtundu wa F-Tile JESD204C IP. Zindikirani: Mapangidwe awa example amagwiritsa ntchito jenereta ya SYSREF kuwonetsa kuyambika kwa ulalo wa F-Tile JESD204C IP. Mu F-Tile JESD204C subclass 1 system level application, muyenera kupanga SYSREF kuchokera kugwero lomwelo monga wotchi ya chipangizocho.
IOPLL	Mapangidwe awa example amagwiritsa ntchito IOPLL kupanga wotchi yotumizira deta mu F-Tile JESD204C IP.
ED Control CSR	Gawoli limapereka chiwongolero chodziwikiratu cha SYSREF ndi mawonekedwe, ndikuwongolera mawonekedwe ndi mawonekedwe.
Bwezerani zotsatizana	Mapangidwe awa exampLe imakhala ndi 2 sequencers: Bwezerani Njira 0-Imayendetsa kukonzanso ku TX/RX Avalon® domain yosinthira, Avalon-mapped domain, core PLL, TX PHY, TX core, ndi SYSREF jenereta. Bwezeretsani Sequence 1-Imayendetsa kukonzanso ku RX PHY ndi RX core.
System PLL	Gwero la wotchi yoyambira ya F-tile hard IP ndi kuwoloka kwa EMIB.
Chitsanzo jenereta	Jenereta ya chitsanzo imapanga PRBS kapena ramp chitsanzo.
Chowunikira chitsanzo	Chowunikirachi chimatsimikizira PRBS kapena ramp chitsanzo cholandilidwa, ndikuwonetsa cholakwika chikapeza kusagwirizana kwa data sample.

Zofunikira papulogalamu

Intel amagwiritsa ntchito mapulogalamu otsatirawa kuyesa kapangidwe kakaleamplembani mu Linux system:

• Pulogalamu ya Intel Quartus Prime Pro Edition
• Questa*/ModelSim* kapena VCS*/VCS MX simulator

Kupanga Mapangidwe

Kupanga kapangidwe example kuchokera ku IP parameter editor:

1. Pangani pulojekiti yolunjika ku banja la chipangizo cha Intel Agilex F-tile ndikusankha chipangizo chomwe mukufuna.
2. M'gulu la IP, Zida ➤ IP Catalog, sankhani F-Tile JESD204C Intel FPGA IP.
3. Tchulani dzina lapamwamba kwambiri ndi chikwatu cha kusintha kwanu kwa IP. Dinani Chabwino. Mkonzi wa parameter amawonjezera pamwamba .ip file ku polojekiti yamakono basi. Ngati mwapemphedwa kuti muwonjezere pamanja .ip file ku polojekitiyo, dinani Pulojekiti ➤ Onjezani/ Chotsani Files mu Project kuwonjezera ma file.
4. Pansi pa Eksample Design tabu, tchulani kapangidwe kakaleample magawo monga tafotokozera mu Design Exampndi Parameters.
5. Dinani Pangani Exampndi Design.

Pulogalamuyi imapanga mapangidwe onse files m'ma sub-directories. Izi files amafunikira kuyendetsa kayeseleledwe ndi kuphatikiza.

Design Exampndi Parameters
F-Tile JESD204C Intel FPGA IP parameter editor imaphatikizapo Example Design tabu kuti mutchule magawo ena musanapange zojambulazoample.

Table 6. Parameters mu Exampndi Design Tab

Parameter	Zosankha	Kufotokozera
Sankhani Design	System Console Control Palibe	Sankhani system console control kuti mupeze zojambula zakaleample data kudzera pa system console.
Kuyerekezera	Yatsani, Off	Yatsani IP kuti mupange zofunikira files poyerekezera kapangidwe kakaleample.
Kaphatikizidwe	Yatsani, Off	Yatsani IP kuti mupange zofunikira files ya Intel Quartus Prime compilation ndi mawonetsero a hardware.
Mtundu wa HDL (zoyerekeza)	Verilog Chithunzi cha VDHL	Sankhani mtundu wa HDL wa RTL files kwa kayeseleledwe.
Mtundu wa HDL (za kaphatikizidwe)	Verilog yokha	Sankhani mtundu wa HDL wa RTL files kwa kaphatikizidwe.

Parameter	Zosankha	Kufotokozera
Pangani gawo la 3-waya SPI	Yatsani, Off	Yatsani kuti mutsegule mawonekedwe a 3-waya SPI m'malo mwa mawaya anayi.
Sysref mode	Kuwombera kumodzi Nthawi ndi nthawi Pafupipafupi nthawi	Sankhani ngati mukufuna kuti SYSREF igwirizane ndi kuwombera kamodzi, pafupipafupi, kapena kwapang'onopang'ono, kutengera zomwe mukufuna kupanga komanso kusinthasintha kwanthawi. Kuwombera kumodzi-Sankhani izi kuti SYSREF ikhale yowombera kamodzi. The sysref_ctrl[17] registry bit's value ndi 0. Pambuyo pa F-Tile JESD204C IP kukonzanso zosakaniza, sinthani mtengo wa sysref_ctrl[17] registry kuchoka pa 0 mpaka 1, kenako mpaka 0, pakuwombera kumodzi kwa SYSREF. Periodic-SYSREF mu modeic mode ili ndi 50:50 ntchito yozungulira. Nthawi ya SYSREF ndi E*SYSREF_MULP. Gapped periodic—SYSREF ili ndi nthawi yosinthika ya granularity ya 1 link clock cycle. Nthawi ya SYSREF ndi E*SYSREF_MULP. Pakukhazikitsa kwa ntchito zakunja, chipika cha SYSREF chiyenera kutengera 50:50 kuzungulira kwa ntchito. Onani ku SYSREF Jenereta Gawo kuti mudziwe zambiri za SYSREF nthawi.
Sankhani bolodi	Palibe	Sankhani bolodi la kapangidwe kakaleample. Palibe-Kusankhaku sikuphatikiza mbali za Hardware za kapangidwe kakaleample. Ntchito zonse za pini zidzakhazikitsidwa kukhala ma pini enieni.
Chitsanzo Choyesera	Mtengo wa PRBS-7 Mtengo wa PRBS-9 Mtengo wa PRBS-15 Mtengo wa PRBS-23 Ramp	Sankhani jenereta yachitsanzo ndi mtundu woyeserera. Chitsanzo jenereta-JESD204C kuthandiza PRBS chitsanzo jenereta pa deta sample. Izi zikutanthauza kuti m'lifupi mwa deta ndi N + CS njira. PRBS pattern jenereta ndi cheki ndizothandiza popanga ma dataample stimulus yoyesera ndipo sizogwirizana ndi PRBS test mode pa ADC/DAC converter. Ramp Jenereta Yachitsanzo- JESD204C ulalo wosanjikiza umagwira ntchito bwino koma zoyendera pambuyo pake zimayimitsidwa ndipo zolowetsa kuchokera ku fomati sizinyalanyazidwa. Msewu uliwonse umatulutsa mtsinje wofanana wa octet womwe umakwera kuchokera ku 0x00 kupita ku 0xFF ndikubwereza. Ramp mayeso amtundu amathandizidwa ndi prbs_test_ctl. PRBS Pattern Checker-JESD204C PRBS scrambler imadzigwirizanitsa yokha ndipo ikuyembekezeka kuti IP core ikatha kulumikiza ulalo, mbewu yomwe ikukankha ilumikizidwa kale. PRBS kukwapula mbewu idzatenga ma octets 8 kuti muyambe nokha. Ramp Pattern Checker-JESD204C kuthamangitsa ndikudzigwirizanitsa nokha ndipo akuyembekezeka kuti IP Core ikatha kulumikiza ulalo, mbewu yomwe ikukankhayo idalumikizidwa kale. Octet yoyamba yovomerezeka imayikidwa ngati ramp mtengo woyamba. Zomwe zimatsatira ziyenera kuwonjezereka mpaka 0xFF ndikupitilira mpaka 0x00. Ramp Woyang'anira mawonekedwe ayenera kuyang'ana mawonekedwe ofanana panjira zonse.
Yambitsani serial loopback yamkati	Yatsani, Off	Sankhani mkati siriyo loopback.
Yambitsani Command Channel	Yatsani, Off	Sankhani njira yolamula.

Kapangidwe ka Kalozera
Mapangidwe a F-Tile JESD204C example akalozera ali ndi opangidwa files kwa kapangidwe examples.

Chithunzi 3. Kapangidwe ka Kalozera wa F-Tile JESD204C Intel Agilex Design Example

Table 7. Directory Files

Mafoda	Files
ed/rtl	tx j204c_f_tx_ip.qsys j204c_f tx_ss.qsys altera_s10_user_rst_clkgate_0.ip j204c f_se_outbuf_1bit.ip
kayeseleledwe/wophunzitsa	modelim_sim.tcl tb_top_waveform.do
kayeseleledwe/masinopsy	vcs vcs_sim.sh TB_top_wave_ed.do vcsmx vcsmx_sim.sh TB_top_wave_ed.do

Kutsanzira Design Exampndi Testbench

Mapangidwe example testbench imatsanzira kapangidwe kanu kopanga.

Chithunzi 4. Ndondomeko

Kuti muyesere kupanga, chitani izi:

1. Sinthani chikwatu chogwirira ntchito kutiample_design_directory>/simulation/ .
2. Mu mzere wolamula, yendetsani script yoyeserera. Gome ili m'munsiyi likuwonetsa malamulo oyendetsera ma simulators othandizidwa.

Woyeserera	Lamulo
Questa/ModelSim	vsim -do modelim_sim.tcl
	vsim -c -do modelsim_sim.tcl (popanda Questa/ ModelSim GUI)
Zithunzi za VCS	sh vcs_sim.sh
Chithunzi cha VCS MX	sh vcsmx_sim.sh

Kuyerekezera kumathera ndi mauthenga omwe amasonyeza ngati kuthamanga kunapambana kapena ayi.

Chithunzi 5. Kufanizira Bwino
Chiwerengerochi chikuwonetsa uthenga woyeserera bwino wa VCS simulator.

Kupanga Design Example

Kupanga chophatikiza-chokha exampndi polojekiti, tsatirani izi:

1. Onetsetsani kapangidwe kakuphatikiza example generation yatha.
2. Mu pulogalamu ya Intel Quartus Prime Pro Edition, tsegulani pulojekiti ya Intel Quartus Prime Pro Editionample_ design_ directory>/ed/quartus.
3. Pa Processing menyu, dinani Start Compilation.

Kufotokozera Mwatsatanetsatane kwa F-Tile JESD204C Design Example

Mapangidwe a F-Tile JESD204C example akuwonetsa magwiridwe antchito akukhamukira kwa data pogwiritsa ntchito loopback mode.
Mutha kufotokozera zosintha zomwe mwasankha ndikupanga zojambula zakaleample.
Mapangidwe example imapezeka mumitundu iwiri yokha pamitundu yonse ya Base ndi PHY. Mutha kusankha Base kokha kapena PHY zokha koma IP ikhoza kupanga mapangidwe akeample kwa onse a Base ndi PHY.

Zindikirani:  Zosintha zina zapamwamba za data zitha kulephera kusunga nthawi. Kuti mupewe kulephera kwa nthawi, ganizirani kutchula mtengo wocheperako wochulukitsira wotchi (FCLK_MULP) pagawo la Configurations la F-Tile JESD204C Intel FPGA IP parameter editor.

Zida Zadongosolo

Mapangidwe a F-Tile JESD204C example imapereka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe ka kayendetsedwe kake.

Mapangidwe example imathandizira kulumikizana kwa auto mkati ndi kunja kwa loopback modes.

JTAG ku Avalon Master Bridge
Ophunzira a JTAG kupita ku Avalon Master Bridge imapereka kulumikizana pakati pa makina ochitira alendo kuti azitha kugwiritsa ntchito mapu a F-Tile JESD204C IP ndi zotumphukira IP control ndi zolembetsa mbiri kudzera mu J.TAG mawonekedwe.

Chithunzi 6. System yokhala ndi JTAG ku Avalon Master Bridge Core

Zindikirani:  Wotchi yadongosolo iyenera kukhala 2X mwachangu kuposa ma JTAG koloko. Wotchi yadongosolo ndi mgmt_clk (100MHz) pamapangidwe awaample.

Parallel I/O (PIO) Core
Pachimake chofananira / chotulutsa (PIO) chokhala ndi mawonekedwe a Avalon chimapereka mawonekedwe okumbukira kukumbukira pakati pa doko la akapolo la Avalon lokhala ndi mapu komanso madoko a I/O. Madoko a I/O amalumikizana ndi malingaliro a on-chip, kapena ma pin a I/O omwe amalumikizana ndi zida zakunja kwa FPGA.

Chithunzi 7. PIO Core yokhala ndi Madoko Olowetsa, Madoko Otulutsa, ndi IRQ Support
Mwachisawawa, gawo la Platform Designer limalepheretsa Interrupt Service Line (IRQ).

Madoko a PIO I/O amaperekedwa pamlingo wapamwamba kwambiri wa HDL file (io_ mawonekedwe a madoko olowera, io_ control pamadoko otuluka).

Gome ili m'munsili likufotokoza kulumikizidwa kwa siginecha kwa mawonekedwe ndi kuwongolera madoko a I/O kupita ku switch ya DIP ndi LED pa zida zachitukuko.

Table 8. PIO Core I/O Ports

Port	Pang'ono	Chizindikiro
Out_port	0	USER_LED SPI zachitika
	31:1	Zosungidwa
Mu_doko	0	USER_DIP mkati mwa siriyo loopback yatsetsani Off = 1 Pa = 0
	1	USER_DIP FPGA yopangidwa ndi SYSREF yambitsani Off = 1 Pa = 0
	31:2	Zosungidwa.

SPI Master
SPI master module ndi gawo lokhazikika la Platform Designer mu laibulale yokhazikika ya IP Catalog. Gawoli limagwiritsa ntchito protocol ya SPI kuti ithandizire kusinthika kwa otembenuza akunja (mwachitsanzoample, ADC, DAC, ndi ma jenereta a mawotchi akunja) kudzera m'malo olembetsa okonzedwa mkati mwa zidazi.

Mbuye wa SPI ali ndi mawonekedwe okumbukira a Avalon omwe amalumikizana ndi mbuye wa Avalon (JTAG kupita ku Avalon master bridge) kudzera pa Avalon memory-mapped interconnect. Mbuye wa SPI amalandira malangizo osinthira kuchokera kwa mbuye wa Avalon.

SPI master module imawongolera mpaka akapolo 32 odziyimira pawokha a SPI. Mlingo wa SCLK baud umapangidwira 20 MHz (yogawika ndi 5).
Gawoli lakonzedwa kuti likhale ndi mawonekedwe a 4-waya, 24-bit m'lifupi. Ngati njira ya Generate 3-Wire SPI Module yasankhidwa, gawo lowonjezera limakhazikitsidwa kuti lisinthe mawonekedwe a 4-waya a SPI master kukhala 3-waya.

IOPLL
IOPLL imapanga wotchi yofunikira kuti ipange frame_clk ndi link_clk. Wotchi yolozera ku PLL ndi yosinthika koma imangokhala ndi kuchuluka kwa data/chinthu cha 33.

• Za kapangidwe example yomwe imathandizira kuchuluka kwa data 24.33024 Gbps, kuchuluka kwa wotchi ya frame_clk ndi link_clk ndi 368.64 MHz.
• Za kapangidwe example yomwe imathandizira kuchuluka kwa data 32 Gbps, kuchuluka kwa wotchi ya frame_clk ndi link_clk ndi 484.848 MHz.

SYSREF jenereta
SYSREF ndi chizindikiro cha nthawi yovuta kwa otembenuza ma data okhala ndi mawonekedwe a F-Tile JESD204C.

Jenereta ya SYSREF mu kapangidwe kakaleample imagwiritsidwa ntchito ngati duplex JESD204C IP ulalo woyambitsa cholinga chokhacho. Mu JESD204C subclass 1 system level application, muyenera kupanga SYSREF kuchokera kugwero lomwelo monga wotchi ya chipangizocho.

Pa F-Tile JESD204C IP, chochulukitsa cha SYSREF (SYSREF_MULP) cha SYSREF control register imatanthawuza nthawi ya SYSREF, yomwe ndi n-integer multiple of E parameter.

Muyenera kuonetsetsa kuti E*SYSREF_MULP ≤16. Za example, ngati E=1, zochunira zamalamulo za SYSREF_MULP ziyenera kukhala mkati mwa 1–16, ndipo ngati E=3, zokhazikitsira zamalamulo za SYSREF_MULP ziyenera kukhala mkati mwa 1–5.

Zindikirani:  Mukakhazikitsa SYSREF_MULP yakunja, jenereta ya SYSREF ikonza SYSREF_MULP=1.
Mutha kusankha ngati mukufuna kuti mtundu wa SYSREF ukhale wowomberedwa kamodzi, wanthawi ndi nthawi, kapena wapakatikati kudzera pa Ex.ample Design tabu mu F-Tile JESD204C Intel FPGA IP parameter editor.

Table 9. ExampLes of Periodic and Gapped Periodic SYSREF Counter

E	SYSREF_MULP	Nthawi ya SYSREF (E*SYSREF_MULP* 32)	Duty Cycle	Kufotokozera
1	1	32	1..31 (Zotheka)	Gapped Periodic
1	1	32	16 (Zokhazikika)	Nthawi ndi nthawi
1	2	64	1..63 (Zotheka)	Gapped Periodic
1	2	64	32 (Zokhazikika)	Nthawi ndi nthawi
1	16	512	1..511 (Zotheka)	Gapped Periodic
1	16	512	256 (Zokhazikika)	Nthawi ndi nthawi
2	3	19	1..191 (Zotheka)	Gapped Periodic
2	3	192	96 (Zokhazikika)	Nthawi ndi nthawi
2	8	512	1..511 (Zotheka)	Gapped Periodic
2	8	512	256 (Zokhazikika)	Nthawi ndi nthawi
2	9 (Zosaloledwa)	64	32 (Zokhazikika)	Gapped Periodic
2	9 (Zosaloledwa)	64	32 (Zokhazikika)	Nthawi ndi nthawi

 

Table 10. SYSREF Control Registers
Mutha kusinthanso ma registry owongolera a SYSREF ngati zolembetsa zili zosiyana ndi zomwe mudatchula mukamapanga kapangidwe kake.ample. Konzani zolembetsa za SYSREF F-Tile JESD204C Intel FPGA IP isanakhazikitsidwe. Mukasankha jenereta yakunja ya SYSREF kudzera pa
sysref_ctrl[7] register bit, mutha kunyalanyaza zosintha zamtundu wa SYSREF, zochulukitsa, kuzungulira kwa ntchito ndi gawo.

Bits	Mtengo Wofikira	Kufotokozera
sysref_ctrl[1:0]	2'b00: Kuwombera kumodzi 2'b01: Nthawi 2'b10: Nthawi ndi nthawi	Mtundu wa SYSREF. Mtengo wokhazikika umatengera mawonekedwe a SYSREF mu Exampndi Design tabu mu F-Tile JESD204C Intel FPGA IP parameter editor.
sysref_ctrl[6:2]	5'b00001	SYSREF chochulukitsa. Gawo ili la SYSREF_MULP limagwira ntchito pamtundu wa SYSREF wanthawi ndi nthawi. Muyenera kusintha mtengo wochulukitsira kuti mutsimikizire kuti mtengo wa E*SYSREF_MULP uli pakati pa 1 mpaka 16 F-Tile JESD204C IP isanayimitsidwenso. Ngati mtengo wa E*SYSREF_MULP wachoka pagululi, mtengo wochulutsa usintha kukhala 5'b00001.
sysref_ctrl[7]	Duplex datapath: 1'b1 Simplex TX kapena RX datapath: 1'b0	SYSREF kusankha. Mtengo wokhazikika umadalira njira ya data mu Example Design tabu mu F-Tile JESD204C Intel FPGA IP parameter editor. 0: Simplex TX kapena RX (Yakunja SYSREF) 1: Duplex (Mkati SYSREF)
sysref_ctrl[16:8]	9h0 ku	Ntchito ya SYSREF ngati mtundu wa SYSREF umakhala wanthawi ndi nthawi. Muyenera kukonza nthawi yantchito F-Tile JESD204C IP isanayimitsidwenso. Mtengo wokwanira = (E*SYSREF_MULP*32)-1 MwachitsanzoampLe: 50% ya ntchito = (E*SYSREF_MULP*32)/2 Kuzungulira kwantchito kumakhala kosasintha kwa 50% ngati simukonza gawo ili lolembetsa, kapena ngati mukonza gawo lolembetsa kukhala 0 kapena kupitilira mtengo wovomerezeka.
sysref_ctrl[17]	1'b0	Kuwongolera pamanja pamene mtundu wa SYSREF uli ndi chithunzi chimodzi. Lembani 1 kuti muyike chizindikiro cha SYSREF pamwamba. Lembani 0 kuti mutsike chizindikiro cha SYSREF. Muyenera kulemba 1 kenako 0 kuti mupange kugunda kwa SYSREF munjira imodzi yowombera.
sysref_ctrl[31:18]	22h0 ku	Zosungidwa.

Bwezeretsani Sequencers
Mapangidwe awa example ili ndi zotsatizana ziwiri:

• Bwezerani Njira 0-Imayendetsa kukonzanso ku TX/RX Avalon stream domain, Avalon memory-mapped domain, core PLL, TX PHY, TX core, ndi SYSREF jenereta.
• Bwezeretsani Sequence 1-Imayendetsa kukonzanso ku RX PHY ndi RX Core.

3-Waya SPI
Gawoli ndilosankha kusintha mawonekedwe a SPI kukhala 3-waya.

System PLL
F-tile ili ndi ma PLL atatu pa board system. Ma PLL amachitidwe awa ndiye gwero loyambira la wotchi ya IP (MAC, PCS, ndi FEC) ndi kuwoloka kwa EMIB. Izi zikutanthauza kuti, mukamagwiritsa ntchito mawotchi a PLL, zotchinga sizimatsekedwa ndi wotchi ya PMA ndipo sizidalira wotchi yomwe imachokera pachimake cha FPGA. Dongosolo lililonse la PLL limangopanga wotchi yolumikizidwa ndi mawonekedwe amodzi pafupipafupi. Za example, mufunika ma PLL awiri kuti mugwiritse ntchito mawonekedwe amodzi pa 1 GHz ndi mawonekedwe amodzi pa 500 MHz. Kugwiritsa ntchito PLL kumakupatsani mwayi wogwiritsa ntchito njira iliyonse popanda kusintha kwa wotchi yomwe ikukhudza njira yoyandikana nayo.
Dongosolo lililonse la PLL litha kugwiritsa ntchito iliyonse mwa mawotchi asanu ndi atatu a FGT. Ma System PLL amatha kugawana wotchi yolozera kapena kukhala ndi mawotchi osiyanasiyana. Mawonekedwe aliwonse amatha kusankha PLL yomwe imagwiritsa ntchito, koma, ikasankhidwa, imakhazikika, osasinthikanso pogwiritsa ntchito kukonzanso kwamphamvu.

Zambiri Zogwirizana
F-tile Architecture ndi PMA ndi FEC Direct PHY IP User Guide

Zambiri zokhudzana ndi makina a PLL clocking mode mu Intel Agilex F-tile zipangizo.

Chitsanzo jenereta ndi Checker
Jenereta ndi chowunikira ndizothandiza popanga ma data samples ndi kuyang'anira pazolinga zoyezetsa.
Table 11. Anathandiza Pattern Generator

Chitsanzo jenereta	Kufotokozera
PRBS chitsanzo jenereta	Mapangidwe a F-Tile JESD204C example PRBS pattern jenereta imathandizira magawo otsatirawa a polynomials: PRBS23: X23+X18+1 PRBS15: X15+X14+1 PRBS9: X9+X5+1 PRBS7: X7+X6+1
Ramp jenereta ya chitsanzo	The ramp kuchulukitsa kwapateni ndi 1 pa s iliyonse yotsatiraample ndi m'lifupi mwa jenereta ya N, ndikugudubuza ku 0 pamene zonse zimalowa mu sampndi 1. Thandizani ramp jenereta yapatani polemba 1 mpaka 2 ya kaundula wa tst_ctl wa block block ya ED.
Lamulo la njira ramp jenereta ya chitsanzo	Mapangidwe a F-Tile JESD204C example imathandizira command channel ramp jenereta ya chitsanzo pa kanjira. The ramp Kuwonjezeka kwa mtengo wa chitsanzo ndi 1 pa ma bits 6 a mawu olamula. Mbewu yoyambira ndi njira yowonjezeramo panjira zonse.

Table 12. Supported Pattern Checker

Chitsanzo Checker	Kufotokozera
PRBS chowunikira mawonekedwe	Mbeu yopukutira mu choyang'anira pateni imadzigwirizanitsa yokha pomwe F-Tile JESD204C IP ikwaniritsa ma deskew. Chowunikirachi chimafuna ma octet 8 kuti mbewu yopukusa igwirizane yokha.
Ramp chitsanzo chowunika	Deta yoyamba yovomerezeka sample pa chosinthira chilichonse (M) chimayikidwa ngati mtengo woyamba wa ramp chitsanzo. Deta yotsatira sampma values ​​akuyenera kuchulukira ndi 1 pawotchi iliyonse mpaka pamlingo wokulirapo ndikupitilira mpaka 0.

Chitsanzo Checker	Kufotokozera
	Za example, pamene S=1, N=16 ndi WIDTH_MULP = 2, m'lifupi mwa data pa converter ndi S * WIDTH_MULP * N = 32. Deta yaikulu sampmtengo wake ndi 0xFFFF. The ramp Mapattern amatsimikizira kuti mawonekedwe ofanana amalandilidwa pa otembenuza onse.
Lamulo la njira ramp chitsanzo chowunika	Mapangidwe a F-Tile JESD204C example imathandizira command channel ramp chitsanzo chowunika. Liwu loyamba lolamula (6 bits) lolandilidwa limakwezedwa ngati mtengo woyamba. Mawu olamula otsatirawa mumsewu womwewo ayenera kuwonjezereka mpaka 0x3F ndikugudubuza mpaka 0x00. Njira yolamula ramp fufuzani chitsanzo cha ramp mawonekedwe amitundu yonse.

F-Tile JESD204C TX ndi RX IP
Mapangidwe awa example limakupatsani mwayi wokonza TX/RX iliyonse mumayendedwe a simplex kapena duplex mode.
Kukonzekera kwa Duplex kumalola kuwonetsera kwa IP pogwiritsa ntchito mkati kapena kunja kwa serial loopback. Ma CSR mkati mwa IP samakonzedwa kuti alole kuwongolera kwa IP ndikuwona mawonekedwe.

F-Tile JESD204C Design Example Clock ndi Bwezeraninso

Mapangidwe a F-Tile JESD204C example ali ndi seti ya wotchi ndikukhazikitsanso zidziwitso.

Table 13.Design Exampndi Mawotchi

Chizindikiro Clock	Mayendedwe	Kufotokozera
mgmt_clk	Zolowetsa	Wotchi yosiyana ya LVDS yokhala ndi pafupipafupi 100 MHz.
refclk_xcvr	Zolowetsa	Wotchi yolozera ya Transceiver yokhala ndi ma frequency a data rate/factor of 33.
refclk_core	Zolowetsa	Koloko yolozera koloko yokhala ndi ma frequency ofanana ndi refclk_xcvr.
mu_sysref	Zolowetsa	Chizindikiro cha SYSREF. Mafupipafupi a SYSREF ndi kuchuluka kwa data/(66x32xE).
sysref_out	Zotulutsa
txlink_clk rxlink_clk	Zamkati	TX ndi RX yolumikizira wotchi yokhala ndi kuchuluka kwa data / 66.
txframe_clk rxframe_clk	Zamkati	TX ndi RX chimango wotchi yokhala ndi kuchuluka kwa data/33 (FCLK_MULP=2) TX ndi RX chimango wotchi yokhala ndi kuchuluka kwa data/66 (FCLK_MULP=1)
tx_fclk rx_fclk	Zamkati	TX ndi RX gawo wotchi yokhala ndi kuchuluka kwa data/66 (FCLK_MULP=2) TX ndi RX gawo wotchi imakhala yokwera nthawi zonse (1'b1) pamene FCLK_MULP=1
spi_SCLK	Zotulutsa	SPI baud mlingo wotchi ndi pafupipafupi 20 MHz.

Mukanyamula zojambula zakaleampkulowa mu chipangizo cha FPGA, chochitika chamkati cha ninit_done chimatsimikizira kuti JTAG kupita ku Avalon Master mlatho wakonzedwanso komanso midadada ina yonse.

Jenereta ya SYSREF ili ndi kukonzanso kwake kodziyimira pawokha kuyika ubale wadala wa mawotchi a txlink_clk ndi rxlink_clk. Njirayi ndi yokwanira pakutsanzira chizindikiro cha SYSREF kuchokera ku chip wotchi yakunja.

Table 14. Design Exampndi Resets

Bwezerani Chizindikiro	Mayendedwe	Kufotokozera
global_rst_n	Zolowetsa	Kanikizani batani kukonzanso padziko lonse lapansi pama block onse, kupatula JTAG kupita ku Avalon Master Bridge.
ninit_done	Zamkati	Zotuluka kuchokera ku Reset Release IP kwa JTAG kupita ku Avalon Master Bridge.
edctl_rst_n	Zamkati	ED Control block idakhazikitsidwanso ndi JTAG kupita ku Avalon Master Bridge. Madoko a hw_rst ndi global_rst_n samakhazikitsanso chipika cha ED Control.
hw_woyamba	Zamkati	Tsimikizirani ndi dessert hw_rst polemba ku rst_ctl registry ya block ya ED Control. mgmt_rst_in_n amatsimikizira pamene hw_rst atsimikiziridwa.
mgmt_rst_in_n	Zamkati	Bwezeraninso mawonekedwe a Avalon omwe amakumbukiridwa ndi ma IP osiyanasiyana ndi zolowetsa za sequencers:  j20c_reconfig_reset ya F-Tile JESD204C IP duplex Native PHY spi_rst_n ya SPI master pio_rst_n ya PIO udindo ndi kuwongolera reset_in0 doko la sequencer 0 ndi 1 Madoko a global_rst_n, hw_rst, kapena edctl_rst_n akhazikitsidwanso pa mgmt_rst_in_n.
sysref_rst_n	Zamkati	Bwezeraninso chipika cha jenereta cha SYSREF mu chipika cha ED Control pogwiritsa ntchito sequencer 0 reset_out2 port. Kubwezeretsanso sequencer 0 reset_out2 port deassserts kukonzanso ngati core PLL yatsekedwa.
choyambirira_pll_choyamba	Zamkati	Imakonzanso core PLL kudzera mu sequencer 0 reset_out0 port. Pakatikati PLL imayambiranso pamene mgmt_rst_in_n kukonzanso kumatsimikiziridwa.
j204c_tx_avs_rst_n	Zamkati	Imakonzanso mawonekedwe a F-Tile JESD204C TX Avalon-mapu-mapu ojambulidwa kudzera mu sequencer yokonzanso 0. Mawonekedwe a TX Avalon memory-mapped amati mgmt_rst_in_n atsimikiziridwa.
j204c_rx_avs_rst_n	Zamkati	Imakonzanso mawonekedwe a F-Tile JESD204C TX Avalon-mapu-mapu ojambulidwa kudzera mu sequencer yokonzanso 1. Mawonekedwe a RX Avalon memory-mapped amati mgmt_rst_in_n atsimikiziridwa.
j204c_tx_rst_n	Zamkati	Imakonzanso ulalo wa F-Tile JESD204C TX ndi zigawo zoyendera mu txlink_clk, ndi txframe_clk, madambwe. Sequencer 0 reset_out5 imakhazikitsanso doko j204c_tx_rst_n. Izi zotsitsimutsanso ngati core PLL yatsekedwa, ndipo tx_pma_ready ndi tx_ready siginecha zimatsimikiziridwa.
j204c_rx_rst_n	Zamkati	Imakhazikitsanso ulalo wa F-Tile JESD204C RX ndi zigawo zoyendera mu madambwe, rxlink_clk, ndi rxframe_clk.

Bwezerani Chizindikiro	Mayendedwe	Kufotokozera
		Sequencer 1 reset_out4 imakhazikitsanso doko j204c_rx_rst_n. Izi zotsitsimutsanso ngati core PLL yatsekedwa, ndipo rx_pma_ready ndi rx_ready zizindikiro zimatsimikiziridwa.
j204c_tx_rst_ack_n	Zamkati	Bwezeretsani chizindikiro cha kugwirana chanza ndi j204c_tx_rst_n.
j204c_rx_rst_ack_n	Zamkati	Bwezeretsani chizindikiro chakugwirana chanza ndi j204c_rx_rst_n.

Chithunzi 8. Chithunzi cha Nthawi cha Design Exampndi Resets

F-Tile JESD204C Design Exampndi Signals

Table 15. Zizindikiro za Chiyankhulo Chadongosolo

Chizindikiro	Mayendedwe	Kufotokozera
Mawotchi ndi Kukonzanso
mgmt_clk	Zolowetsa	100 MHz wotchi yoyendetsera dongosolo.
refclk_xcvr	Zolowetsa	Wotchi yolozera ya F-tile UX QUAD ndi System PLL. Zofanana ndi kuchuluka kwa data/chinthu cha 33.
refclk_core	Zolowetsa	Wotchi ya Core PLL. Imagwiritsa ntchito mawotchi omwewo monga refclk_xcvr.
mu_sysref	Zolowetsa	Chizindikiro cha SYSREF kuchokera ku jenereta yakunja ya SYSREF ya JESD204C Subclass 1 kukhazikitsa.
sysref_out	Zotulutsa	Chizindikiro cha SYSREF cha JESD204C Subclass 1 kukhazikitsa chopangidwa ndi chipangizo cha FPGA cha kapangidwe kakaleampndi cholinga choyambitsa kugwirizana kokha.

 

Chizindikiro	Mayendedwe	Kufotokozera
SPI
spi_SS_n[2:0]	Zotulutsa	Yotsika yotsika, chizindikiro chosankha akapolo a SPI.
spi_SCLK	Zotulutsa	Wotchi yamtundu wa SPI.
spi_sdio	Zolowetsa/Zotulutsa	Zotulutsa kuchokera kwa mbuye kupita ku kapolo wakunja. Lowetsani zambiri kuchokera ku kapolo wakunja kupita kwa mbuye.

Chizindikiro	Mayendedwe	Kufotokozera
Zindikirani:Pamene Pangani 3-Wire SPI Module njira yayatsidwa.
spi_MISO Zindikirani: Pamene Kupanga 3-Waya SPI Module njira sikuyatsidwa.	Zolowetsa	Lowetsani zambiri kuchokera kwa kapolo wakunja kupita kwa SPI master.
spi_MOSI Zindikirani: Pamene Kupanga 3-Waya SPI Module njira sikuyatsidwa.	Zotulutsa	Zotulutsa kuchokera kwa SPI master kupita kwa kapolo wakunja.

 

Chizindikiro	Mayendedwe	Kufotokozera
ADC / DAC
tx_serial_data[LINK*L-1:0]	Zotulutsa	Kusiyanasiyana kwa data yothamanga kwambiri ku DAC. Wotchiyo imayikidwa mumayendedwe amtundu wa serial data.
tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0]	Zolowetsa	Zosiyanasiyana zamtundu wothamanga kwambiri kuchokera ku ADC. The wotchi anachira kuchokera siriyo deta mtsinje.
rx_serial_data_n[LINK*L-1:0]

 

Chizindikiro	Mayendedwe	Kufotokozera
General Purpose I/O
ogwiritsa_wotsogolera[3:0]	Zotulutsa	Imawonetsa momwe zinthu zilili: [0]: Kukonzekera kwa SPI kwachitika [1]: Cholakwika cha ulalo wa TX [2]: Vuto la ulalo wa RX [3]: Cholakwika choyang'ana pazithunzi za data ya Avalon
user_dip[3:0]	Zolowetsa	Kulowetsa kwa DIP kwa ogwiritsa ntchito: [0]: Yambitsani serial loopback yamkati [1]: SYSREF yopangidwa ndi FPGA yathandizira [3:2]: Wosungidwa

 

Chizindikiro	Mayendedwe	Kufotokozera
Out-of-band (OOB) ndi Status
rx_patchk_data_error[LINK-1:0]	Zotulutsa	Chizindikirochi chikatsimikiziridwa, chimasonyeza kuti chowunika chawona cholakwika.
rx_link_error[LINK-1:0]	Zotulutsa	Chizindikirochi chikanenedwa, chikuwonetsa kuti JESD204C RX IP yanena kuti kusokoneza.
tx_link_error[LINK-1:0]	Zotulutsa	Chizindikirochi chikanenedwa, chikuwonetsa kuti JESD204C TX IP yanena kuti kusokoneza.
emb_lock_out	Zotulutsa	Chizindikirochi chikanenedwa, chimasonyeza kuti JESD204C RX IP yakwaniritsa loko ya EMB.
sh_lock_out	Zotulutsa	Chizindikirochi chikanenedwa, chikuwonetsa mutu wa kulunzanitsa wa JESD204C RX IP watsekedwa.

 

Chizindikiro	Mayendedwe	Kufotokozera
Avalon Streaming
rx_avst_valid[LINK-1:0]	Zolowetsa	Imawonetsa ngati chosinthira sample data pagawo la pulogalamu ndiyovomerezeka kapena yolakwika. 0: Zambiri ndizolakwika 1: Zambiri ndizovomerezeka
rx_avst_data[(TOTAL_SAMPLE*N)-1:0 ]	Zolowetsa	Converter sample data ku gawo la ntchito.

F-Tile JESD204C Design Exampndi Control Registers

Mapangidwe a F-Tile JESD204C exampamalembetsa mu block ya ED Control amagwiritsa ntchito byte-addressing (32 bits).

Table 16. Design Exampndi Adilesi Mapu
Ma register block block a 32-bit ED ali mu domeni ya mgmt_clk.

Chigawo	Adilesi
F-Tile JESD204C TX IP	0x000C_0000 – 0x000C_03FF
F-Tile JESD204C RX IP	0x000D_0000 – 0x000D_03FF
SPI Control	0x0102_0000 – 0x0102_001F
PIO Control	0x0102_0020 – 0x0102_002F
PIO Status	0x0102_0040 – 0x0102_004F
Bwezeretsani Sequencer 0	0x0102_0100 – 0x0102_01FF
Bwezeretsani Sequencer 1	0x0102_0200 – 0x0102_02FF
ED Control	0x0102_0400 – 0x0102_04FF
F-Tile JESD204C IP transceiver PHY Reconfig	0x0200_0000 – 0x023F_FFFF

Table 17. Lembani Mtundu Wofikira ndi Tanthauzo
Gome ili likufotokoza mtundu wopezera kaundula wa Intel FPGA IPs.

Mtundu Wofikira	Tanthauzo
RO/V	Mapulogalamu owerengera-okha (palibe chokhudza kulemba). Mtengo ukhoza kusiyana.
RW	Mapulogalamu amawerenga ndikubweza mtengo waposachedwa. Mapulogalamu amalemba ndikuyika pang'ono pamtengo womwe ukufunidwa.
Mtengo wa RW1C	Mapulogalamu amawerenga ndikubweza mtengo waposachedwa. Mapulogalamu amalemba 0 ndipo alibe zotsatira. Mapulogalamu amalemba 1 ndikuchotsa pang'ono ku 0 ngati pang'onoyo yakhazikitsidwa ku 1 ndi hardware. Hardware imapanga pang'ono kukhala 1. Software clear imakhala yofunika kwambiri kuposa seti ya hardware.

Table 18. ED Control Address Map

Offset	Register Dzina
0x00 pa	woyamba_ctl
0x04 pa	choyamba_st0
anapitiriza…

Offset	Register Dzina
0x10 pa	rst_sts_detected0
0x40 pa	sysref_ctl
0x44 pa	sysref_sts
0x80 pa	tst_ctl
Zamgululi	tst_err0

Table 19. ED Control Block Control and Status Registers

Bwino Offset	Register	Dzina	Kufikira	Bwezerani	Kufotokozera
0x00 pa	woyamba_ctl	choyamba_assert	RW	0x0 pa	Bwezerani zowongolera. [0]: Lembani 1 kuti mutsimikizire kukonzanso. (hw_rst) Lembani 0 kachiwiri kuti mukonzenso dessert. [31:1]: Wosungidwa.
0x04 pa	choyamba_st0	choyamba_status	RO/V	0x0 pa	Bwezerani mawonekedwe. [0]: Core PLL yotsekedwa. [31:1]: Wosungidwa.
0x10 pa	rst_sts_dete cted0	rst_sts_set	Mtengo wa RW1C	0x0 pa	SYSREF m'mphepete mwa mawonekedwe a jenereta yamkati kapena yakunja ya SYSREF. [0]: Mtengo wa 1 Umasonyeza kuti SYSREF yokwera m'mphepete imapezeka pa ntchito ya subclass 1. Mapulogalamu atha kulemba 1 kuti achotse pang'onopang'ono ichi kuti athe kuzindikira m'mphepete mwa SYSREF. [31:1]: Wosungidwa.
0x40 pa	sysref_ctl	sysref_contr ol	RW	Duplex datapath Chithunzi chimodzi: 0x00080	Kuwongolera kwa SYSREF. Onani ku Table 10 patsamba 17 kuti mudziwe zambiri za kagwiritsidwe ntchito ka kaundulayu.
				Nthawi:	Zindikirani: Mtengo wokonzanso umatengera
				0x00081 pa	mtundu wa SYSREF ndi F-Tile
				Pafupipafupi - pafupipafupi:	JESD204C IP data njira zosintha.
				0x00082 pa
				TX kapena RX data
				njira
				Kuwombera kumodzi:
				0x00000 pa
				Nthawi:
				0x00001 pa
				Zosiyana-
				pafupipafupi:
				0x00002 pa
0x44 pa	sysref_sts	sysref_statu s	RO/V	0x0 pa	Chithunzi cha SYSREF. Regista iyi ili ndi nthawi yaposachedwa ya SYSREF komanso zosintha zantchito za jenereta yamkati ya SYSREF. Onani ku Table 9 patsamba 16 za mtengo wamalamulo wanthawi ya SYSREF ndi nthawi yantchito.
anapitiriza…

Bwino Offset	Register	Dzina	Kufikira	Bwezerani	Kufotokozera
					[8:0]: Nthawi ya SYSREF. Pamene mtengo ndi 0xFF, ndi Nthawi ya SYSREF = 255 Pamene mtengo ngati 0x00, nthawi ya SYSREF = 256. [17:9]: SYSREF ntchito kuzungulira. [31:18]: Wosungidwa.
0x80 pa	tst_ctl	tst_control	RW	0x0 pa	Kuwongolera mayeso. Gwiritsani ntchito regista iyi kuti mutsegule mitundu yosiyanasiyana yoyeserera ya jenereta yapateni ndi chowunikira. [1:0] = Munda wosungidwa [2] = ramp_test_ctl 1'b0 = Imathandizira jenereta ya PRBS ndi chowunikira 1'b1 = Imathandiza ramp jenereta ya chitsanzo ndi checker [31:3]: Wosungidwa.
Zamgululi	tst_err0	tst_error	Mtengo wa RW1C	0x0 pa	Mbendera yolakwika ya Link 0. Pamene pang'ono ndi 1'b1, zimasonyeza kuti cholakwika chachitika. Muyenera kuthetsa cholakwikacho musanalembe 1'b1 kuti muchotse cholakwikacho. [0] = Cholakwika choyang'ana chitsanzo [1] = tx_link_error [2] = rx_link_error [3] = Cholakwika choyang'ana chalamulo [31:4]: Chosungidwa.

Mbiri Yokonzanso Zolemba za F-Tile JESD204C Intel FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2021.10.11	21.3	1.0.0	Kutulutsidwa koyamba.

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