DisplayPort Agilex F-Tile FPGA IP Design Example
Wogwiritsa Ntchito
Zasinthidwa kwa Intel® Quartus® Prime Design Suite: 21.4
Mtundu wa IP: 21.0.0

DisplayPort Intel FPGA IP Design Exampndi Quick Start Guide

Mapangidwe a DisplayPort Intel® FPGA IP examples pazida za Intel Agilex™ F-tile zimakhala ndi testbench yoyeserera komanso kapangidwe kazinthu kazinthu zomwe zimathandizira kuphatikiza ndi kuyesa kwa hardware.
DisplayPort Intel FPGA IP imapereka mawonekedwe otsatirawaampzochepa:

• DisplayPort SST parallel loopback popanda gawo la Pixel Clock Recovery (PCR) pamlingo wokhazikika

Mukapanga zojambula zakaleampndi, mkonzi wa parameter amangopanga files zofunika kuyerekezera, kusonkhanitsa, ndi kuyesa mapangidwe mu hardware.
Zindikirani: Pulogalamu ya Intel Quartus® Prime 21.4 imangothandiza Preliminary Design Example pazolinga za Kuyerekezera, Kaphatikizidwe, Kuphatikiza, ndi Kusanthula Nthawi. Kugwira ntchito kwa Hardware sikunatsimikizidwe mokwanira.
Chithunzi 1. Chitukuko Stages

Zambiri Zogwirizana

• DisplayPort Intel FPGA IP User Guide
• Kusamukira ku Intel Quartus Prime Pro Edition

1.1. Kapangidwe ka Kalozera
Chithunzi 2. Kalozera Kapangidwe

Table 1. Design Exampndi Components

Mafoda	Files
rtl/core	dp_core.ip
	dp_rx.ip
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((chida chomangira cha DP PMA UX)
	dp_rx_data_fifo.ip
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((chida chomangira cha DP PMA UX)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Zofunikira pa Hardware ndi Mapulogalamu
Intel imagwiritsa ntchito zida ndi mapulogalamu otsatirawa kuyesa kapangidwe kakaleampLe:
Zida zamagetsi

• Intel Agilex I-Series Development Kit

Mapulogalamu

• Intel Quartus Prime
• Synopsy * VCL Simulator

1.3. Kupanga Mapangidwe
Gwiritsani ntchito DisplayPort Intel FPGA IP parameter editor mu Intel Quartus Prime software kuti mupange zojambulazoample.
Chithunzi 3. Kupanga Mapangidwe Oyenda

1. Sankhani Zida ➤ IP Catalog, ndikusankha Intel Agilex F-tile ngati banja lazida zomwe mukufuna.
   Chidziwitso: Mapangidwe a example imangothandizira zida za Intel Agilex F-tile.
2. Mu Catalog ya IP, pezani ndikudina kawiri DisplayPort Intel FPGA IP. Zenera la New IP Variation likuwonekera.
3. Tchulani dzina lapamwamba lamitundu yanu ya IP. Mkonzi wa parameter amasunga zosintha za IP mu a file dzina .ip.
4. Mutha kusankha chipangizo china cha Intel Agilex F-tile m'munda wa Chipangizo, kapena sungani chosankha cha pulogalamu ya Intel Quartus Prime.
5. Dinani Chabwino. The parameter editor ikuwonekera.
6. Konzani magawo omwe mukufuna a TX ndi RX
7. Pa Design Examppa tabu, sankhani DisplayPort SST Parallel Loopback Popanda PCR.
8. Sankhani Kayeseleledwe kupanga testbench, ndi kusankha kaphatikizidwe kupanga hardware kapangidwe example. Muyenera kusankha chimodzi mwazosankha izi kuti mupange zojambula zakaleample files. Ngati musankha zonse ziwiri, nthawi ya m'badwo ndi yayitali.
9. Dinani Pangani Exampndi Design.

1.4. Kutsanzira Mapangidwe
Mapangidwe a DisplayPort Intel FPGA IP example testbench imatengera kapangidwe ka serial loopback kuchokera pa TX kupita ku RX. Gawo lamkati la jenereta lamavidiyo limayendetsa chiwonetsero cha DisplayPort TX ndipo mawonekedwe a kanema a RX amalumikizana ndi zowunikira za CRC mu testbench.
Chithunzi 4. Kupanga Kuyerekeza Kuyenda

1. Pitani ku chikwatu cha Synopsys simulator ndikusankha VCS.
2. Thamangani script yoyeserera.
   Gwero vcs_sim.sh
3. Zolemba zimapanga Quartus TLG, zimaphatikiza ndikuyendetsa testbench mu simulator.
4. Unikani zotsatira zake.
   Kuyerekeza kopambana kumatha ndi kufananitsa kwa Source ndi Sink SRC.

1.5. Kupanga ndi Kutsanzira Mapangidwe
Chithunzi 5. Kupanga ndi Kutsanzira Mapangidwe

Kupanga ndikuyesa kuyesa kwachiwonetsero pa hardware example design, tsatirani izi:

1. Onetsetsani kuti hardware example design generation yatha.
2. Yambitsani pulogalamu ya Intel Quartus Prime Pro Edition ndikutsegula /quartus/agi_dp_demo.qpf.
3. Dinani Kukonza ➤ Yambani Kuphatikiza.
4. Dikirani mpaka Compilation imalize.

Zindikirani: Mapangidwe example sichimatsimikizira kuti Preliminary Design Example pa hardware mu kutulutsidwa kwa Quartus.
Zambiri Zogwirizana
Intel Agilex I-Series FPGA Development Kit User Guide

1.6. DisplayPort Intel FPGA IP Design Exampndi Parameters
Table 2. DisplayPort Intel FPGA IP Design Example Ma Parameters a Intel Agilex F-tile Chipangizo

Parameter	Mtengo	Kufotokozera
Mapangidwe Opezeka Example
Sankhani Design	• Palibe • DisplayPort SST Parallel Loopback popanda PCR	Sankhani chitsanzo chojambulaample kuti apangidwe. • Palibe: Palibe kapangidwe kakaleample likupezeka pakusankha kwa parameter pano • DisplayPort SST Parallel Loopback popanda PCR: Kapangidwe kameneka kaleample imawonetsa kubwereza kofananira kuchokera kusinki ya DisplayPort kupita kugwero la DisplayPort popanda gawo la Pixel Clock Recovery (PCR) mukayatsa gawo la Yambitsani Chithunzi Chojambula cha Video.
Design Example Files
Kuyerekezera	Yatsani, Off	Yatsani izi kuti mupange zofunikira files ya testbench yoyeserera.
Kaphatikizidwe	Yatsani, Off	Yatsani izi kuti mupange zofunikira files ya Intel Quartus Prime compilation ndi hardware design.
Mtundu Wopangidwa wa HDL
Pangani File Mtundu	Verilog, VHDL	Sankhani mtundu womwe mumakonda wa HDL wamapangidwe opangidwa kaleample fileset. Zindikirani: Izi zimangotsimikizira mtundu wa IP yapamwamba yopangidwa files. Zina zonse files (mwachitsanzo Eksample testbenches ndi mlingo wapamwamba files zowonetsera za hardware) zili mu mtundu wa Verilog HDL.
Chida Chachitukuko cha Target
Sankhani Board	• Palibe Zida Zachitukuko • Intel Agilex I-Series Zida Zachitukuko	Sankhani bolodi la mapangidwe omwe mukufunaample. • No Development Kit: Izi sizikuphatikiza mbali zonse za Hardware za kapangidwe kakaleample. IP core imayika magawo onse a pini kukhala ma pini enieni. • Intel Agilex I-Series FPGA Development Kit: Njira iyi imangosankha chipangizo chandamale cha polojekiti kuti chigwirizane ndi chipangizo chomwe chili pazitukukozi. Mutha kusintha chipangizo chomwe mukufuna kugwiritsa ntchito Change Target Device parameter ngati bolodi lanu liri ndi chida chosiyana. IP core imayika magawo onse a pini malinga ndi zida zachitukuko. Zindikirani: Preliminary Design Example silinatsimikizidwe bwino pa hardware mu kutulutsidwa kwa Quartus. • Custom Development Kit: Njira iyi imalola zojambula zakaleample kuti ayesedwe pa zida zachitukuko chachitatu ndi Intel FPGA. Mungafunike kukhazikitsa ma pin assignments nokha.
	Chida Cholowera
Sinthani Chipangizo Chotsatira	Yatsani, Off	Yatsani njira iyi ndikusankha chosinthira chomwe mumakonda cha zida zachitukuko.

Parallel Loopback Design Examples

Mapangidwe a DisplayPort Intel FPGA IP examples kuwonetsa kubwereza kofananira kuchokera pachiwonetsero cha DisplayPort RX kupita ku DisplayPort TX popanda gawo la Pixel Clock Recovery (PCR) pamlingo wokhazikika.
Table 3. DisplayPort Intel FPGA IP Design Example kwa Intel Agilex F-tile Chipangizo

Design Example	Kusankhidwa	Mtengo wa Data	Njira Yama Channel	Mtundu wa Loopback
DisplayPort SST kufanana loopback popanda PCR	Chithunzi cha DisplayPort SST	Zamgululi	Simplex	Kufanana popanda PCR

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Features
SST parallel loopback design exampLes kuwonetsa kutumiza kwa vidiyo imodzi kuchokera kusinki ya DisplayPort kupita ku DisplayPort gwero popanda Pixel Clock Recovery (PCR) pamlingo wokhazikika.

Chithunzi 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback popanda PCR

• M'mitundu iyi, gawo la DisplayPort source, TX_SUPPORT_IM_ENABLE, limayatsidwa ndipo mawonekedwe amakanema amagwiritsidwa ntchito.
• Sinki ya DisplayPort imalandira makanema kapena kutulutsa mawu kuchokera kugwero lakunja lamavidiyo monga GPU ndikuisintha kukhala mawonekedwe ofanana ndi makanema.
• Kutulutsa kwamavidiyo a DisplayPort kumayendetsa mwachindunji mawonekedwe a kanema wa DisplayPort ndikuyika pa ulalo waukulu wa DisplayPort musanatumize ku polojekiti.
• IOPLL imayendetsa masinki onse a DisplayPort ndi mawotchi amakanema pafupipafupi.
• Ngati DisplayPort sinki ndi MAX_LINK_RATE magawo ake asinthidwa kukhala HBR3 ndipo PIXELS_PER_CLOCK asinthidwa kukhala Quad, wotchi ya kanema imayenda pa 300 MHz kuti igwirizane ndi 8Kp30 pixel rate (1188/4 = 297 MHz).

2.2. Clock Scheme
Chiwembu chowotchera chikuwonetsa madera omwe ali mu DisplayPort Intel FPGA IP kapangidwe kakeample.
Chithunzi 7. Intel Agilex F-tile DisplayPort Transceiver clocking scheme

Table 4. Zizindikiro za Clock Scheme

Wotchi pachithunzi	Kufotokozera
Kusintha kwa SysPLL	Wotchi ya F-tile System PLL yomwe imatha kukhala mawotchi aliwonse omwe amatha kugawidwa ndi System PLL pama frequency omwe amachokera. M'mapangidwe awa example, system_pll_clk_link ndi rx/tx refclk_link akugawana SysPLL refclk yomwe ili 150Mhz. Iyenera kukhala wotchi yaulere yomwe imalumikizidwa kuchokera pa wotchi yodzipatulira ya transceiver kupita ku doko lolowera la Reference ndi System PLL Clocks IP, musanalumikizane ndi doko lofananira ndi DisplayPort Phy Top.
system_pll_clk_link	Kuchepa kwapang'onopang'ono kwa System PLL kuthandizira chiwonetsero chonse cha DisplayPort ndi 320Mhz. Mapangidwe awa example amagwiritsa 900 Mhz (zapamwamba) zotulutsa pafupipafupi kuti SysPLL refclk itha kugawidwa ndi rx/tx refclk_link yomwe ili 150 Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	Rx CDR ndi Tx PLL Link refclk yomwe idakhazikika ku 150 Mhz kuti ithandizire kuchuluka kwa data ya DisplayPort.
rx_ls_clkout/tx Ndi clkout	DisplayPort Link Speed ​​​​Clock kuti mutsegule pachimake cha DisplayPort IP. Mafupipafupi ofanana ndi Deta Rate gawani ndi data yofananira m'lifupi mwake. ExampLe: Frequency = kuchuluka kwa data / kuchuluka kwa data = 8.1G (HBR3) / 40bits = 202.5Mhz

2.3. Simulation Testbench
Testbench yoyeserera imatsanzira DisplayPort TX serial loopback ku RX.
Chithunzi 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram

Table 5. Zida za Testbench

Chigawo	Kufotokozera
Video Pattern Generator	Jenereta iyi imapanga mitundu ya mipiringidzo yomwe mutha kuyikonza. Mukhoza parameterize kanema mtundu nthawi.
Testbench Control	Chida ichi chimayang'anira kutsatizana koyeserera ndikupangira zidziwitso zofunikira pakatikati pa TX. Chotchinga chowongolera cha testbench chimawerengeranso mtengo wa CRC kuchokera kugwero ndi kuzama kuti mufananize.
RX Link Speed ​​​​Clock Frequency Checker	Chowunikirachi chimatsimikizira ngati ma transceiver a RX omwe adachira mawotchi amafanana ndi zomwe mukufuna.
TX Link Speed ​​​​Clock Frequency Checker	Chowunikirachi chimatsimikizira ngati ma transceiver a TX omwe adachira mawotchi amafanana ndi kuchuluka kwa data komwe mukufuna.

Testbench yoyeserera imatsimikizira izi:
Table 6. Testbench Verifications

Zoyeserera	Kutsimikizira
• Lumikizani Maphunziro pa Data Rate HBR3 • Werengani ma registanti a DPCD kuti muwone ngati DP Status imakhazikitsa ndikuyesa ma frequency a TX ndi RX Link Speed.	Imaphatikiza Frequency Checker kuyeza ma frequency a Link Speed ​​wotchi kuchokera pa TX ndi RX transceiver.
• Kuthamanga kanema chitsanzo kuchokera TX kuti RX. • Tsimikizirani gwero ndi sinki ya CRC kuti muwone ngati ikugwirizana	• Imalumikiza jenereta ya mavidiyo ku DisplayPort Source kuti ipangitse mawonekedwe a kanema. • Kuwongolera kwa Testbench kumawerengera onse Source ndi Sink CRC kuchokera ku DPTX ndi DPRX registry ndikuyerekeza kuti zitsimikizire kuti ma CRC onse ndi ofanana. Zindikirani: Kuti muwonetsetse kuti CRC yawerengedwa, muyenera kuyatsa gawo la Support CTS test automation parameter.

Mbiri Yokonzanso Zolemba za DisplayPort Intel

Agilex F-tile FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2021.12.13	21.4	21.0.0	Kutulutsidwa koyamba.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
*Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
ISO 9001: 2015 Adalembetsa

Baibulo Lomasulira
Tumizani Ndemanga
UG-20347
ID: 709308
Mtundu: 2021.12.13

Zolemba / Zothandizira

Intel DisplayPort Agilex F-Tile FPGA IP Design Example [pdf] Buku Logwiritsa Ntchito DisplayPort Agilex F-Tile FPGA IP Design Example, DisplayPort Agilex, F-Tile FPGA IP Design Example, F-Tile FPGA IP Design, FPGA IP Design Exampndi, IP Design Example, IP Design, UG-20347, 709308

Maumboni

• Buku Logwiritsa Ntchito