FPGA IP
Design Exampndi User Guide
F-Tile 25G Ethernet Intel®
Zasinthidwa kwa Intel® Quartus®
Prime Design Suite: 22.3
Mtundu wa IP: 1.0.0

Quick Start Guide

F-tile 25G Ethernet Intel FPGA IP ya zida za Intel Agilex™ imapereka kuthekera kopanga mapangidwe apangidweamples kwa masinthidwe osankhidwa.
Chithunzi 1. Design Exampndi Kugwiritsa

Kapangidwe ka Kalozera

Chithunzi 2. 25G Ethernet Intel FPGA IP Design Exampndi Kapangidwe ka Directory

• Kayeseleledwe files (testbench for simulation only) ali mkatiample_dir>/example_testbench.
• Kapangidwe kophatikiza kokha example ili muample_dir>/ compilation_test_design.
• Kukonzekera kwa hardware ndi kuyesa files (Design example in hardware) zili mkatiample_dir>/hardware_test_design.

Table 1. Directory ndi File Kufotokozera

File Mayina	Kufotokozera
eth_ex_25g.qpf	Intel Quartus® Prime Project file.
eth_ex_25g.qsf	Zokonda pa Intel Quartus Prime project file.
eth_ex_25g.sdc	Zolepheretsa Zopanga za Synopsys file. Mutha kukopera ndikusintha izi file pakupanga kwanu koyambira kwa 25GbE Intel FPGA IP.
eth_ex_25g.v	Mapangidwe apamwamba a Verilog HDL example file. Kupanga kwanjira imodzi kumagwiritsa ntchito Verilog file.
wamba/	Mapangidwe a Hardware exampndi support files.
hwtest/main.tcl	Chachikulu file kuti mupeze System Console.

Kupanga Design Example

Chithunzi 4. Example Design Tab mu F-tile 25G Ethernet Intel FPGA IP Parameter Editor

Tsatirani izi kuti mupange mawonekedwe a Hardware example ndi testbench:

1. Mu Intel Quartus Prime Pro Edition, dinani File ➤ Project Wizard Watsopano kuti apange polojekiti yatsopano ya Quartus Prime, kapena File ➤ Tsegulani Project kuti mutsegule pulojekiti yomwe ilipo ya Quartus Prime. Wizard imakulimbikitsani kuti mutchule chipangizo.
2. Mu Catalog ya IP, pezani ndikusankha 25G Ethernet Intel FPGA IP ya Agilex. Zenera la New IP Variation likuwonekera.
3. Tchulani dzina lapamwamba la IP yanu ndipo dinani OK. Mkonzi wa parameter amawonjezera pamwamba .ip file ku polojekiti yamakono basi. Ngati mwapemphedwa kuti muwonjezere pamanja .ip file ku polojekitiyo, dinani Pulojekiti ➤ Onjezani/ Chotsani Files mu Project kuwonjezera ma file.
4. Mu pulogalamu ya Intel Quartus Prime Pro Edition, muyenera kusankha chipangizo china cha Intel Agilex pagawo la Chipangizo, kapena kusunga chipangizo chokhazikika chomwe pulogalamu ya Intel Quartus Prime ikufuna.
   Zindikirani: Mapangidwe a hardware example overwrites kusankha ndi chipangizo pa chandamale bolodi. Mumatchula bolodi lomwe mukufuna kuchokera pamenyu ya kapangidwe kakaleample options mu Exampndi Design tabu.
5. Dinani Chabwino. The parameter editor ikuwonekera.
6. Pa tabu ya IP, tchulani magawo akusintha kwanu kwa IP.
7. Pa Eksample Design tabu, ya Eksampndi Design Files, sankhani njira yoyeserera kuti mupange testbench, ndikusankha njira ya kaphatikizidwe kuti mupange kapangidwe ka Hardware ex.ample. Verilog HDL yokha files amapangidwa.
   Zindikirani: IP yogwira ntchito ya VHDL IP palibe. Tchulani Verilog HDL yokha, ya IP core design example.
8. Kwa Target Development Kit, sankhani Agilex I-series Transceiver-SoC Dev Kit
9. Dinani Pangani Exampndi Design batani. Sankhani Exampzenera la Design Directory likuwonekera.
10. Ngati mukufuna kusintha kapangidwe examplembani njira kapena dzina kuchokera pazosintha zomwe zikuwonetsedwa (alt_e25_f_0_example_design), sakatulani njira yatsopano ndikulemba mawonekedwe atsopanoample directory name (ample_dir>).
11. Dinani Chabwino.

1.2.1. Kupanga Eksampndi Parameters
Table 2. Parameters mu Exampndi Design Tab

Parameter	Kufotokozera
Exampndi Design	Zopezeka kaleample amapangira zoikamo za IP parameter. Njira imodzi yokha example design imathandizidwa ndi IP iyi.
Exampndi Design Files	The files kuti apange magawo osiyanasiyana a chitukuko. • Kuyerekezera—kumapanga zofunika files poyerekezera ndi exampkupanga. • Kaphatikizidwe—kumapanga kaphatikizidwe files. Gwiritsani ntchito izi files kuti apange mapangidwe mu pulogalamu ya Intel Quartus Prime Pro Edition yoyesa ma hardware ndi kusanthula nthawi.
Pangani File Mtundu	Chithunzi cha RTL files kwa kayeseleledwe-Verilog.
Sankhani Board	Zida zothandizira kuti zitheke kupanga mapangidwe. Mukasankha gulu lachitukuko la Intel FPGA, gwiritsani ntchito chipangizo cha AGIB027R31B1E2VRO ngati Chipangizo Chotsatira cha kapangidwe kakale.ampndi generation. Agilex I-Series Transceiver-SoC Dev Kit: Njira iyi imakupatsani mwayi woyesa kapangidwe kake.ample pa zida zosankhidwa za Intel FPGA IP. Izi njira basi kusankha Target Chipangizo cha AGIB027R31B1E2VRO. Ngati kubwereza kwa board yanu kuli ndi giredi yosiyana ya chipangizo, mutha kusintha chipangizo chomwe mukufuna. Palibe: Izi sizikuphatikiza mbali za Hardware za kapangidwe kakaleample.

1.3. Kupanga Tile Files

The Support-Logic Generation ndi sitepe yophatikizika yomwe imagwiritsidwa ntchito popanga zokhudzana ndi matayala files zofunika pa kayeseleledwe ndi hardware kapangidwe. Kupanga matayala ndikofunikira kwa onse
F-tile based design zofananira. Muyenera kumaliza sitepe iyi musanayerekeze.

1. Pakulamula, pitani ku foda ya compilation_test_design mu exampndi design: cd /compilation_test_design.
2. Thamangani lamulo ili: quartus_tlg alt_eth_25g

1.4. Kutengera F-tile 25G Ethernet Intel FPGA IP Design 
Exampndi Testbench
Mutha kuphatikizira ndikufanizira kapangidwe kake poyendetsa script yoyeserera kuchokera pagawo lolamula.

1. Pakulamula, sinthani chikwatu cha testbench yoyeserera ntchito: cdample_dir>/ex_25g/sim.
2. Yambitsani kayeseleledwe ka IP:ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Table 3. Njira Zotsanzira Testbench

Woyeserera	Malangizo
VCS*	Mu mzere wolamula, lembani sh run_vcs.sh
QuestaSim*	Mu mzere wolamula, lembani vsim -do run_vsim.do -logfile vsim.log Ngati mukufuna kutsanzira popanda kubweretsa QuestaSim GUI, lembani vsim -c -do run_vsim.do -logfile vsim.log
Cadence -Xcelium*	Mu mzere wolamula, lembani sh run_xcelium.sh

Kuyerekeza kopambana kumatha ndi uthenga wotsatirawu:
Kuyerekezera Kwadutsa. kapena Testbench wamaliza.
Mukamaliza bwino, mutha kusanthula zotsatira.
1.5. Kupanga ndi Kukonza Design Exampndi mu Hardware
25G Ethernet Intel FPGA IP core parameter editor imakulolani kuti muphatikize ndikukonzekera zojambulazo.ample pa zida zachitukuko zomwe mukufuna.

Kupanga ndi kukonza kapangidwe examppa hardware, tsatirani izi:

1. Yambitsani pulogalamu ya Intel Quartus Prime Pro Edition ndikusankha Kukonzekera ➤ Yambani Kuphatikiza kuti mupange mapangidwewo.
2. Mukapanga chinthu cha SRAM file .sof, tsatirani izi kuti mupange mawonekedwe a hardware example pa chipangizo cha Intel Agilex:
   a. Pa Zida menyu, dinani Programmer.
   b. Mu Programmer, dinani Hardware Setup.
   c. Sankhani chipangizo chokonzera.
   d. Sankhani ndi kuwonjezera bolodi la Intel Agilex ku gawo lanu la Intel Quartus Prime Pro Edition.
   e. Onetsetsani kuti Mode yakhazikitsidwa ku JTAG.
   f. Sankhani chipangizo cha Intel Agilex ndikudina Add Chipangizo. Pulogalamuyi ikuwonetsa
   Chithunzi cha block cha kulumikizana pakati pa zida pa bolodi lanu.
   g. Mu mzere ndi .sof yanu, fufuzani bokosi la .sof.
   h. Chongani bokosi mu gawo la Pulogalamu/Sinthani.
   ndi. Dinani Yambani.

1.6. Kuyesa F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
Mukapanga F-tile 25G Ethernet Intel FPGA IP core design example ndikuikonza pa chipangizo chanu cha Intel Agilex, mutha kugwiritsa ntchito System Console kukonza maziko a IP.
Kuti muyatse System Console ndikuyesa kapangidwe ka Hardware example, tsatirani izi:

1. Mu pulogalamu ya Intel Quartus Prime Pro Edition, sankhani Zida ➤ System
   Zida Zowongolera ➤ System Console kuti mutsegule cholumikizira.
2. Pagawo la Tcl Console, lembani cd hwtest kuti musinthe chikwatu kukhala / hardware_test_design/hwtest.
3. Lembani source main.tcl kuti mutsegule kulumikiza ku JTAG mbuye.

Tsatirani njira yoyesera mu gawo la Hardware Testing ex designample ndikuwona zotsatira zoyesa mu System Console.

F-tile 25G Ethernet Design Example kwa Intel Agilex Devices

Mapangidwe a F-tile 25G Ethernet example akuwonetsa yankho la Ethernet la zida za Intel Agilex pogwiritsa ntchito 25G Ethernet Intel FPGA IP core.
Pangani ex designample ku Eksample Design tabu ya 25G Ethernet Intel FPGA IP parameter editor. Mukhozanso kusankha kupanga mapangidwe ndi kapena popanda
mawonekedwe a Reed-Solomon Forward Error Correction (RS-FEC).
2.1. Mbali

• Imathandizira njira imodzi ya Ethernet yomwe ikugwira ntchito pa 25G.
• Amapanga example ndi mawonekedwe a RS-FEC.
• Amapereka testbench ndi kayeseleledwe script.
• Imakhazikitsa F-Tile Reference ndi System PLL Mawotchi Intel FPGA IP kutengera kasinthidwe ka IP.

2.2. Zofunikira pa Hardware ndi Mapulogalamu
Intel imagwiritsa ntchito zida ndi mapulogalamu otsatirawa kuyesa kapangidwe kakaleamplembani mu Linux system:

• Pulogalamu ya Intel Quartus Prime Pro Edition.
• Siemens* EDA QuestaSim, Synopsys* VCS, ndi Cadence Xcelium simulator.
• Intel Agilex I-series Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) yoyesa zida.

2.3. Kufotokozera Kwantchito
Mapangidwe a F-tile 25G Ethernet example imakhala ndi mtundu wa MAC+PCS+PMA core. Zithunzi zotsatirazi zikuwonetsa mapangidwe apangidwe ndi zizindikiro zapamwamba za MAC + PCS + PMA core kusiyana mu F-tile 25G Ethernet design ex.ample.
Chithunzi 5. Chojambula Chotchinga-F-tile 25G Ethernet Design Example (MAC+PCS+PMA Core Variant)

2.3.1. Zida Zopangira
Table 4. Zida Zopangira

Chigawo	Kufotokozera
F-tile 25G Ethernet Intel FPGA IP	Muli ndi MAC, PCS, ndi Transceiver PHY, ndi masinthidwe awa: • Core VariantMtundu: MAC+PCS+PMA • Yambitsani kuyendetsa bwino: Zosankha • Yambitsani kupanga zolakwika za ulalo: Zosankha • Yambitsani kupita patsogolo: Zosankha • Yambitsani kusonkhanitsa ziwerengero: Zosankha • Yambitsani zowerengera za MAC: Zosankha • Malipiro a wotchi pafupipafupi:156.25 Za kapangidwe ka example ndi mawonekedwe a RS-FEC, gawo lowonjezera lotsatirali limakonzedwa: • Yambitsani RS-FEC: Zosankha
F-Tile Reference ndi System PLL Mawotchi a Intel FPGA IP	F-Tile Reference ndi System PLL Mawotchi a Intel FPGA IP parameter editor agwirizane ndi zofunikira za F-tile 25G Ethernet Intel FPGA IP. Ngati mupanga mapangidwe a exampndi kugwiritsa Pangani Exampndi Design batani mu mkonzi wa parameter ya IP, IP imangoyambitsa zokha. Ngati mupanga zojambula zanu zakaleample, muyenera kukhazikitsa pamanja IP iyi ndikulumikiza madoko onse a I/O. Kuti mudziwe zambiri za IP iyi, onani F-Tile Architecture ndi PMA ndi FEC Direct PHY IP User Guide.
Malingaliro a kasitomala	Muli: • Jenereta yamagalimoto, yomwe imapanga mapaketi ophulika ku 25G Ethernet Intel FPGA IP pachimake potumiza. • Traffic monitor, yomwe imayang'anira mapaketi ophulika omwe akuchokera ku 25G Ethernet Intel FPGA IP core.
Source ndi Probe	Magwero ndi ma siginecha a kafukufuku, kuphatikiza chizindikiro cholowetsamo chokhazikitsira, chomwe mungagwiritse ntchito kuthetsa vuto.

Zambiri Zogwirizana
F-Tile Architecture ndi PMA ndi FEC Direct PHY IP User Guide

Kuyerekezera

Testbench imatumiza magalimoto kupyola IP core, imagwiritsa ntchito mbali yotumizira ndikulandira mbali ya IP core.
2.4.1. Testbench
Chithunzi 6. Chojambula chotchinga cha F-tile 25G Ethernet Intel FPGA IP Design Exampndi Simulation Testbench

Table 5. Zida za Testbench

Chigawo	Kufotokozera
Chipangizo chikuyesedwa (DUT)	25G Ethernet Intel FPGA IP pachimake.
Ethernet Packet Generator ndi Packet Monitor	• Jenereta ya paketi imapanga mafelemu ndikutumiza ku DUT. • Packet Monitor imayang'anira TX ndi RX datapaths ndikuwonetsa mafelemu mu simulator console.
F-Tile Reference ndi System PLL Mawotchi a Intel FPGA IP	Amapanga mawotchi a transceiver ndi system PLL.

2.4.2. Simulation Design Exampndi Components
Table 6. F-tile 25G Ethernet Design Exampndi Testbench File Kufotokozera

File Dzina	Kufotokozera
Testbench ndi Simulation Files
basic_avl_tb_top.v	Testbench yapamwamba kwambiri file. Testbench imayambitsa DUT, imapanga kasinthidwe ka kukumbukira kwa Avalon® pamagulu apangidwe ndi malingaliro a kasitomala, ndipo imatumiza ndi kulandira paketi kupita kapena kuchokera ku 25G Ethernet Intel FPGA IP.
Zolemba za Testbench
anapitiriza…

File Dzina	Kufotokozera
run_vsim.do	The ModelSim script kuyendetsa testbench.
run_vcs.sh	Synopsys VCS script yoyendetsa testbench.
run_xcelium.sh	The Cadence Xcelium script kuti ayendetse testbench.

2.4.3. Mlandu Woyesera
Mayeso oyeserera amachita izi:

1. Instatiates F-tile 25G Ethernet Intel FPGA IP ndi F-Tile Reference ndi System PLL Mawotchi Intel FPGA IP.
2. Imadikirira wotchi ya RX ndi chizindikiro cha PHY kuti ikhazikike.
3. Imasindikiza mawonekedwe a PHY.
4. Amatumiza ndi kulandira 10 zovomerezeka.
5. Imasanthula zotsatira. Ma testbench opambana akuwonetsa "Testbench yatha".

Zotsatirazi sample output ikuwonetsa kuyesa koyeserera kopambana:

Kuphatikiza

Tsatirani ndondomekoyi pakukonza ndi Kukonza Example in Hardware kuti apange ndikusintha kapangidwe kakaleample mu hardware yosankhidwa.
Mutha kuyerekezera kagwiritsidwe ntchito kazinthu ndi Fmax pogwiritsa ntchito kapangidwe kake kopanga kaleample. Mutha kupanga mapangidwe anu pogwiritsa ntchito lamulo la Start Compilation pa
Kukonza menyu mu pulogalamu ya Intel Quartus Prime Pro Edition. Kupanga kopambana kumapanga chidule cha lipoti lokonzekera.
Kuti mumve zambiri, onani Kupanga Kupanga mu Intel Quartus Prime Pro Edition User Guide.
Zambiri Zogwirizana

• Kupanga ndi Kukonza Design Example mu Hardware patsamba 7
• Kupanga Kupanga Mu Intel Quartus Prime Pro Edition User Guide

2.6. Kuyesa kwa Hardware
Mu kapangidwe ka hardware example, mutha kukonza IP pachimake mkati mwa serial loopback mode ndikupanga kuchuluka kwa magalimoto kumbali yotumizira yomwe imabwerera kumbuyo kunjira yolandila.
Tsatirani ndondomeko yomwe ili pa ulalo wokhudzana ndi zomwe zaperekedwa kuti muyese kapangidwe kakaleample mu hardware yosankhidwa.
Zambiri Zogwirizana
Kuyesa F-tile 25G Ethernet Intel FPGA IP Hardware Design Example patsamba 8
2.6.1. Njira Zoyesera
Tsatirani izi kuti muyese zojambula zakaleampndi hardware:

1. Musanayendetse kuyesa kwa hardware kwa kapangidwe kakale kamenekaampLero, muyenera kukhazikitsanso dongosolo:
   a. Dinani Zida ➤ Chida cha In-System Source & Probes Editor kuti mukhale ndi Chitsimikizo chosasinthika ndi Probe GUI.
   b. Sinthani chizindikiro chokhazikitsanso dongosolo (Source[3:0]) kuchokera ku 7 mpaka 8 kuti mugwiritse ntchito zobwezeretsanso ndikubwezeretsanso chizindikiro chobwezeretsanso ku 7 kuti mutulutse dongosololo kuchokera pakukonzanso.
   c. Yang'anirani ma sign a Probe ndikuwonetsetsa kuti malowo ndi ovomerezeka.
2. Mu system console, yendani ku hwtest foda ndikuyendetsa lamulo: source main.tcl kuti musankhe JTAG mbuye. Mwachikhazikitso, woyamba JTAG master pa JTAG unyolo wasankhidwa. Kusankha JTAG master pazida za Intel Agilex, yendetsani lamulo ili: set_jtag <number of appropriate JTAG bwana>. Eksampizi: jtag 1.
3. Pangani malamulo otsatirawa mu system console kuti muyambe kuyesa kwa serial loopback:

Table 7. Command Parameters

Parameter	Kufotokozera	Exampndi Kugwiritsa
chkphy_status	Imawonetsa ma frequency a wotchi ndi mawonekedwe a PHY loko.	% chkphy_status 0 # Onani momwe ulalo uliri 0
chkmac_stats	Imawonetsa mitengo muzowerengera za MAC.	% chkmac_stats 0 # Yang'anani ziwerengero za mac za ulalo 0
clear_all_stats	Imachotsa zowerengera za IP core.	% clear_all_stats 0 # Imachotsa zowerengera za ulalo 0
chiyambi_gen	Imayamba jenereta ya paketi.	% start_gen 0 # Yambani kupanga paketi pa ulalo 0
stop_gen	Kuyimitsa paketi jenereta.	% stop_gen 0 # Imani kupanga mapaketi pa ulalo 0
loop_pa	Imayatsa loopback yamkati.	% loop_on 0 # Yatsani loopback yamkati pa ulalo 0
loop_off	Izimitsa loopback yamkati.	% loop_off 0 # Zimitsani kuzungulira kwamkati pa ulalo 0
reg_werengani	Imabweza mtengo wa kaundula wa IP pa .	% reg_read 0x402 # Werengani IP CSR registry pa adilesi 402 ya ulalo 0
reg_write	Amalemba kupita ku registry ya IP pa adilesi .	% reg_write 0x401 0x1 # Lembani 0x1 ku IP CSR zolembera zolembera pa adilesi 401 ya ulalo 0

a. Lembani loop_on kuti muyatse njira yamkati ya serial loopback.
b. Lembani chkphy_status kuti muwone momwe PHY ilili. Makhalidwe a TXCLK, RXCLK, ndi RX akuyenera kukhala ndi mfundo zomwe zili pansipa pa ulalo wokhazikika:

c. Lembani clear_all_stats kuchotsa ziwerengero za TX ndi RX.
d. Lembani start_gen kuyamba kupanga paketi.
e. Lembani stop_gen kuyimitsa kupanga paketi.
f. Lembani chkmac_stats kuti muwerenge ziwerengero za TX ndi RX. Onetsetsani kuti:
ndi. Mafelemu a paketi opatsirana amafanana ndi mafelemu a paketi omwe alandilidwa.
ii. Palibe mafelemu olakwika omwe amalandiridwa.
g. Lembani loop_off kuzimitsa serial loopback yamkati.
Chithunzi 7. Sample Test Output-TX ndi RX Statistics Counters

Mbiri Yokonzanso Zolemba za F-tile 25G Ethernet FPGA IP Design Exampndi User Guide

Document Version	Intel Quartus Prime Version	Mtundu wa IP	Zosintha
2022.10.14	22.3	1.0.0	Kutulutsidwa koyamba.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
ISO
9001:2015
Olembetsedwa

Baibulo Lomasulira
Tumizani Ndemanga
ID: 750200
Mtundu: 2022.10.14

Zolemba / Zothandizira

Intel F-Tile 25G Efaneti FPGA IP Design Example [pdf] Buku Logwiritsa Ntchito F-Tile 25G Ethernet FPGA IP Design Example, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Design Exampndi, IP Design Exampndi, 750200

Maumboni

• Buku Logwiritsa Ntchito