DisplayPort Agilex F-Tile FPGA IP Design Example
Bukana ea Mosebelisi
E ntlafalitsoe bakeng sa Intel® Quartus® Prime Design Suite: 21.4
Phetolelo ea IP: 21.0.0

DisplayPort Intel FPGA IP Design Example Quick Start Guide

Moetso oa DisplayPort Intel® FPGA IP examples bakeng sa lisebelisoa tsa Intel Agilex™ F-tile li na le benche ea teko e etsisang le moralo oa hardware o tšehetsang ho bokella le ho hlahloba hardware.
DisplayPort Intel FPGA IP e fana ka moralo o latelang oa mohlalaamphanyane:

• DisplayPort SST parallel loopback ntle le mojule oa Pixel Clock Recovery (PCR) ka sekhahla se tsitsitseng

Ha o hlahisa ex designample, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware.
Hlokomela: Intel Quartus® Prime 21.4 software version e tšehetsa feela Preliminary Design Example bakeng sa sepheo sa Ketsiso, Kamano, Kopano, le tlhahlobo ea Nako. Ts'ebetso ea Hardware ha e ea netefatsoa ka botlalo.
Setšoantšo sa 1. Ntlafatso ea Stages

Lintlha Tse Amanang

• DisplayPort Intel FPGA IP User Guide
• Ho fallela ho Intel Quartus Prime Pro Edition

1.1. Sebopeho sa Directory
Setšoantšo sa 2. Sebopeho sa Directory

Lethathamo la 1. Moqapi Example Likarolo

Liphutheli	Files
rtl/core	dp_core.ip
	dp_rx.ip
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((Sebaka sa moaho sa DP PMA UX)
	dp_rx_data_fifo.ip
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((Sebaka sa moaho sa DP PMA UX)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Litlhoko tsa Hardware le Software
Intel e sebelisa lisebelisoa tse latelang le software ho leka moralo oa exampLe:
Lisebelisoa

• Intel Agilex I-Series Development Kit

Software

• Intel Quartus Prime
• Synopsy* VCL Simulator

1.3. Ho Hlahisa Moralo
Sebelisa DisplayPort Intel FPGA IP parameter mohlophisi ho Intel Quartus Prime software ho hlahisa moralo oa example.
Setšoantšo sa 3. Ho Hlahisa Phallo ea Moqapi

1. Khetha Tools ➤ IP Catalog, ebe u khetha Intel Agilex F-tile e le lelapa la sesebelisoa se shebiloeng.
   Tlhokomeliso: Moqapi oa mohlalaample e tšehetsa feela lisebelisoa tsa Intel Agilex F-tile.
2. Ho IP Catalog, fumana le ho penya habeli DisplayPort Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variation.
3. Hlalosa lebitso la boemo bo holimo bakeng sa IP ea hau ea tloaelo. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip.
4. U ka khetha sesebelisoa se ikhethileng sa Intel Agilex F-tile tšimong ea Sesebelisoa, kapa u boloke khetho ea sesebelisoa sa Intel Quartus Prime sa kamehla.
5. Tobetsa OK. Mohlophisi oa parameter oa hlaha.
6. Lokisa liparamente tse lakatsehang tsa TX le RX ka bobeli
7. Ka Moqapi Exampho tab, khetha DisplayPort SST Parallel Loopback Ntle le PCR.
8. Khetha Simulation ho hlahisa testbench, 'me u khethe Synthesis ho hlahisa moralo oa hardware example. U tlameha ho khetha bonyane e 'ngoe ea likhetho tsena ho hlahisa sebopeho sa example files. Haeba u khetha ka bobeli, nako ea tlhahiso e telele.
9. Tobetsa Hlahisa Example Design.

1.4. Ho Etsisa Moralo
Moetso oa DisplayPort Intel FPGA IP example testbench e etsisa moralo oa serial loopback ho tloha mohlala oa TX ho ea ho mohlala oa RX. Mojule oa jenereithara oa ka hare oa video o khanna mohlala oa DisplayPort TX mme tlhahiso ea video ea RX e hokahana le licheke tsa CRC ho testbench.
Setšoantšo sa 4. Phallo ea Ketsiso ea Moralo

1. Eya ho foldara ea simulator ea Synopsy ebe u khetha VCS.
2. Etsa mongolo oa ketsiso.
   Mohloli vcs_sim.sh
3. Script e etsa Quartus TLG, e bokella le ho tsamaisa testbench ho simulator.
4. Sekaseka sephetho.
   Papiso e atlehileng e qetella ka papiso ea Mohloli le Sink SRC.

1.5. Ho Kopanya le ho Etsisa Moralo
Setšoantšo sa 5. Ho bokella le ho etsisa Moralo

Ho bokella le ho etsa tlhahlobo ea pontšo ho hardware example design, latela mehato ena:

1. Netefatsa hore hardware example tlhahiso ea moralo e felile.
2. Qala software ea Intel Quartus Prime Pro Edition 'me u bule /quartus/agi_dp_demo.qpf.
3. Tobetsa Ho sebetsa ➤ Qala ho Kopanya.
4. Ema ho fihlela Compilation e phethoa.

Hlokomela: Moqapi example ha e netefatse ka mokhoa o sebetsang Moqapi oa Pele Example ho hardware tokollong ena ea Quartus.
Lintlha Tse Amanang
Intel Agilex I-Series FPGA Development Kit User Guide

1.6. DisplayPort Intel FPGA IP Design Example Li-Parameters
Letlapa la 2. DisplayPort Intel FPGA IP Design Example Parameters bakeng sa Sesebelisoa sa Intel Agilex F-tile

Paramethara	Boleng	Tlhaloso
Moqapi o Fumanehang Example
Kgetha Moralo	• Ha ho letho • DisplayPort SST Parallel Loopback ntle le PCR	Khetha mohlala oa moraloample tla hlahisoa. • Ha ho letho: Ha ho na mohlala oa moraloample e fumaneha bakeng sa khetho ea hajoale ea parametha • DisplayPort SST Parallel Loopback ntle le PCR: Moqapi ona example e bonts'a loopback e ts'oanang ho tloha sinking ea DisplayPort ho ea mohloling oa DisplayPort ntle le mojule oa Pixel Clock Recovery (PCR) ha o bulela paramethara ea Numella Video Input Image Port.
Moqapi Example Files
Ketsiso	Bulehile, Tima	Bulela khetho ena ho etsa se hlokahalang files bakeng sa ketsiso testbench.
Synthesis	Bulehile, Tima	Bulela khetho ena ho etsa se hlokahalang files bakeng sa pokello ea Intel Quartus Prime le moralo oa lisebelisoa.
HDL Format e entsoeng
Hlahisa File Sebopeho	Verilog, VHDL	Khetha mofuta oo u o ratang oa HDL bakeng sa sebopeho se hlahisitsoeng sa example filebeha. Hlokomela: Khetho ena e khetha feela sebopeho sa IP ea boemo bo holimo e hlahisitsoeng files. Tse ling kaofela files (mohlample testbenches le boemo bo holimo files bakeng sa pontšo ea hardware) li ka sebopeho sa Verilog HDL.
Setsi sa Nts'etsopele se reriloeng
Khetha Boto	• Ha ho Kit ea Ntlafatso • Intel Agilex I-Series Ntlafatso Kit	Khetha boto bakeng sa moralo o lebisitsoeng oa mohlalaample. • No Development Kit: Khetho ena ha e kenyeletse likarolo tsohle tsa hardware bakeng sa ex designample. IP core e beha likabelo tsohle tsa pini ho li-virtual pin. • Intel Agilex I-Series FPGA Development Kit: Khetho ena e ikhethela sesebelisoa se shebiloeng sa morero ho tsamaisana le sesebelisoa ho kit ena ea ntlafatso. U ka fetola sesebelisoa se shebiloeng u sebelisa parameter ea Change Target Device haeba boto ea hau e na le phapang e fapaneng ea lisebelisoa. IP core e beha likabelo tsohle tsa phini ho latela lisebelisoa tsa nts'etsopele. Hlokomela: Moqapi oa Pele ExampLe ha e ea netefatsoa ka lisebelisoa tsa Hardware tokollong ena ea Quartus. • Custom Development Kit: Khetho ena e lumella moqapi exampe tla lekoa ho lisebelisoa tsa nts'etsopele ea motho oa boraro ka Intel FPGA. Ho ka 'na ha hlokahala hore u behe likabelo tsa phini u le mong.
	Sesebediswa se reriloeng
Fetola Sesebediswa se Lebeletsweng	Bulehile, Tima	Bulela khetho ena 'me u khethe mofuta o ratoang oa sesebelisoa bakeng sa lisebelisoa tsa ntlafatso.

Parallel Loopback Design Examples

Moetso oa DisplayPort Intel FPGA IP exampre bonts'a loopback e ts'oanang ho tloha mohlaleng oa DisplayPort RX ho isa ho DisplayPort TX ntle le mojule oa Pixel Clock Recovery (PCR) ka sekhahla se tsitsitseng.
Letlapa la 3. DisplayPort Intel FPGA IP Design Example bakeng sa Sesebelisoa sa Intel Agilex F-tile

Moqapi Example	Khethollo	Sekhahla sa Lintlha	Mokhoa oa Channel	Mofuta oa Loopback
DisplayPort SST parallel loopback ntle le PCR	DisplayPort SST	HBR3	Simplex	E tšoana ntle le PCR

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Features
Moetso oa SST o ts'oanang oa loopback exampre bonts'a phetiso ea video e le 'ngoe ho tloha siling ea DisplayPort ho ea mohloling oa DisplayPort ntle le Pixel Clock Recovery (PCR) ka sekhahla se tsitsitseng.

Setšoantšo sa 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback ntle le PCR

• Mofuteng ona, paramethara ea mohloli oa DisplayPort, TX_SUPPORT_IM_ENABLE, e buletsoe 'me ho sebelisoa sebopeho sa setšoantšo sa video.
• Sekoahelo sa DisplayPort se amohela video le kapa audio audio ho tsoa mohloling oa video o kantle joalo ka GPU ebe e e hlophisa hore e be sebopeho sa video se ts'oanang.
• Tlhahiso ea video e tebang ea DisplayPort e khanna ka kotloloho sebopeho sa video sa mohloli oa DisplayPort ebe e kenyelletsa sehokelo sa mantlha sa DisplayPort pele e fetisetsa ho sebali.
• IOPLL e khanna sinki ea DisplayPort le lioache tsa video tsa mohloli ka lebelo le tsitsitseng.
• Haeba sinki ea DisplayPort le mohloli oa MAX_LINK_RATE parameter e lokiselitsoe ho ba HBR3 'me PIXELS_PER_CLOCK e hlophisitsoe ho ba Quad, oache ea video e sebetsa ho 300 MHz ho tšehetsa 8Kp30 reiti (1188/4 = 297 MHz).

2.2. Sekema sa ho Tlisa
Morero oa oache o bonts'a libaka tsa oache ho DisplayPort Intel FPGA IP moralo example.
Setšoantšo sa 7. Intel Agilex F-tile DisplayPort Transceiver clocking scheme

Letlapa la 4. Lipontšo tsa Scheme ea ho Tsupa

Setšoantšo sa oache	Tlhaloso
Setšoantšo sa SysPLL	F-tile System PLL e ka ba maqhubu leha e le afe a oache a aroloang ke System PLL bakeng sa maqhubu ao a tsoang. Moqaping ona example, system_pll_clk_link le rx/tx refclk_link e arolelana refclk e tšoanang ea SysPLL e leng 150Mhz. E tlameha ho ba oache ea mahala e hokahantsoeng ho tloha pineng ea oache ea transceiver e inehetseng ho koung ea oache ea Reference le System PLL Clocks IP, pele e hokahanya boema-kepe bo lumellanang le DisplayPort Phy Top.
system_pll_clk_link	Nako e fokolang ea tlhahiso ea System PLL ho tšehetsa sekhahla sa DisplayPort kaofela ke 320Mhz. Moqapi ona example sebelisa 900 Mhz (e phahameng ka ho fetisisa) maqhubu a tlhahiso e le hore SysPLL refclk e ka arolelanoa le rx/tx refclk_link e leng 150 Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	Rx CDR le Tx PLL Link refclk e tsitsitseng ho 150 Mhz ho tšehetsa sekhahla sa data sa DisplayPort kaofela.
rx_ls_clkout/tx Ke clkout	DisplayPort Link Speed ​​​​Clock ho tšupa konokono ea DisplayPort IP. Maqhubu a lekanang le Sekhahla sa Lintlha arola ka bophara ba data bo bapileng. ExampLe: Hangata = sekhahla sa data / bophara ba data = 8.1G (HBR3) / 40bits = 202.5 Mhz

2.3. Ketsiso Testbench
Testbench ea simulation e etsisa DisplayPort TX serial loopback ho RX.
Setšoantšo sa 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram

Letlapa la 5. Likarolo tsa Testbench

Karolo	Tlhaloso
Jenereithara ea Paterone ea Video	Jenereithara ena e hlahisa lipaterone tsa mebala eo u ka e hlophisang. U ka etsa parameterize ea nako ea sebopeho sa video.
Taolo ea Testbench	Sebaka sena se laola tatellano ea tlhahlobo ea papiso mme e hlahisa matšoao a hlokahalang a ts'usumetso ho mantlha ea TX. Setsi sa taolo ea testbench se boetse se bala boleng ba CRC ho tloha mohloling le ho teba ho etsa lipapiso.
RX Link Speed ​​Clock Frequency Checker	Sehlahlobi sena se netefatsa hore na transceiver ea RX e fumaneng nako ea oache e lumellana le sekhahla sa data se lakatsehang.
TX Link Speed ​​Clock Frequency Checker	Sehlahlobi sena se netefatsa hore na transceiver ea TX e fumaneng nako ea oache e lumellana le sekhahla sa data se lakatsehang.

The simulation testbench e etsa linetefatso tse latelang:
Letlapa la 6. Litefiso tsa Testbench

Litekanyetso tsa Teko	Netefatso
• Khokahano ea Koetliso ho Sekhahla sa Lintlha HBR3 • Bala direjista tsa DPCD ho bona hore na DP Status e beha le ho lekanya bobedi maqhubu a TX le RX Link Speed.	E kopanya Frequency Checker ho lekanya tlhahiso ea maqhubu ea sebatli sa Link Speed ​​ho tsoa ho transceiver ea TX le RX.
• Matha paterone ea video ho tloha TX ho ea ho RX. • Netefatsa CRC bakeng sa mohloli le sink ho hlahloba hore na lia lumellana	• E hokahanya jenereithara ea mohlala oa video ho Mohloli oa DisplayPort ho hlahisa paterone ea video. • Taolo ea Testbench e latelang e bala ka bobeli Source le Sink CRC ho tsoa ho DPTX le DPRX rejisetara mme e bapisa ho netefatsa hore boleng ba CRC ka bobeli boa tšoana. Hlokomela: Ho etsa bonnete ba hore CRC e baloa, o tlameha ho nolofalletsa paramethara ea tlhahlobo ea tšehetso ea CTS.

Nalane ea Phetoho ea Tokomane bakeng sa DisplayPort Intel

Agilex F-tile FPGA IP Design Example Bukana ea Mosebelisi

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
2021.12.13	21.4	21.0.0	Tokollo ea pele.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.
*Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO 9001: 2015 E ngolisitsoe

Online Version
Romella Maikutlo
UG-20347
ID: 709308
Mofuta: 2021.12.13

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Intel DisplayPort Agilex F-Tile FPGA IP Design Example [pdf] Bukana ea Mosebelisi DisplayPort Agilex F-Tile FPGA IP Design Example, DisplayPort Agilex, F-Tile FPGA IP Design Example, F-Tile FPGA IP Design, FPGA IP Design Example, IP Design Example, IP Design, UG-20347, 709308

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