DisplayPort Agilex F-Tile FPGA IP Design Example
Jagorar Mai Amfani
An sabunta don Intel® Quartus® Prime Design Suite: 21.4
Shafin IP: 21.0.0

DisplayPort Intel FPGA IP Design ExampJagorar Farawa Mai sauri

DisplayPort Intel® FPGA IP ƙiraamples don na'urorin F-tile na Intel Agilex™ suna da simintin gwajin gwaji da ƙirar kayan masarufi waɗanda ke goyan bayan haɗawa da gwajin kayan aiki.
DisplayPort Intel FPGA IP yana ba da ƙira mai zuwaampda:

• DisplayPort SST daidaitaccen madauki ba tare da ƙirar Pixel Clock farfadowa da na'ura ba (PCR) a daidaitaccen ƙimar

Lokacin da kuka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik fileya zama dole don kwaikwaya, tarawa, da gwada ƙira a cikin kayan masarufi.
Lura: Sigar software ta Intel Quartus® Prime 21.4 tana goyan bayan Zane na Farko Example don Simulation, Synthesis, Compilation, and Timeing analysis purpose. Ba a tabbatar da cikakken aikin hardware ba.
Hoto 1. Ci gaban Stages

Bayanai masu alaƙa

• DisplayPort Intel FPGA IP Jagorar Mai amfani
• Hijira zuwa Intel Quartus Prime Pro Edition

1.1. Tsarin Jagora
Hoto 2. Tsarin Jagora

Tebur 1. Zane ExampAbubuwan da aka gyara

Jakunkuna	Files
rtl/core	dp_core.ip
	dp_rx.ip
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX block)
	dp_rx_data_fifo.ip
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX block)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Bukatun Hardware da Software
Intel yana amfani da kayan masarufi da software masu zuwa don gwada ƙirar ƙiraampda:
Hardware

• Intel Agilex I-Series Development Kit

Software

• Intel Quartus Prime
• Synopsys* VCL Simulator

1.3. Samar da Zane
Yi amfani da editan madaidaicin IP na DisplayPort Intel FPGA a cikin software na Intel Quartus Prime don samar da ƙirar ƙiraample.
Hoto 3. Samar da Tsarin Zane

1. Zaɓi Kayan aiki ➤ IP Catalog, kuma zaɓi Intel Agilex F-tile azaman dangin na'urar da aka yi niyya.
   Lura: The zane exampLe kawai yana goyan bayan na'urorin F-tile na Intel Agilex.
2. A cikin Catalog na IP, gano wuri kuma danna DisplayPort Intel FPGA IP sau biyu. Sabuwar taga Bambancin IP yana bayyana.
3. Ƙayyade sunan babban matakin don bambancin IP na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip.
4. Kuna iya zaɓar takamaiman na'urar tayal F-tile na Intel Agilex a cikin filin na'ura, ko kiyaye tsoffin zaɓin na'urar software ta Intel Quartus Prime.
5. Danna Ok. Editan siga ya bayyana.
6. Sanya sigogin da ake so don duka TX da RX
7. Akan Zane ExampDaga shafin, zaɓi DisplayPort SST Daidaitacce Loopback Ba tare da PCR ba.
8. Zaɓi Simulation don samar da benci na gwaji, kuma zaɓi Synthesis don samar da ƙirar kayan masarufiample. Dole ne ku zaɓi aƙalla ɗaya daga cikin waɗannan zaɓuɓɓukan don samar da ƙirar tsohuwarample files. Idan kun zaɓi duka biyun, lokacin tsara ya fi tsayi.
9. Danna Ƙirƙirar Exampda Design.

1.4. Simulating da Zane
DisplayPort Intel FPGA IP ƙira example testbench yana kwaikwayi ƙirar madauki na serial daga misalin TX zuwa misalin RX. Modulin janareta na bidiyo na ciki yana fitar da misalin DisplayPort TX kuma fitowar bidiyo ta RX ta haɗa zuwa masu duba CRC a cikin testbench.
Hoto 4. Zane Simulators

1. Jeka babban fayil ɗin Synopsys na'urar kwaikwayo kuma zaɓi VCS.
2. Gudanar da rubutun kwaikwayo.
   Tushen vcs_sim.sh
3. Rubutun yana yin Quartus TLG, yana tattarawa kuma yana gudanar da gwajin benci a cikin na'urar kwaikwayo.
4. Yi nazarin sakamakon.
   Nasarar kwaikwayo ta ƙare tare da kwatanta Source da Sink SRC.

1.5. Haɗawa da Kwatancen Zane
Hoto 5. Haɗawa da Kwaikwaya Zane

Don haɗawa da gudanar da gwajin gwaji akan hardware exampdon tsarawa, bi waɗannan matakan:

1. Tabbatar da hardware example zane tsara ya cika.
2. Kaddamar da Intel Quartus Prime Pro Edition software kuma buɗe /quartus/agi_dp_demo.qpf.
3. Danna Processing ➤ Fara Tari.
4. Jira har sai an kammala Tarin.

Lura: Zane example baya tabbatar da aikin Farko ExampLe on hardware a cikin wannan Quartus saki.
Bayanai masu alaƙa
Intel Agilex I-Series FPGA Jagorar Mai amfani Kit na Ci gaban

1.6. DisplayPort Intel FPGA IP Design Exampda Parameters
Tebur 2. DisplayPort Intel FPGA IP Design ExampLe Parameters don Intel Agilex F-tile Device

Siga	Daraja	Bayani
Akwai Zane Example
Zaɓi Zane	• Babu Layi ɗaya na DisplayPort SST Dubawa ba tare da PCR ba	Zaɓi zane exampda za a haifar. • Babu: Babu ƙira example yana samuwa don zaɓin siga na yanzu • DisplayPort SST Parallel Loopback ba tare da PCR ba: Wannan ƙirar misaliample yana nuna madaidaicin madaidaici daga nutsewar DisplayPort zuwa tushen DisplayPort ba tare da ƙirar Pixel Clock farfadowa da na'ura ba (PCR) lokacin da kuka kunna siginar tashar Hoton shigar da Bidiyo.
Zane Example Files
kwaikwayo	Kunnawa, Kashe	Kunna wannan zaɓi don samar da abin da ake bukata files don simulation testbench.
Magana	Kunnawa, Kashe	Kunna wannan zaɓi don samar da abin da ake bukata files don Haɗin Intel Quartus Prime da ƙirar kayan masarufi.
Samar da Tsarin HDL
Ƙirƙira File Tsarin	Verilog, VHDL	Zaɓi tsarin HDL da kuka fi so don ƙirar ƙiraample filesaita. Lura: Wannan zaɓin yana ƙayyadaddun tsari ne kawai don babban matakin IP da aka samar files. Duk sauran files (misaliample testbenches da babban matakin files don zanga-zangar hardware) suna cikin tsarin Verilog HDL.
Kit ɗin Ci gaban Target
Zaɓi Board	• Babu Kayan Ci gaba • Intel Agilex I-Series Kit ɗin Ci gaba	Zaɓi allon don ƙirar da aka yi niyya example. • Babu Kit ɗin Haɓakawa: Wannan zaɓin ya keɓance duk abubuwan kayan masarufi don ƙirar ƙiraample. Babban IP ɗin yana saita duk ayyukan fil zuwa fil ɗin kama-da-wane. • Intel Agilex I-Series FPGA Development Kit: Wannan zaɓi yana zaɓar na'urar da aka yi niyya ta atomatik don dacewa da na'urar akan wannan kayan haɓakawa. Kuna iya canza na'urar da aka yi niyya ta amfani da ma'aunin Canja Na'urar Target idan bita na allo yana da bambancin na'urar daban. Tushen IP yana saita duk ayyukan fil bisa ga kayan haɓakawa. Lura: Zane na farko Example ba a tabbatar da aikin ba akan kayan masarufi a cikin wannan sakin Quartus. • Kit ɗin Haɓakawa na Musamman: Wannan zaɓi yana ba da damar ƙira exampza a gwada shi akan kayan haɓaka na ɓangare na uku tare da Intel FPGA. Kuna iya buƙatar saita ayyukan fil da kanku.
	Na'urar Target
Canja Na'urar Target	Kunnawa, Kashe	Kunna wannan zaɓi kuma zaɓi bambance-bambancen na'urar da aka fi so don kayan haɓakawa.

Daidaici Loopback Design Examples

DisplayPort Intel FPGA IP ƙira exampmu nuna madaidaicin madaidaici daga misalin DisplayPort RX zuwa misalin DisplayPort TX ba tare da tsarin Pixel Clock farfadowa da na'ura ba (PCR) a matsakaici.
Tebur 3. DisplayPort Intel FPGA IP Design Exampdon Intel Agilex F-tile Device

Zane Example	Nadi	Adadin Bayanai	Yanayin Channel	Nau'in Loopback
DisplayPort SST layi daya madauki ba tare da PCR ba	DisplayPort SST	HBR3	Simplex	Daidaitacce ba tare da PCR ba

2.1. Intel Agilex F-tile DisplayPort SST Daidaitacce Mahimman Bayanan Tsara
The SST layi daya loopback zane exampdon nuna watsa rafin bidiyo guda ɗaya daga nutsewar DisplayPort zuwa tushen DisplayPort ba tare da farfadowar Agogon Pixel ba (PCR) a tsaye.

Hoto 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback ba tare da PCR ba

• A cikin wannan bambance-bambancen, ana kunna ma'aunin tushen DisplayPort, TX_SUPPORT_IM_ENABLE, kuma ana amfani da mu'amalar hoton bidiyo.
• The DisplayPort nutse yana karɓar bidiyo da ko sauti mai gudana daga tushen bidiyo na waje kamar GPU kuma yana yanke shi zuwa yanayin mu'amalar bidiyo iri ɗaya.
• Fitowar bidiyo ta nutsewa ta DisplayPort kai tsaye tana tafiyar da ƙirar bidiyo ta tushen DisplayPort kuma tana ɓoyewa zuwa babban hanyar haɗin gwiwar DisplayPort kafin aikawa zuwa mai saka idanu.
• IOPLL tana tafiyar da ma'aunin nuninPort da agogon bidiyo mai tushe a mitoci masu tsayi.
• Idan DisplayPort nutse da ma'aunin MAX_LINK_RATE na tushe an saita su zuwa HBR3 kuma an saita PIXELS_PER_CLOCK zuwa Quad, agogon bidiyo yana gudana a 300 MHz don tallafawa ƙimar pixel 8Kp30 (1188/4 = 297 MHz).

2.2. Tsarin agogo
Tsarin agogo yana kwatanta wuraren agogo a cikin DisplayPort Intel FPGA IP ƙiraample.
Hoto 7. Intel Agilex F-tile DisplayPort Transceiver clocking makirci

Tebur 4. Siginonin Tsare-tsaren agogo

Agogo a cikin zane	Bayani
Rahoton da aka ƙayyade na SysPLL	F-tile System Agogon tunani na PLL wanda zai iya zama kowane mitar agogo wanda System PLL ke raba don wannan mitar fitarwa. A cikin wannan zane example, system_pll_clk_link da rx/tx refclk_link suna raba SysPLL refclk iri ɗaya wanda shine 150Mhz. Dole ne ya zama agogon gudu na kyauta wanda aka haɗa daga keɓaɓɓen madaidaicin agogon nuni zuwa tashar agogon shigarwa na Reference da System PLL Clocks IP, kafin haɗa tashar fitarwa mai dacewa zuwa DisplayPort Phy Top.
tsarin_pll_clk_link	Matsakaicin mitar fitarwa na System PLL don tallafawa duk ƙimar DisplayPort shine 320Mhz. Wannan zane exampLe yana amfani da mitar fitarwa 900 Mhz (mafi girma) don a iya raba SysPLL refclk tare da rx/tx refclk_link wanda shine 150 Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	Rx CDR da Tx PLL Link refclk wanda aka gyara zuwa 150Mhz don tallafawa duk ƙimar bayanan DisplayPort.
rx_ls_clkout/tx Yana da kullun	Agogo saurin Haɗin Haɗin kai zuwa agogo DisplayPort IP core. Mitar daidai yake da Raba ƙimar Bayanai ta hanyar faɗin bayanan layi ɗaya. Exampda: Frequency = ƙimar bayanai/ faɗin bayanai = 8.1G (HBR3) / 40bits = 202.5Mhz

2.3. Simulators Testbench
Gwajin simintin simintin yana simintin siginar DisplayPort TX zuwa RX.
Hoto 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block zane

Tebur 5. Abubuwan Gwajin Testbench

Bangaren	Bayani
Bidiyo Tsarin Generator	Wannan janareta yana samar da alamun mashaya launi waɗanda zaku iya saita su. Za ka iya parameterize da video format lokaci.
Gudanarwar Testbench	Wannan toshe yana sarrafa jerin gwajin simulation kuma yana haifar da sigina masu mahimmanci ga ainihin TX. Katangar sarrafa gwajin gwaji kuma tana karanta ƙimar CRC daga tushe da nutse don yin kwatance.
RX Link Speed ​​​​Clock Checker	Wannan mai duba yana tabbatar da idan mai karɓar RX ya dawo da mitar agogo yayi daidai da ƙimar bayanan da ake so.
TX Link Speed ​​​​Clock Checker	Wannan mai duba yana tabbatar da idan mai karɓar TX da aka dawo da mitar agogo yayi daidai da ƙimar bayanan da ake so.

The simulation testbench yana yin waɗannan tabbaci masu zuwa:
Tebur 6. Tabbatar da Testbench

Ma'aunin Gwaji	Tabbatarwa
• Koyarwar haɗin kai a ƙimar bayanai HBR3 • Karanta rajistar DPCD don bincika idan Matsayin DP ya saita kuma yana auna mitar saurin haɗin TX da RX.	Yana Haɗa Mai duba Mitar don auna fitowar mitar agogon Haɗin kai daga TX da RX transceiver.
• Gudanar da tsarin bidiyo daga TX zuwa RX. • Tabbatar da CRC don duka tushe da nutsewa don bincika idan sun dace	• Haɗa janareta ƙirar bidiyo zuwa Tushen DisplayPort don samar da tsarin bidiyo. • Ikon Testbench na gaba yana karanta duka Source da Sink CRC daga rajistar DPTX da DPRX kuma suna kwatanta don tabbatar da ƙimar CRC duka iri ɗaya ne. Lura: Don tabbatar da an ƙididdige CRC, dole ne ku kunna madaidaicin gwajin CTS na goyan baya.

Tarihin Bita na Takardu don DisplayPort Intel

Agilex F-tile FPGA IP Design ExampJagorar Mai Amfani

Sigar Takardu	Intel Quartus Prime Version	Sigar IP	Canje-canje
2021.12.13	21.4	21.0.0	Sakin farko.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
ISO 9001: 2015 Rajista

Online Version
Aika da martani
Saukewa: UG-20347
ID: 709308
Siga: 2021.12.13

Takardu / Albarkatu

intel DisplayPort Agilex F-Tile FPGA IP Design Example [pdf] Jagorar mai amfani DisplayPort Agilex F-Tile FPGA IP Design Example, DisplayPort Agilex, F-Tile FPGA IP Design Example, F-Tile FPGA IP Design, FPGA IP Design Example, IP Design Example, IP Design, UG-20347, 709308

Magana

• Manual mai amfani