MICROCHIP Xilinx Spartan 6 Example Phetoho
Mofani ea ka Sehloohong oa Litharollo tsa Taolo e Kenyellelitsoeng e Bohlale, e Hokahaneng le e Sireletsehileng
Theha Libero® SoC Design Suite Project
Beha sengoloa sa ho fetolela ho ISE® bukana ea morero
python conv_xise_1v0.py -t .xise
Bula Libero SoC Design Suite 'me u tsamaise TCL-script e entsoeng
Morero o entsoe empa ha o eo:
- IP: BlockRAM, my_clocks
- Architectural base-blocks: bufg
Tsoela pele
Mehaho e tšehelitsoeng e etselitsoeng phetoho
- MPFS: PolarFire® SoC
- MPF: PolarFire FPGA
- M2S: SmartFusion®2
- M2GL: IGLOO®2
- AGL: IGLOO
- A3P: ProASIC®3
Lisebelisoa tsa IGLOO le ProASIC3 li hloka mofuta oa Libero SoC 11.9 kapa pejana
Mehaho e meng e tšehetsoeng ke mofuta oa morao-rao oa Libero SoC
Fetola li-PLL le li-DCM
- Khetha lethathamo la IP ho Libero ® SoC Design Suite
- Theha Clock Conditioning Circuit (CCC) bakeng sa maqhubu a hlokahalang
- Khetha "Advanced" tab bakeng sa ho seta bocha
Fetola Li-Buffers tsa Clock tsa Motho ka Mong
Meralo hangata e na le li-buffers tsa oache (BUFG)
- Lilaebrari tse khethehileng tsa barekisi
- Unisim => smartfusion, smartfusion2, polarfire
Ho fetoha ha maikutlo
- BUFG => CLKINT
Litokomane: Tataiso ea Laebrari ea Macro
- SmartFusion®, IGLOO® le ProASIC®3
- SmartFusion2 le IGLOO2
- PolarFire ®
Fetola RAM ea Block
- Theha LSRAM e ncha ho tsoa lethathamong la IP
- Lokisa LSRAM
Theha Shim
- Nka 'mapa o teng oa boema-kepe oa Block RAM
- Theha HDL e ncha file
- Fetola 'mapa oa boema-kepe oa shim
Kenya LSRAM ho Shim
- Fumana phatlalatso ea mokhatlo ho tsoa ho IP file
- Kopanya likou tsa shim ka mohlala
Ntlafatsa Boemo ba Boqapi
Tobetsa Build Hierarchy“
Ho kopanngoa ha mehloli tlas'a moralo oa metso
Lokisa liphoso ho HDL
Matha synthesis
- Litaelo tse nepahetseng tse ka bang teng tse tlalehiloeng ke lisebelisoa
Litšitiso
Tobetsa habeli Laola Litšitiso"
Kenya lithibelo tsa nako
Theha lithibelo tse hlahisitsoeng"
Litšitiso tse hlahisitsoeng:
- Nka ts'ebetso ea PLL (phatlalatso / phase shift)
- Lithibelo "b ehind" phetoho ea oache
Tobetsa ho "Derive Constraints"
- E tlatsa SDC e eketsehileng file
Constrain clock domain crossings
Abela Lithapa
- Motsamaisi oa lithibelo
- Mosebetsi oa ho penya ka tafole
- Pina mosebetsi ka sephutheloana
Phetha Moralo
- Moralo oa sebaka le tsela
- Lekola nako 'me u koale nako
(set_false_path sebakeng sa nako ea nako
- Theha bitstream
E felile
Natefeloa ke nako e telele ea moralo oa hau o mocha oa FPGA
2022 Microchip Technology Inc. le makalana a eona
Litokomane / Lisebelisoa
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MICROCHIP Xilinx Spartan 6 Example Phetoho [pdf] Bukana ea Mosebelisi Xilinx Spartan 6 Example Phetoho, Xilinx, Spartan 6 Example Phetoho, Example Phetoho |
