MICROCHIP Xilinx Spartan 6 Examphloov pauv
Ib Tus Thawj Saib Xyuas Kev Txawj Ntse, Kev Sib Txuas thiab Kev Ruaj Ntseg Embedded Control Solutions
Tsim Libero® SoC Design Suite Project
Muab qhov hloov pauv-ntawv rau hauv ISE® daim ntawv teev npe qhov project
python conv_xise_1v0.py -t .xis
Qhib Libero SoC Design Suite thiab khiav tsim TCL-ntawv
Qhov project yog tsim tab sis ploj lawm:
- IP: BlockRAM, my_clocks
- Architectural puag-blocks: bufg ua
Txuas ntxiv
Txhawb lub hom phiaj architectures rau kev hloov dua siab tshiab
- MPFS: PolarFire® SoC
- MPF: PolarFire FPGA Cov
- M2S: SmartFusion® 2
- M2GL: IGLOO® 2
- AGL: IGLO
- A3P: ProASIC® 3
IGLOO thiab ProASIC3 li xav tau Libero SoC version 11.9 lossis ntxov dua
Lwm cov architectures txhawb nqa nyob rau hauv qhov tseeb version of Libero SoC
Hloov PLLs thiab DCMs
- Xaiv IP catalog hauv Libero ® SoC Design Suite
- Tsim Clock Conditioning Circuit (CCC) rau cov zaus yuav tsum tau ua
- Xaiv Advanced" tab rau pib dua
Hloov Tus Kheej Clock Buffers
Cov qauv tsim feem ntau muaj instantiated moos buffers (BUFG)
- Cov tsev qiv ntawv tshwj xeeb muag khoom
- Unisim => smartfusion, smartfusion2,polarfire
Hloov ntawm instantiations
- BUFG => CLKINT
Cov ntaub ntawv: Macro Library Guide
- SmartFusion®, IGLOO® thiab ProASIC® 3
- SmartFusion2 thiab IGLOO2
- PolarFire ® Cov
Hloov Block RAM
- Tsim LSRAM tshiab los ntawm IP catalog
- Configure LSRAM
Tsim Shim
- Siv daim ntawv qhia chaw nres nkoj uas twb muaj lawm ntawm Block RAM
- Tsim HDL tshiab file
- Adapt chaw nres nkoj daim ntawv qhia ntawm shim
Instantiate LSRAM rau hauv Shim
- Siv cov ntawv tshaj tawm los ntawm IP file
- Txuas shim ports nrog piv txwv
Hloov Kho Tsim Hierarchy
Nyem Tsim Hierarchy"
Kev koom ua ke ntawm cov peev txheej hauv paus tsim
Kho qhov yuam kev hauv HDL
Khiav synthesis
- Kho tej zaum typos qhia los ntawm cov cuab yeej
Kev txwv
Muab ob npaug rau nyem Tswj kev txwv"
Nkag mus rau lub sijhawm txwv
Tsim cov kev txwv tsis pub dhau"
Derived constraints:
- Siv PLL kev ua haujlwm (ntau zaus / theem ua haujlwm)
- Kev txwv "b ehind" moos hloov kho
Nyem rau ntawm "Derive Constraints"
- Populates SDC ntxiv file
Txwv lub moos domain crossings
Muab Pins
- Tus tswj kev txwv
- Pin assignment via table
- Pin assignment ntawm pob
Siv cov qauv tsim
- Qhov chaw thiab txoj kev tsim
- Tshawb xyuas lub sijhawm thiab ua lub sijhawm kaw
(set_false_path ntawm lub moos sau
- Tsim bitstream
Ua tiav
Txaus siab rau lub neej ntev ntawm koj tus qauv FPGA tshiab
2022 Microchip Technology Inc. thiab nws cov koom haum
Cov ntaub ntawv / Cov ntaub ntawv
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