MICROCHIP Xilinx Spartan 6 Exampda Canzawa
Jagoran Mai Ba da Wayo, Haɗe da Amintaccen Maganin Sarrafa Ciki
Ƙirƙiri aikin Libero® SoC Design Suite
Sanya rubutun juzu'i zuwa littafin ISE®
Python conv_xise_1v0.py -t .xisa
Bude Libero SoC Design Suite kuma gudanar da rubutun TCL da aka ƙirƙira
An ƙirƙiri aikin amma ya ɓace:
- IP: BlockRAM, my_clocks
- Tubalan ginin gine-gine: bufg
Ci gaba
Goyan bayan gine-ginen manufa don juyawa
- MPFS: PolarFire® SoC
- MPF: PolarFire FPGA
- M2S: SmartFusion®2
- M2GL: IGLOO®2
- AGL: IGLOO
- A3P: ProASIC®3
Na'urorin IGLOO da ProASIC3 suna buƙatar nau'in Libero SoC 11.9 ko baya
Sauran gine-ginen da aka tallafa a cikin sabuwar sigar Libero SoC
Sauya PLLs da DCMs
- Zaɓi kundin adireshi na IP a cikin Libero ® SoC Design Suite
- Ƙirƙirar da'ira mai sanyaya agogo (CCC) don mitocin da ake buƙata
- Zaɓi Advanced" tab don sake saiti
Maye gurbin Matsalolin Agogo ɗaya
Zane-zane galibi yana ƙunshe da madaidaitan agogon nan take (BUFG)
- takamaiman ɗakunan karatu na mai siyarwa
- Unisim => smartfusion, smartfusion2, gobarar wuta
Canje-canje na hanzari
- BUFG => CLKINT
Takardun: Jagorar Laburaren Makiro
- SmartFusion®, IGLOO® da ProASIC®3
- SmartFusion2 da IGLOO2
- PolarFire®
Sauya Block RAM
- Ƙirƙiri sabon LSRAM daga kundin adireshin IP
- Sanya LSRAM
Ƙirƙiri Shim
- Ɗauki taswirar tashar tashar jiragen ruwa na Block RAM
- Ƙirƙiri sabon HDL file
- Daidaita taswirar tashar jiragen ruwa na shim
Nan take LSRAM cikin Shim
- Dauki sanarwar mahaɗan daga IP file
- Haɗa tashar jiragen ruwa tare da misali
Sabunta Tsarin Tsara
Danna Gina Matsayi"
Haɗuwa da tushe a ƙarƙashin ƙirar tushen
Gyara kurakurai a cikin HDL
Gudanar da kira
- Gyara yuwuwar buga rubutu ta kayan aikin
Matsaloli
Danna sau biyu Sarrafa Constraints"
Shigar da iyakokin lokaci
Ƙirƙirar Matsaloli da Aka Samu"
Matsalolin da aka samu:
- Ɗauki aikin PLL (yawan sauyin lokaci)
- Ƙuntatawar “haɓaka” agogo
Danna kan "Samu Constraints"
- Yawan jama'a ƙarin SDC file
Ƙaddamar da ƙetare yankin agogo
Sanya Fil
- Manajan ƙuntatawa
- Pin aiki ta tebur
- Sanya aikin ta hanyar kunshin
Aiwatar da Zane
- Tsarin wuri da hanya
- Bincika lokaci kuma yi lokacin rufewa
(set_false_path akan yankin agogo
- Ƙirƙiri bitstream
Anyi
Yi farin ciki da dadewa na sabon ƙirar ku na FPGA
2022 Microchip Technology Inc. da rassansa
Takardu / Albarkatu
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MICROCHIP Xilinx Spartan 6 Exampda Canzawa [pdf] Jagorar mai amfani Xilinx Spartan 6 ExampCanjin, Xilinx, Spartan 6 Example Juyawa, Exampda Canzawa |
