MICROCHIP Xilinx Spartan 6 Example Conversion
Mupi Anotungamira weSmart, Akabatana uye Akachengeteka Embedded Control Solutions
Gadzira Libero® SoC Dhizaini Suite Project
Isa shanduko-script muISE® chirongwa dhairekitori
python conv_xise_1v0.py -t .xise
Vhura Libero SoC Dhizaini Suite uye mhanya yakagadzirwa TCL-script
Project yakagadzirwa asi isipo:
- IP: BlockRAM, my_clocks
- Architectural base-blocks: bufg
Kuenderera mberi
Inotsigirwa inotangwa yezvivakwa zvekushandura
- MPFS: PolarFire® SoC
- MPF: PolarFire FPGA
- M2S: SmartFusion®2
- M2GL: IGLOO®2
- AGL: IGLOO
- A3P: ProASIC®3
IGLOO uye ProASIC3 zvishandiso zvinoda Libero SoC vhezheni 11.9 kana kumberi
Zvimwe zvivakwa zvinotsigirwa mune yazvino vhezheni yeLibero SoC
Tsiva PLLs uye DCMs
- Sarudza IP catalog muLibero® SoC Dhizaini Suite
- Gadzira Clock Conditioning Circuit (CCC) yemafrequency anodiwa
- Sarudza Yepamberi" tab yekumisikidza
Tsiva Individual Clock Buffers
Madhizaini anowanzo ane instantiated wachi buffers (BUFG)
- Mutengesi chaiwo raibhurari
- Unisim => smartfusion, smartfusion2,polarfire
Kuchinja kwezviitiko
- BUFG => CLKINT
Zvinyorwa: Macro Library Guide
- SmartFusion®, IGLOO® uye ProASIC®3
- SmartFusion2 uye IGLOO2
- PolarFire ®
Tsiva Block RAM
- Gadzira itsva LSRAM kubva kuIP katalogi
- Gadzirisa LSRAM
Gadzira Shim
- Tora mepu iripo yechiteshi cheBlock RAM
- Gadzira HDL itsva file
- Gadzirisa mepu yechiteshi cheshim
Isa LSRAM muShim
- Tora chiziviso chesangano kubva kuIP file
- Batanidza shim ports nemuenzaniso
Gadziridza Dhizaini Hierarchy
Dzvanya Build Hierarchy"
Kubatanidzwa kwezvinyorwa pasi pekugadzirwa kwemidzi
Gadzirisa zvikanganiso muHDL
Run synthesis
- Hurukuro dzinogona kuitika typos dzinotaurwa nemidziyo
Zvipingamupinyi
Tinya kaviri Manage Constraints"
Pinda zvipingaidzo zvenguva
Gadzira Zvisungo Zvakatorwa"
Derived contraints:
- Tora PLL mashandiro (kuwanza / nhanho shanduko)
- Zvisungo "b ehind" gadziriso yewachi
Dzvanya pa "Dhivha Zvipingamupinyi"
- Inowedzera mamwe SDC file
Constrain clock domain crossings
Govera Pini
- Constraints maneja
- Pin basa kuburikidza netafura
- Pin basa kuburikidza nepasuru
Shandisa Dhizaini
- Nzvimbo uye nzira yekugadzira
- Tarisa nguva uye ita nguva yekuvhara
(set_false_path pane wachi domain
- Gadzira bitstream
Ndapedza
Nakidzwa nehupenyu hurefu hweFPGA yako dhizaini
2022 Microchip Technology Inc. uye masangano ayo
Zvinyorwa / Zvishandiso
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MICROCHIP Xilinx Spartan 6 Example Conversion [pdf] Bhuku reMushandisi Xilinx Spartan 6 Example Shanduko, Xilinx, Spartan 6 Example Kutendeuka, Eksample Conversion |
