Xilinx Spartan-6 Example Conversion

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Step 1: Create Libero® SoC Design Suite Project

Place conversion-script into ISE® project directory. Use the command: python conv_xise_1v0.py -t <arch> <design>.xise.
Open Libero SoC Design Suite and run the created TCL-script.
The project is created but may be missing: IP components like BlockRAM, my_clocks, and architectural base-blocks such as bufg.

Step 1: Continued - Supported Target Architectures

MPFS: PolarFire® SoC
MPF: PolarFire FPGA
M2S: SmartFusion®2
M2GL: IGLOO®2
AGL: IGLOO
A3P: ProASIC®3

Note: IGLOO and ProASIC3 devices require Libero SoC version 11.9 or earlier. Other architectures are supported in the latest version of Libero SoC.

Step 2: Replace PLLs and DCMs

Select the IP catalog in Libero® SoC Design Suite.
Create a Clock Conditioning Circuit (CCC) for the required frequencies.
Choose the "Advanced" tab for reset configuration.

Step 3: Replace Individual Clock Buffers

Designs often contain instantiated clock buffers (BUFG). Vendor-specific libraries like Unisim are used, mapping to smartfusion, smartfusion2, and polarfire.

Change instantiations from BUFG to CLKINT.
Refer to the Macro Library Guide for SmartFusion®, IGLOO®, ProASIC®3, SmartFusion2, IGLOO2, and PolarFire® for detailed information.

Step 4: Replace Block RAM

Create a new LSRAM from the IP catalog.
Configure the LSRAM parameters.

Step 5: Create Shim

Take the existing port map of the Block RAM.
Create a new HDL file for the shim.
Adapt the port map of the shim to match the new requirements.

Step 6: Instantiate LSRAM into Shim

Take the entity declaration from the IP-file for the LSRAM.
Connect the shim ports with the LSRAM instance using the appropriate port mapping.

Step 7: Update Design Hierarchy

Click "Build Hierarchy" to integrate all sources under the root design.
Correct any errors found in the HDL code. For example, syntax errors might occur.
Run synthesis.
Correct potential typos reported by the synthesis tools.

Step 8: Constraints

Double-click "Manage Constraints" to open the constraint management interface.
Enter the necessary timing constraints for the design.

Step 9: Create "Derived Constraints"

Derived constraints leverage PLL functionality (multiply/phase-shift) and are applied "behind" clock modifications.

Click on "Derive Constraints" to populate an additional SDC-file.
Constrain clock domain crossings using commands like set_false_path and set_max_delay.

Step 10: Assign Pins

Utilize the Constraints manager for pin assignments.
Perform pin assignment via a table interface.
Perform pin assignment via the package view.

Step 11: Implement Design

Place and route the design.
Check timing and perform timing closure, often by applying set_false_path on clock domain crossings.
Create the final bitstream.

Step 12: Done

Enjoy the longevity of your new FPGA design.

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