PolarFire Ìdílé FPGA Aṣa Ṣiṣan Itọsọna olumulo
Libero SoC v2024.2

Iṣaaju (Beere ibeere kan)

Sọfitiwia System-on-Chip (SoC) sọfitiwia n pese agbegbe apẹrẹ aaye ti Eto Iṣeto Gate Array (FPGA) ni kikun. Sibẹsibẹ, awọn olumulo diẹ le fẹ lati lo iṣelọpọ ẹni-kẹta ati awọn irinṣẹ adaṣe ni ita agbegbe Libero SoC. Libero le ni bayi ṣepọ si agbegbe apẹrẹ FPGA. A ṣe iṣeduro lati lo Libero SoC lati ṣakoso gbogbo ṣiṣan apẹrẹ FPGA.
Itọsọna olumulo yii ṣe apejuwe Sisan Aṣa fun PolarFire ati awọn ẹrọ Ìdílé PolarFire SoC, ilana kan lati ṣepọ Libero gẹgẹbi apakan ti ṣiṣan apẹrẹ FPGA nla. Awọn idile Ẹrọ ti a ṣe atilẹyin® Tabili ti o tẹle ṣe atokọ awọn idile ẹrọ ti Libero SoC ṣe atilẹyin. Sibẹsibẹ, diẹ ninu alaye ninu itọsọna yii le kan si idile awọn ẹrọ nikan. Ni idi eyi, iru alaye ti wa ni kedere damo.
Tabili 1. Awọn idile Ẹrọ Atilẹyin nipasẹ Libero SoC

Ẹrọ Ìdílé	Apejuwe
PolarFire®	Awọn FPGA PolarFire ṣafihan agbara ti o kere julọ ti ile-iṣẹ ni awọn iwuwo aarin pẹlu aabo iyasọtọ ati igbẹkẹle.
PolarFire SoC	PolarFire SoC jẹ SoC FPGA akọkọ pẹlu ipinnu, isokan RISC-V Sipiyu iṣupọ, ati eto ipilẹ-ipin iranti L2 ti o n mu Linux® ṣiṣẹ ati awọn ohun elo akoko gidi.

Pariview (Beere ibeere kan)

Lakoko ti Libero SoC n pese agbegbe apẹrẹ ipari-si-opin ni kikun lati ṣe idagbasoke SoC ati awọn apẹrẹ FPGA, o tun pese irọrun lati ṣiṣẹ iṣelọpọ ati simulation pẹlu awọn irinṣẹ ẹnikẹta ni ita agbegbe Libero SoC. Sibẹsibẹ, diẹ ninu awọn igbesẹ apẹrẹ gbọdọ wa laarin agbegbe Libero SoC.
Tabili ti o tẹle ṣe atokọ awọn igbesẹ pataki ninu ṣiṣan apẹrẹ FPGA ati tọkasi awọn igbesẹ ti Libero SoC gbọdọ ṣee lo.
Table 1-1. FPGA Design Sisan

Apẹrẹ Flow Igbesẹ	Gbọdọ Lo Libero	Apejuwe
Titẹ sii apẹrẹ: HDL	Rara	Lo olootu HDL ẹni-kẹta/ọpa oluṣayẹwo ni ita Libero® SoC ti o ba fẹ.
Design titẹsi: Configurators	Bẹẹni	Ṣẹda akọkọ Libero ise agbese fun IP katalogi mojuto paati iran.
Laifọwọyi PDC / SDC idiwọ iran	Rara	Awọn ihamọ ti ari nilo gbogbo HDL files ati ohun elo derive_constraints nigba ti a ṣe ni ita ti Libero SoC, gẹgẹ bi a ti ṣe apejuwe rẹ ni Àfikún C-Awọn ihamọ.
Afọwọṣe	Rara	Lo ohun elo ẹni-kẹta ni ita Libero SoC, ti o ba fẹ. Nbeere igbasilẹ ti awọn ile-ikawe simulation ti a ṣajọ tẹlẹ fun ẹrọ ibi-afẹde, simulator ibi-afẹde, ati ẹya Libero ibi-afẹde ti a lo fun imuse ẹhin.
Akopọ	Rara	Lo ohun elo ẹni-kẹta ni ita Libero SoC ti o ba fẹ.
Imuse Oniru: Ṣakoso Awọn ihamọ, Ṣakojọ Netlist, Ibi-ati- Ipa-ọna (wo Loriview)	Bẹẹni	Ṣẹda iṣẹ akanṣe Libero keji fun imuse ẹhin.
Akoko ati Agbara Ijeri	Bẹẹni	Duro ni ise agbese Libero keji.
Ṣe atunto Data Ibẹrẹ Apẹrẹ ati Awọn iranti	Bẹẹni	Lo ọpa yii lati ṣakoso awọn oriṣi awọn iranti ati ipilẹṣẹ apẹrẹ ninu ẹrọ naa. Duro ni iṣẹ akanṣe keji.
Siseto File Iran iran	Bẹẹni	Duro ni iṣẹ akanṣe keji.

Pataki: Iwọ gbọdọ ṣe igbasilẹ awọn ile-ikawe ti a ti ṣajọ tẹlẹ ti o wa ni PreCompiled Simulation Library oju-iwe lati lo simulator ẹni-kẹta.
Ninu ṣiṣan FPGA aṣọ funfun, tẹ apẹrẹ rẹ sii nipa lilo HDL tabi titẹsi sikematiki ki o kọja iyẹn taara
si awọn irinṣẹ iṣelọpọ. Sisan naa tun ni atilẹyin. PolarFire ati PolarFire SoC FPGAs ni pataki
Awọn bulọọki IP lile ti ara ẹni ti o nilo lilo awọn ohun kohun iṣeto (SgCores) lati Libero SoC IP
katalogi. A nilo mimu pataki fun eyikeyi awọn bulọọki ti o ni iṣẹ ṣiṣe SoC:

• PolarFire
  – PF_UPROM
  – PF_SYSTEM_SERVICES
  - PF_CCC
  - PF CLK DIV
  – PF_CRYPTO
  - PF_DRI
  – PF_INIT_MONITOR
  – PF_NGMUX
  - PF_OSC
  Awọn Ramu (TPSRAM, DPSRAM, URAM)
  - PF_SRAM_AHBL_AXI
  - PF_XCVR_ERM
  - PF_XCVR_REF_CLK
  - PF_TX_PLL
  – PF_PCIE
  – PF_IO
  - PF_IOD_CDR
  - PF_IOD_CDR_CCC
  – PF_IOD_GENERIC_RX
  – PF_IOD_GENERIC_TX
  – PF_IOD_GENERIC_TX_CCC
  - PF_RGMII_TO_GMII
  – PF_IOD_OCTAL_DDR
  - PF_DDR3
  - PF_DDR4
  - PF_LPDDR3
  - PF_QDR
  - PF_CORESMARTBERT
  – PF_TAMPER
  - PF_TVS, ati bẹbẹ lọ.

Ni afikun si SgCores ti a ṣe akojọ iṣaaju, ọpọlọpọ awọn IPs asọ ti DirectCore wa fun PolarFire ati awọn idile ẹrọ PolarFire SoC ni Iwe akọọlẹ Libero SoC ti o lo awọn orisun aṣọ FPGA.
Fun titẹsi apẹrẹ, ti o ba lo eyikeyi ọkan ninu awọn paati iṣaaju, o gbọdọ lo Libero SoC fun apakan ti titẹsi apẹrẹ (Iṣeto nkan elo), ṣugbọn o le tẹsiwaju iyoku ti titẹsi Apẹrẹ rẹ (titẹsi HDL, ati bẹbẹ lọ) ni ita Libero. Lati ṣakoso ṣiṣan apẹrẹ FPGA ni ita Libero, tẹle awọn igbesẹ ti a pese ninu iyoku itọsọna yii.
1.1 Yiyipo Igbesi aye paati (Beere ibeere kan)
Awọn igbesẹ wọnyi ṣe apejuwe ọna igbesi aye ti paati SoC ati pese awọn itọnisọna lori bi o ṣe le mu data naa.

1. Ṣe ina paati nipa lilo atunto rẹ ni Libero SoC. Eyi ṣẹda awọn iru data wọnyi:
   HDL files
   – Iranti files
   – Akitiyan ati kikopa files
   – paati SDC file
2. Fun HDL files, ese ati ki o ṣepọ wọn ni awọn iyokù ti HDL oniru lilo awọn ita oniru titẹsi ọpa / ilana.
3. Iranti ipese files ati iwuri files si rẹ kikopa ọpa.
4. Ohun elo Ipese SDC file lati Deri Ihamọ ọpa fun Ihamọ Iran. Wo Àfikún C — Awọn ihamọ fun awọn alaye diẹ sii.
5. O gbọdọ ṣẹda iṣẹ akanṣe Libero keji, nibiti o gbe wọle netlist-Synthesis netlist ati metadata paati rẹ, nitorinaa ipari asopọ laarin ohun ti o ṣe ati ohun ti o ṣe eto.

1.2 Libero SoC Project Creation (Beere ibeere kan)
Diẹ ninu awọn igbesẹ apẹrẹ gbọdọ wa ni ṣiṣe ninu agbegbe Libero SoC (Table 1-1). Fun awọn igbesẹ wọnyi lati ṣiṣẹ, o gbọdọ ṣẹda awọn iṣẹ akanṣe Libero SoC meji. Ni igba akọkọ ti ise agbese ti wa ni lo fun oniru paati iṣeto ni ati iran, ati awọn keji ise agbese ni fun awọn ti ara imuse ti awọn oke-ipele oniru.
1.3 Iṣan aṣa (Beere ibeere kan)
Nọmba atẹle yii fihan:

• Libero SoC le ṣepọ bi apakan ti ṣiṣan apẹrẹ FPGA ti o tobi julọ pẹlu iṣelọpọ ẹnikẹta ati awọn irinṣẹ adaṣe ni ita agbegbe Libero SoC.
• Awọn igbesẹ oriṣiriṣi ti o ni ipa ninu ṣiṣan, ti o bẹrẹ lati ẹda apẹrẹ ati stitching gbogbo ọna si siseto ẹrọ naa.
• Paṣipaarọ data (awọn igbewọle ati awọn abajade) ti o gbọdọ waye ni igbesẹ ṣiṣan apẹrẹ kọọkan.

Imọran:

1. SNVM.cfg, UPROM.cfg
2. *.mem file iran fun Simulation: pa4rtupromgen.exe gba UPROM.cfg bi input ki o si se ina UPROM.mem.

Awọn atẹle jẹ awọn igbesẹ ni ṣiṣan aṣa:

1. Iṣeto eroja ati iran:
   a. Ṣẹda iṣẹ akanṣe Libero akọkọ (lati ṣiṣẹ bi Itọkasi Itọkasi).
   b. Yan Core lati Katalogi. Tẹ mojuto lẹẹmeji lati fun orukọ paati kan ati tunto paati naa.
   Eleyi laifọwọyi okeere data paati ati files. Awọn afihan paati kan tun ṣe ipilẹṣẹ. Wo Awọn afihan Ẹya fun awọn alaye. Fun alaye diẹ ẹ sii, wo Iṣeto paati.
2. Pari apẹrẹ RTL rẹ ni ita Libero:
   a. Inseteriate awọn paati HDL files.
   b. Ipo ti HDL files ti wa ni akojọ si ni Awọn afihan Ẹka files.
3. Ṣe ina SDC inira fun awọn paati. Lo IwUlO Awọn Idiwọn lati ṣe ipilẹṣẹ idiwọ akoko file(SDC) da lori:
   a. Ohun elo HDL files
   b. Ẹya SDC files
   c. HDL olumulo files
   Fun awọn alaye diẹ sii, wo Àfikún C—Awọn inira Ti a dari.
4. Irinṣẹ aropọ/ohun elo iṣeṣiro:
   a. Gba HDL files, iwuri files, ati data paati lati awọn ipo pato bi a ti ṣe akiyesi ninu Awọn Afihan Ẹka.
   b. Ṣepọ ati ṣe afiwe apẹrẹ pẹlu awọn irinṣẹ ẹnikẹta ni ita Libero SoC.
5. Ṣẹda keji rẹ (Imuse) Project Libero.
6. Yọ kolaginni lati awọn oniru sisan ọpa pq (Ise agbese> Project Eto> Design Sisan> ko awọn Jeki Synthesis ayẹwo apoti).
7. Gbe wọle orisun oniru files (ifiweranṣẹ-sọpọ * .vm netlist lati inu ohun elo iṣelọpọ):
   - Akowọle lẹhin-akopọ * .vm netlist (File> Gbe wọle> Akopọ Verilog Netlist (VM)).
   – Metadata paati * .cfg files fun uPROM ati/tabi sNVM.
8. Gbe wọle eyikeyi paati Àkọsílẹ Liro SoC files. Àkọsílẹ naa files gbọdọ wa ni * .cxz file ọna kika.
   Fun alaye diẹ sii lori bi o ṣe le ṣẹda bulọọki, wo Itọsọna olumulo PolarFire Block Ṣiṣan.
9. Ṣe agbewọle awọn idiwọ apẹrẹ:
   – Gbe wọle I/O ihamọ files (Oluṣakoso Awọn ihamọ> I/Awọn eroja> Gbe wọle).
   – Gbe wọle pakàplanning * .pdc files (Oluṣakoso Awọn ihamọ> Oluṣeto ilẹ> Gbe wọle).
   – Gbe wọle * .sdc ìlà inira files (Oluṣakoso Awọn ihamọ> Akoko> Gbe wọle). Gbe SDC wọle file ti ipilẹṣẹ nipasẹ Deive Constraint ọpa.
   – Gbe wọle * .ndc inira files (Oluṣakoso Awọn ihamọ> NetlistAttributes> Gbe wọle), ti eyikeyi.
10. Ihamọ file ati ẹgbẹ irinṣẹ
    – Ni awọn Constraint Manager, láti * .pdc files lati gbe ati ipa ọna, awọn * .sdc files lati gbe ati ipa-ọna ati awọn iṣeduro akoko, ati * .ndc files lati sakojo Netlist.
11. Imuse apẹrẹ pipe
    - Ibi ati ipa ọna, ṣayẹwo akoko ati agbara, tunto data ipilẹṣẹ apẹrẹ ati awọn iranti, ati siseto file iran.
12. Fidi apẹrẹ naa
    - Ṣe ifọwọsi apẹrẹ lori FPGA ati yokokoro bi o ṣe pataki nipa lilo awọn irinṣẹ apẹrẹ ti a pese pẹlu suite apẹrẹ Libero SoC.

Iṣeto eroja (Beere ibeere kan)

Igbesẹ akọkọ ninu ṣiṣan aṣa ni lati tunto awọn paati rẹ nipa lilo iṣẹ itọkasi Libero (ti a tun pe ni iṣẹ akanṣe Libero akọkọ ni Tabili 1-1). Ni awọn igbesẹ ti o tẹle, o lo data lati inu iṣẹ itọkasi yii.
Ti o ba nlo awọn paati eyikeyi ti a ṣe akojọ tẹlẹ, labẹ Ipariview ninu apẹrẹ rẹ, ṣe awọn igbesẹ ti a ṣalaye ni apakan yii.
Ti o ko ba lo eyikeyi awọn paati ti o wa loke, o le kọ RTL rẹ ni ita ti Libero ki o gbe wọle taara sinu Synthesis ati awọn irinṣẹ Simulation rẹ. Lẹhinna o le tẹsiwaju si apakan lẹhin iṣelọpọ ati gbe wọle nikan lẹhin-synthesis * .vm netlist sinu iṣẹ imuse Libero ipari rẹ (ti a tun pe ni iṣẹ akanṣe Libero keji ni Tabili 1-1).
2.1 Iṣeto ni nkan elo Lilo Libero (Beere ibeere kan)
Lẹhin yiyan awọn paati ti o gbọdọ lo lati atokọ iṣaaju, ṣe awọn igbesẹ wọnyi:

1. Ṣẹda iṣẹ akanṣe Libero tuntun kan (Iṣeto ipilẹ ati Iran): Yan Ẹrọ ati Ẹbi ti o fojusi apẹrẹ ipari rẹ si.
2. Lo ọkan tabi diẹ ẹ sii ti awọn ohun kohun ti a mẹnuba ninu Ṣiṣan Aṣa.
   a. Ṣẹda SmartDesign kan ki o tunto mojuto ti o fẹ ki o ṣe imudara rẹ ni paati SmartDesign.
   b. Ṣe igbega gbogbo awọn pinni si ipele oke.
   c. Ṣẹda SmartDesign.
   d. Tẹ lẹẹmeji ohun elo Simulate (eyikeyi Pre-Synthesis tabi Post-Synthesis tabi Awọn aṣayan Ifilelẹ Ifilelẹ) lati pe simulator naa. O le jade kuro ni simulator lẹhin ti o ti pe. Igbese yii n ṣe agbekalẹ simulation naa files pataki fun ise agbese rẹ.

Imọran: Iwọ gbọdọ ṣe igbesẹ yii ti o ba fẹ ṣe simulate apẹrẹ rẹ ni ita Libero.
Fun alaye diẹ sii, wo Simulating Your Design.
e. Fi iṣẹ akanṣe rẹ pamọ - eyi ni iṣẹ itọkasi rẹ.
2.2 Awọn ifihan paati (Beere ibeere kan)
Nigba ti o ba se ina rẹ irinše, a ti ṣeto ti files ti ipilẹṣẹ fun kọọkan paati. The paati Manifest Iroyin alaye awọn ṣeto ti files ti ipilẹṣẹ ati lilo ni igbesẹ kọọkan ti o tẹle (Synthesis, Simulation, Firmware Generation, ati bẹbẹ lọ). Iroyin yii fun ọ ni awọn ipo ti gbogbo awọn ti ipilẹṣẹ files nilo lati tẹsiwaju pẹlu Sisan Aṣa. O le wọle si paati farahan ni agbegbe Awọn ijabọ: Tẹ Apẹrẹ> Awọn ijabọ lati ṣii taabu Awọn ijabọ. Ni awọn Iroyin taabu, o ri kan ti ṣeto ti manifest.txt files (O pariview), ọkan fun kọọkan paati ti o ti ipilẹṣẹ.
Imọran: O gbọdọ ṣeto paati kan tabi module bi '”root”' lati rii ifihan paati file awọn akoonu ninu awọn Iroyin taabu.
Ni omiiran, o le wọle si ijabọ ifihan ẹni kọọkan files fun kọọkan mojuto paati ti ipilẹṣẹ tabi SmartDesign paati lati / paati / iṣẹ / / / _manifest.txt tabi / paati / iṣẹ / / _manifest.txt. O tun le wọle si ifihan file awọn akoonu ti kọọkan paati ti ipilẹṣẹ lati titun irinše taabu ni Libero, ibi ti awọn file awọn ipo ti wa ni mẹnuba pẹlu ọwọ si ise agbese liana.Fojusi lori awọn ijabọ Ifihan Ẹka ti o tẹle:

• Ti o ba fi awọn ohun kohun sinu SmartDesign kan, ka awọn file _manifest.txt.
• Ti o ba da irinše fun ohun kohun, ka awọn _manifest.txt.

O gbọdọ lo gbogbo awọn ijabọ Ifihan Ẹka ti o kan apẹrẹ rẹ. Fun exampLe, ti iṣẹ akanṣe rẹ ba ni SmartDesign pẹlu ọkan tabi diẹ ẹ sii awọn paati mojuto ti o wa ninu rẹ ati pe o pinnu lati lo gbogbo wọn ni apẹrẹ ipari rẹ, lẹhinna o gbọdọ yan files ti a ṣe akojọ si ni Awọn ijabọ Ifihan Ẹka ti gbogbo awọn paati wọnyẹn fun lilo ninu ṣiṣan apẹrẹ rẹ.
2.3 Itumọ Ifihan Files (Beere ibeere kan)
Nigbati o ṣii ifihan paati kan file, o ri awọn ọna lati files ninu iṣẹ akanṣe Libero rẹ ati awọn itọka lori ibiti o wa ninu ṣiṣan apẹrẹ lati lo wọn. O le wo awọn iru atẹle wọnyi files ni a farahan file:

• HDL orisun files fun gbogbo Synthesis ati Simulation irinṣẹ
• Imudara files fun gbogbo Simulation irinṣẹ
• Ihamọ files

Atẹle ni Ifihan Ẹya ti paati mojuto PolarFire kan.Kọọkan iru ti file jẹ pataki ibosile ninu rẹ oniru sisan. Awọn wọnyi ruju apejuwe Integration ti awọn files lati farahan sinu sisan oniru rẹ.

Iran Idiwọn (Beere ibeere kan)

Nigbati o ba n ṣiṣẹ iṣeto ni ati iran, rii daju lati kọ / ipilẹṣẹ SDC / PDC / NDC inira files fun apẹrẹ lati gbe wọn lọ si Synthesis, Ibi-ati-Route, ati Ṣayẹwo awọn irinṣẹ akoko.
Lo IwUlO Awọn Idiwọn IwUlO ni ita ti agbegbe Libero lati ṣe ipilẹṣẹ awọn ihamọ dipo kikọ wọn pẹlu ọwọ. Lati lo IwUlO Iṣeduro Derive ni ita agbegbe Libero, o gbọdọ:

• Ipese HDL olumulo, HDL paati, ati ihamọ SDC paati files
• Pato awọn oke ipele module
• Pato ipo ibiti o ti le ṣe ipilẹṣẹ idiwọ ti ari files

Awọn ihamọ paati SDC wa labẹ / paati / iṣẹ / / / liana lẹhin paati iṣeto ni ati iran.
Fun awọn alaye diẹ sii lori bi o ṣe le ṣe awọn idiwọ fun apẹrẹ rẹ, wo Àfikún C — Awọn ihamọ Iwadii.

Ṣiṣẹpọ Apẹrẹ Rẹ (Beere ibeere kan)

Ọkan ninu awọn ẹya akọkọ ti Sisan Aṣa ni lati gba ọ laaye lati lo iṣelọpọ ẹnikẹta
ọpa ita Libero. Sisan aṣa ṣe atilẹyin lilo Synopsys SynplifyPro. Lati ṣepọ rẹ
ise agbese, lo awọn ilana wọnyi:

1. Ṣẹda iṣẹ akanṣe tuntun ninu ohun elo Synthesis rẹ, fojusi idile ẹrọ kanna, ku, ati package bi iṣẹ akanṣe Libero ti o ṣẹda.
   a. Ṣe agbewọle RTL tirẹ files bi o ṣe deede.
   b. Ṣeto iṣẹjade Synthesis lati jẹ Verilog Structural (.vm).
   Imọran: Ilana Verilog (.vm) jẹ ọna kika iṣelọpọ iṣelọpọ atilẹyin nikan ni PolarFire.
2. Gbe wọle HDL paati files sinu ise agbese Synthesis rẹ:
   a. Fun Ijabọ Ifihan Ẹka kọọkan: Fun ọkọọkan file labẹ HDL orisun files fun gbogbo Synthesis ati Simulation irinṣẹ, gbe wọle awọn file sinu rẹ Synthesis Project.
3. Gbe wọle awọn file polarfire_syn_comps.v (ti o ba ti lilo Synopsys Synplify) lati
   Ipo fifi sori ẹrọ>/data/aPA5M si iṣẹ akanṣe Synthesis rẹ.
4. Ṣe agbewọle SDC ti ipilẹṣẹ tẹlẹ file nipasẹ ohun elo Ihamọ ti ari (wo Àfikún
   A—Sample SDC inira) sinu Synthesis ọpa. Idiwọn yii file ṣe idiwọ ọpa iṣelọpọ lati ṣaṣeyọri pipade akoko pẹlu igbiyanju diẹ ati awọn iterations apẹrẹ diẹ.

Pataki: 

• Ti o ba gbero lati lo * .sdc kanna file lati ṣe idiwọ Ibi-ati-Route lakoko ipele imuse apẹrẹ, o gbọdọ gbe * .sdc yii sinu iṣẹ iṣelọpọ. Eyi ni lati rii daju pe ko si awọn aiṣedeede orukọ ohun apẹrẹ ni akojọ nẹtiwọọki ti iṣelọpọ ati awọn ihamọ Ibi-ati-Route lakoko ipele imuse ti ilana apẹrẹ. Ti o ko ba ni eyi * .sdc file ni Igbesẹ Synthesis, nẹtiwọọki ti ipilẹṣẹ lati Synthesis le kuna Ibi ati Igbesẹ Ipa-ọna nitori awọn aiṣedeede orukọ ohun apẹrẹ.
  a. Ṣe agbewọle Awọn abuda Nẹtiwọọki * .ndc, ti eyikeyi, sinu irinṣẹ Synthesis.
  b. Ṣiṣe Synthesis.
• Ipo ti iṣelọpọ irinṣẹ Synthesis rẹ ni * .vm netlist file ti ipilẹṣẹ post Synthesis. O gbọdọ gbe netlist wọle sinu Ise agbese imuse Libero lati tẹsiwaju pẹlu ilana apẹrẹ.

Ṣiṣe Apẹrẹ Rẹ (Beere ibeere kan)

Lati ṣe adaṣe apẹrẹ rẹ ni ita Libero (iyẹn ni, lilo agbegbe kikopa tirẹ ati simulator), ṣe awọn igbesẹ wọnyi:

1. Apẹrẹ Files:
   a. Iṣaṣeṣe iṣaaju-Sinthesis:
   Ṣe agbewọle RTL rẹ sinu iṣẹ akanṣe rẹ.
   • Fun Ijabọ Ifihan Ẹka kọọkan.
   – Gbe wọle kọọkan file labẹ HDL orisun files fun gbogbo Synthesis ati Simulation irinṣẹ sinu rẹ kikopa ise agbese.
   Ṣe akojọpọ awọn wọnyi files gẹgẹbi fun awọn itọnisọna simulator rẹ.
   b. Simulation lẹhin iṣelọpọ:
   Ṣe agbewọle ifiweranṣẹ ifiweranṣẹ rẹ * .vm netlist (ti ipilẹṣẹ ni Ṣiṣẹpọ Apẹrẹ Rẹ) sinu iṣẹ akanṣe rẹ ki o ṣajọ rẹ.
   c. Simulation lẹhin igbekalẹ:
   • Ni akọkọ, pari imuse apẹrẹ rẹ (wo Ṣiṣe Apẹrẹ Rẹ). Rii daju pe iṣẹ akanṣe Libero rẹ ti o kẹhin wa ni ipo-ifiweranṣẹ.
   • Tẹ lẹẹmeji Ṣe ina BackAnnotated Files ni Libero Design Flow window. O ṣẹda meji files:
   / onise / / _ba.v/vhd / onise /
   / _ba.sdf
   Ṣe agbewọle awọn mejeeji wọnyi files sinu rẹ kikopa ọpa.
2. Imudara ati Iṣeto files:
   a. Fun Ijabọ Ifihan Ẹka kọọkan:
   Daakọ gbogbo rẹ files labẹ Stimulus Files fun gbogbo awọn apakan Awọn irinṣẹ Simulation si itọsọna gbongbo ti iṣẹ akanṣe Simulation rẹ.
   b. Rii daju pe eyikeyi Tcl files ninu awọn akojọ ti o ti kọja (ni igbese 2.a) ti wa ni ṣiṣe ni akọkọ, ṣaaju ibẹrẹ ti kikopa.
   c. UPROM.mem: Ti o ba lo mojuto UPROM ninu apẹrẹ rẹ pẹlu aṣayan Lo akoonu fun kikopa ṣiṣẹ fun ọkan tabi diẹ ẹ sii awọn onibara ipamọ data ti o fẹ lati ṣe afarawe, o gbọdọ lo pa4rtupromgen (pa4rtupromgen.exe lori awọn window) lati ṣe ina UPROM.mem. file. Pa4rtupromgen executable gba UPROM.cfg file bi awọn igbewọle nipasẹ a Tcl akosile file ati awọn abajade UPROM.mem file beere fun iṣeṣiro. Eleyi UPROM.mem file gbọdọ wa ni daakọ si folda kikopa ṣaaju ṣiṣe kikopa. Ohun example fifi pa4rtupromgen executable lilo ti pese ni awọn wọnyi awọn igbesẹ ti. Awọn UPROM.cfg file wa ninu liana / paati / iṣẹ / / ninu iṣẹ akanṣe Libero ti o lo lati ṣe agbejade paati UPROM.
   d. snvm.mem: Ti o ba lo mojuto Awọn iṣẹ Eto ninu apẹrẹ rẹ ati tunto taabu sNVM ninu mojuto pẹlu aṣayan Lo akoonu fun kikopa ṣiṣẹ fun ọkan tabi diẹ sii awọn alabara ti o fẹ lati ṣe afarawe, snvm.mem kan file ti wa ni laifọwọyi ti ipilẹṣẹ si
   liana / paati / iṣẹ / / ninu iṣẹ akanṣe Libero ti o lo lati ṣe ipilẹṣẹ paati Awọn iṣẹ Eto. Eleyi snvm.mem file gbọdọ wa ni daakọ si folda kikopa ṣaaju ṣiṣe kikopa.
3. Ṣẹda folda ti n ṣiṣẹ ati iha-folda ti a npè ni kikopa labẹ folda iṣẹ.
   Awọn pa4rtupromgen executable reti niwaju kikopa iha folda ninu awọn ṣiṣẹ folda ati * .tcl akosile ti wa ni gbe ni kikopa iha folda.
4. Da UPROM.cfg file lati akọkọ Libero ise agbese da fun paati iran sinu ṣiṣẹ folda.
5. Lẹẹmọ awọn aṣẹ wọnyi ni iwe afọwọkọ * .tcl kan ki o si fi sii sinu folda kikopa ti a ṣẹda ni igbesẹ 3.
   Sample * .tcl fun PolarFire ati awọn ẹrọ Ìdílé PolarFire Soc lati ṣe ipilẹṣẹ URPOM.mem file
   lati UPROM.cfg
   set_device -fam -kú pkg
   set_input_cfg -ona
   set_sim_mem -onaFile/UPROM.mem>
   gen_sim -use_init eke
   Fun orukọ inu to dara lati lo fun ku ati package, wo * .prjx file ti akọkọ Libero ise agbese (lo fun paati iran).
   Awọn ariyanjiyan use_init gbọdọ wa ni ṣeto si eke.
   Lo aṣẹ set_sim_mem lati pato ọna si iṣẹjade file UPROM.mem ti o jẹ
   ti ipilẹṣẹ lori ipaniyan ti akosile file pẹlu pa4rtupromgen executable.
6. Ni aṣẹ aṣẹ tabi ebute cygwin, lọ si itọsọna iṣẹ ti a ṣẹda ni igbesẹ 3.
   Ṣiṣe pipaṣẹ pa4rtupromgen pẹlu aṣayan-afọwọkọ ki o kọja si i ni * .tcl iwe afọwọkọ ti a ṣẹda ni igbesẹ ti tẹlẹ.
   Fun Windows
   / onise/bin/pa4rtupromgen.exe \
   -script./simulation/ .tcl
   Fun Linux:
   / bin/pa4rtupromgen
   -script./simulation/ .tcl
7. Lẹhin ipaniyan aṣeyọri ti pa4rtupromgen executable, ṣayẹwo pe UPROM.mem naa file ti ipilẹṣẹ ni awọn ipo pato ninu awọn pipaṣẹ set_sim_mem ni * .tcl akosile.
8. Lati ṣe afarawe sNVM, daakọ snvm.mem file lati inu iṣẹ akanṣe Libero akọkọ rẹ (ti a lo fun iṣeto paati) sinu folda kikopa ipele oke ti iṣẹ akanṣe rẹ lati ṣiṣẹ kikopa (ni ita ti Libero SoC). Lati ṣe afarawe awọn akoonu UPROM, daakọ ipilẹṣẹ UPROM.mem file sinu folda kikopa oke ipele ti iṣẹ akanṣe rẹ lati ṣiṣẹ kikopa (ita Libero SoC).

Pataki: Lati ṣe afiwe iṣẹ ṣiṣe ti Awọn paati SoC, ṣe igbasilẹ awọn ile-ikawe simulation PolarFire ti a ti ṣajọ tẹlẹ ki o gbe wọn wọle si agbegbe kikopa rẹ bi a ti ṣalaye rẹ nibi. Fun awọn alaye diẹ sii, wo Àfikún B-Ikowọle Awọn ile-ikawe Simulation sinu Ayika Simulation.

Ṣiṣe Apẹrẹ Rẹ (Beere ibeere kan)

Lẹhin ti pari Synthesis ati Simulation Post-Synthesis ni agbegbe rẹ, o gbọdọ lo Libero lẹẹkansi lati ṣe imuse apẹrẹ rẹ ti ara, ṣiṣe akoko ati itupalẹ agbara, ati ṣe agbekalẹ siseto rẹ file.

1. Ṣẹda iṣẹ akanṣe Libero tuntun fun imuse ti ara ati ifilelẹ ti apẹrẹ. Rii daju lati fojusi ẹrọ kanna gẹgẹbi ninu iṣẹ akanṣe itọkasi ti o ṣẹda ni Iṣeto Ẹka.
2. Lẹhin ṣiṣẹda ise agbese, yọ Synthesis kuro ni pq ọpa ni window Flow Design (Ise agbese> Eto Eto> Sisan Apẹrẹ> Ṣiṣayẹwo Ṣiṣe Agbekale).
3.  Ṣe agbewọle ifiweranṣẹ ifiweranṣẹ rẹ * .vm file sinu iṣẹ akanṣe yii, (File > Gbe wọle > Apapọ Verilog Netlist (VM)).
   Imọran: A gba ọ niyanju pe ki o ṣẹda ọna asopọ kan si eyi file, ki ti o ba ti o ba resynthesize rẹ oniru, Libero nigbagbogbo nlo awọn titun post-synthesis netlist.
   a. Ni awọn Oniru window logalomomoise, akiyesi awọn orukọ ti awọn root module.
4. Ṣe agbewọle awọn idiwọ sinu iṣẹ akanṣe Libero. Lo Oluṣakoso Ihamọ lati gbe wọle * .pdc/*.sdc/* .ndc inira.
   a. Gbe wọle I / O * .pdc ihamọ files (Oluṣakoso Awọn ihamọ> Awọn eroja I/O> gbe wọle).
   b. Gbe wọle Floorplanning * .pdc inira files (Oluṣakoso Awọn ihamọ> Alakoso Ilẹ> Gbe wọle).
   c. Gbe wọle * .sdc akoko ihamọ files (Oluṣakoso Awọn ihamọ> Akoko> Gbe wọle). Ti apẹrẹ rẹ ba ni eyikeyi awọn ohun kohun ti a ṣe akojọ si ni Loriview, rii daju lati gbe SDC wọle file ti ipilẹṣẹ nipasẹ nianfani ihamọ ọpa.
   d. Gbe wọle * .ndc ihamọ files (Oluṣakoso Awọn ihamọ> Awọn eroja Netlist> Gbe wọle).
5. Associate inira Files to oniru irinṣẹ.
   a. Ṣii Oluṣakoso Ihamọ (Ṣakoso Awọn ihamọ> Ṣii Ṣakoso awọn ihamọ View).
   Ṣayẹwo aaye-ati-Ipa-ọna ati Ijẹrisi Iṣayẹwo akoko apoti lẹgbẹẹ ihamọ naa file lati fi idi idiwon file ati ẹgbẹ irinṣẹ. Darapọ mọ idinamọ * .pdc si Ibi-ati Ipa-ọna ati * .sdc si aaye-ati-Ipa-ọna mejeeji ati Ijeri akoko. Darapọ mọ * .ndc file lati sakojo Netlist.
   Imọran: Ti o ba Ibi ati Ipa ọna kuna pẹlu idinamọ * .sdc yii file, lẹhinna gbe wọle kanna * .sdc file lati ṣajọpọ ati tun-ṣiṣẹpọ.
6. Tẹ Akopọ Netlist ati lẹhinna Gbe ati Ipa ọna lati pari igbesẹ akọkọ.
7. Data Ibẹrẹ Apẹrẹ Tunto ati ohun elo Awọn iranti ngbanilaaye lati ṣe ipilẹṣẹ awọn bulọọki apẹrẹ, gẹgẹbi LSRAM, µSRAM, XCVR (awọn transceivers), ati PCIe ni lilo data ti o fipamọ sinu µPROM ti kii ṣe iyipada, sNVM, tabi iranti ibi ipamọ Flash SPI ita. Ọpa naa ni awọn taabu atẹle fun asọye sipesifikesonu ti ọkọọkan ibẹrẹ apẹrẹ, sipesifikesonu ti awọn alabara ibẹrẹ, awọn alabara data olumulo.
   – Apẹrẹ Ibẹrẹ taabu
   – µPROM taabu
   – sNVM taabu
   – SPI Flash taabu
   - Aṣọ Ramu taabu
   Lo awọn taabu inu ọpa lati tunto data ipilẹṣẹ apẹrẹ ati awọn iranti.Lẹhin ipari iṣeto ni, ṣe awọn igbesẹ wọnyi lati ṣe eto data ibẹrẹ:
   • Ṣe ipilẹṣẹ awọn alabara ibẹrẹ
   • Ṣe ina tabi okeere bitstream
   Ṣeto ẹrọ naa
   Fun alaye alaye lori bi o ṣe le lo ọpa yii, wo Itọsọna olumulo Sisan Apẹrẹ Libero SoC. Fun alaye diẹ sii lori awọn aṣẹ Tcl ti a lo lati tunto awọn taabu pupọ ninu ọpa ati pato iṣeto iranti files (*.cfg), wo Itọsọna Itọkasi Awọn aṣẹ Tcl.
8. Ṣẹda Eto kan File lati iṣẹ akanṣe yii ki o lo lati ṣe eto FPGA rẹ.

Àfikún A—SampAwọn ihamọ SDC (Beere ibeere kan

Libero SoC ṣe ipilẹṣẹ awọn ihamọ akoko SDC fun awọn ohun kohun IP kan, gẹgẹbi CCC, OSC, Transceiver ati bẹbẹ lọ. Gbigbe awọn idiwọ SDC si awọn irinṣẹ apẹrẹ ṣe alekun aye ti ipade pipade akoko pẹlu igbiyanju ti o dinku ati awọn iterations apẹrẹ diẹ. Ọna iṣakoso ni kikun lati apẹẹrẹ ipele-oke ni a fun fun gbogbo awọn nkan apẹrẹ ti a tọka si awọn ihamọ.
7.1 SDC Awọn ihamọ akoko (Beere ibeere kan)
Ninu iṣẹ itọkasi mojuto Libero IP, idiwọ SDC ipele-oke yii file wa lati Oluṣakoso Ihamọ (Sisan Apẹrẹ> Ṣii Ṣakoso ihamọ View > Aago> Awọn ihamọ ti a gba).
Pataki: Wo eyi file lati ṣeto awọn ihamọ SDC ti apẹrẹ rẹ ba ni CCC, OSC, Transceiver, ati awọn paati miiran. Ṣatunṣe ọna ilana ni kikun, ti o ba jẹ dandan, lati baamu awọn ilana aṣapẹrẹ rẹ tabi lo IwUlO Derive_Constraints ati awọn igbesẹ ni Àfikún C — Awọn ihamọ lori ipele paati SDC file.
Fipamọ awọn file si orukọ ti o yatọ ati gbe SDC wọle file si irinṣẹ iṣelọpọ, Ibi-ati-Ọpa Ipa-ọna, ati Awọn Imudaniloju akoko, gẹgẹ bi eyikeyi idiwọ SDC miiran files.
7.1.1 Ti ari SDC File (Beere ibeere kan)
# Eyi file ti ipilẹṣẹ da lori awọn wọnyi SDC orisun files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/ paati/iṣẹ/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/ paati/iṣẹ/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/ paati/iṣẹ/
TRANSMIT_PLL/ TRANSMIT_PLL_0/TARANSMIT_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/ paati/iṣẹ/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/ paati/iṣẹ/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/ paati/iṣẹ/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/ paati/iṣẹ/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/ paati/iṣẹ/
PCIE_INITIATOR/ PCIE_INITIATOR_0/ PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** Eyikeyi awọn iyipada si eyi file yoo sọnu ti o ba ti awọn ihamọ ti ari ti wa ni tun-ṣiṣe. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} -akoko 6.25
[ gba_pins {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } ] create_clock -name {REF_CLK_PAD_P} -akoko 10 [gba_ports {REF_CLK_PAD_P} ] create_clock -name {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/tx
DIV_CLK} -akoko 8
[ gba_pins {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK } ] ṣẹda_generated_clock -orukọ {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/P_CC_0/P_CC
OUT0} -multiply_by 25 -divide_by 32 -orisun
[gba_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -ipele 0
[gba_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0} ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT1} -multiply_by 25 -divide_by 32 -orisun
[gba_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -ipele 0
[gba_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1} ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT2} -multiply_by 25 -divide_by 32 -orisun
[gba_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -ipele 0
[gba_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2} ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT3} -multiply_by 25 -divide_by 64 -orisun
[gba_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -ipele 0
[gba_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3} ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_DIMZ
Y_DIV} -divide_by 2 -orisun
[gba_pins {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CLK_DIV_0/I_CD/A} ] [gba_pins { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80V_CD_DIV set_false_path -through [ get_nets { DMA_INITIATOR_inst_0/ARESETN*} ] set_false_path -lati [gba_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*]].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray*}] -si [gba_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1* } ] set_false_path -lati [gba_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray*}] -si [gba_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1*} ] set_false_path -nipasẹ [gba_nets {FIC0_INITIATOR_inst_0/ARESETN*} ] set_false_path -to [gba_pins {PCIE/PF_PCIE_C0_0/ PCIE_1/INTERRUPT[0] PCIE/PF_PCIE_C0
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/ PCIE_1/MPERST_N} ] set_false_path -lati [gba_pins { PCIE/PF_PCIE_C0_0/ PCIE_1/TL_CLK} ] set_false_path -nipasẹ [get_nets {PCIE_NITIA] Àfikún B—Ṣiṣewọle Awọn ile-ikawe Simulation sinu Ayika Simulation (Beere ibeere kan)
Simulator aiyipada fun kikopa RTL pẹlu Libero SoC jẹ ModelSim ME Pro.
Awọn ile-ikawe ti a ṣajọ tẹlẹ fun simulator aiyipada wa pẹlu fifi sori ẹrọ Libero ni itọsọna /Apẹrẹ/lib/modelsimpro/precompiled/vlog for® atilẹyin idile. Libero SoC tun ṣe atilẹyin awọn ẹda simulators ẹni-kẹta miiran ti ModelSim, Questasim, VCS, Xcelium
, HDL ti nṣiṣe lọwọ, ati Riviera Pro. Ṣe igbasilẹ awọn oniwun awọn ile-ikawe ti a ṣajọ tẹlẹ lati Libero SoC v12.0 ati nigbamii da lori simulator ati ẹya rẹ.
Iru si Libero ayika, run.do file gbọdọ wa ni da lati ṣiṣe kikopa ita Libero.
Ṣẹda ṣiṣe ti o rọrun.do file ti o ni awọn aṣẹ lati fi idi ile-ikawe silẹ fun awọn abajade akojọpọ, ṣiṣe aworan ile-ikawe, akojọpọ, ati kikopa. Tẹle awọn igbesẹ lati ṣẹda ipilẹ run.do file.

1. Ṣẹda ile-ikawe ọgbọn lati tọju awọn abajade akopo ni lilo pipaṣẹ vlib vlib presynth.
2. Ṣe maapu orukọ ile-ikawe ọgbọn naa si itọsọna ikawe ti a ṣajọ tẹlẹ nipa lilo vmap pipaṣẹ vmap .
3. Iṣakojọpọ orisun files —lo awọn aṣẹ alakojo ede-kan pato lati ṣajọ apẹrẹ files sinu ṣiṣẹ liana.
   – vlog fun .v/.sv
   – vcom fun .vhd
4. Fifuye apẹrẹ fun kikopa nipa lilo pipaṣẹ vsim nipa sisọ orukọ eyikeyi module ipele-oke.
5. Ṣe afarawe apẹrẹ nipa lilo pipaṣẹ ṣiṣe.
   Lẹhin ikojọpọ apẹrẹ, akoko kikopa ti ṣeto si odo, ati pe o le tẹ aṣẹ ṣiṣe lati bẹrẹ simulation.
   Ninu ferese tiransikiripiti simulator, ṣiṣẹ run.do file bi run.do ṣiṣe kikopa. Sample run.do file ni atẹle.

ni idakẹjẹ ṣeto ACTELLIBNAME PolarFire ni idakẹjẹ ṣeto PROJECT_DIR "W:/Test/Basic_test" ti o ba jẹ
{[file tẹlẹ presynth/_info]} {echo “INFO: Simulation Library presynth”} miiran
{ file paarẹ -force presynth vlib presynth } vmap presynth presynth vmap PolarFire
"X:/Libero/Apẹrẹ/lib/modelsimpro/precompiled/vlog/PolarFire" vlog -sv -work presynth
"${PROJECT_DIR}/hdl/top.v" vlog "+incdir+${PROJECT_DIR}/stimulus" -sv -iṣẹ presynth "$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb fi igbi /tb/*
ṣiṣe 1000ns log /tb/* jade

Àfikún C—Ìdíwọ̀nBeere ibeere kan)

Àfikún yìí ṣapejuwe Awọn aṣẹ Awọn ihamọ Tcl ti Deri.
9.1 Gba Awọn ihamọ Tcl Awọn aṣẹ (Beere ibeere kan)
IwUlO derive_constraints ṣe iranlọwọ fun ọ lati gba awọn ihamọ lati RTL tabi atunto ni ita agbegbe apẹrẹ Libero SoC. Lati ṣe ipilẹṣẹ awọn idiwọ fun apẹrẹ rẹ, o nilo HDL olumulo, HDL paati, ati Awọn ihamọ paati files. Awọn ihamọ paati SDC files wa labẹ / paati / iṣẹ / / / liana lẹhin paati iṣeto ni ati iran.
Ihamọ paati kọọkan file oriširiši set_component tcl pipaṣẹ (pato awọn paati orukọ) ati awọn akojọ ti awọn inira ti ipilẹṣẹ lẹhin iṣeto ni. Awọn idiwọn ti wa ni ipilẹṣẹ ti o da lori iṣeto ati pe o wa ni pato si paati kọọkan.
Example 9-1. Ihamọ paati File fun PF_CCC mojuto
Eyi jẹ ẹya Mofiample ti a paati ihamọ file fun PF_CCC mojuto:
ṣeto_paati PF_CCC_C0_PF_CCC_C0_0_PF_CCC
# Microchip Corp.
# Ọjọ: 2021-Oṣu Kẹwa 26 04:36:00
# Aago mimọ fun PLL #0
create_clock -period 10 [ get_pins {pll_inst_0/REF_CLK_0} ] create_generated_clock -divide_by 1 -orisun [ get_pins { pll_inst_0/
REF_CLK_0 } ] -phase 0 [get_pins {pll_inst_0/OUT0} ] Nibi, create_clock ati create_generated_clock jẹ itọkasi ati awọn ihamọ aago ti o jade ni atele, eyiti o da lori iṣeto.
9.1.1 Nṣiṣẹ pẹlu IwUlO_constraints (Beere ibeere kan)
Awọn inira ti o kọja nipasẹ apẹrẹ ati pin awọn idiwọ tuntun fun apẹẹrẹ kọọkan ti paati ti o da lori paati SDC ti a pese tẹlẹ. files. Fun awọn aago itọkasi CCC, o tan kaakiri nipasẹ apẹrẹ lati wa orisun ti aago itọkasi. Ti orisun ba jẹ I/O, ihamọ aago itọkasi yoo ṣeto lori I/O. Ti o ba jẹ abajade CCC tabi orisun aago miiran (fun example, Transceiver, oscillator), o nlo aago lati awọn miiran paati ati ki o Ikilọ iroyin ti o ba ti awọn aaye arin ko baramu. Awọn ihamọ itọsẹ yoo tun pin awọn ihamọ fun diẹ ninu awọn macros bi awọn oscillators ori-chip ti o ba ni wọn ninu RTL rẹ.
Lati ṣiṣẹ ohun elo derive_constraints, o gbọdọ pese .tcl kan file ariyanjiyan laini aṣẹ pẹlu alaye atẹle ni aṣẹ ti a pato.

1. Pato alaye ẹrọ nipa lilo alaye ni apakan set_device.
2. Pato ọna si RTL files lilo alaye ni apakan read_verilog tabi read_vhdl.
3. Ṣeto module oke ni lilo alaye ni apakan set_top_level.
4. Pato ona si SDC paati files lilo alaye ni apakan read_sdc tabi read_ndc.
5. Ṣiṣe awọn files lilo alaye ni apakan derive_constraints.
6.  Pato ọna si awọn ihamọ ti ari SDC file lilo alaye ni apakan write_sdc tabi write_pdc tabi write_ndc.

Example 9-2. Ipaniyan ati Awọn akoonu ti itọsẹ.tcl File
Awọn atẹle jẹ ẹya example ariyanjiyan laini aṣẹ lati ṣiṣẹ ohun elo derive_constraints.
$ /bin{64}/derive_constraints derive.tcl
Awọn akoonu ti derive.tcl file:
# Alaye ẹrọ
set_device -ebi PolarFire -die MPF100T -iyara -1
# RTL files
read_verilog -mode system_verilog project/component/ise/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
read_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
read_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd}
# paati SDC files
ipele_top_level {xcvr1}
read_sdc - paati {project/component/work/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
read_sdc -paati {ise agbese/paati/ise/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
# Lo aṣẹ derive_constraint
deive_constraints
Abajade #SDC/PDC/NDC files
write_sdc {project/constraint/xcvr1_derived_constraints.sdc}
write_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 ẹrọ_eto (Beere ibeere kan)
Apejuwe
Pato orukọ idile, orukọ iku, ati ite iyara.
set_device - ebi -kú -iyara
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
-ebi	Okun	Pato orukọ idile naa. Awọn iye to ṣeeṣe jẹ PolarFire®, PolarFire SoC.
-kú	Okun	Pato orukọ kú.
-iyara	Okun	Pato ite iyara ẹrọ. Awọn iye to ṣeeṣe jẹ STD tabi -1.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0023	Paramita ti a beere — kú ti nsọnu	Aṣayan kú jẹ dandan ati pe o gbọdọ wa ni pato.
ERR0005	Aimọ iku 'MPF30'	Iye ti aṣayan -die ko pe. Wo atokọ ti o ṣeeṣe ti awọn iye ni apejuwe aṣayan.
ERR0023	Parameter — kú ti sonu iye	Aṣayan kú jẹ pato laisi iye.
ERR0023	Paramita ti a beere — idile nsọnu	Aṣayan ẹbi jẹ dandan ati pe o gbọdọ wa ni pato.
ERR0004	Idile aimọ 'PolarFire®'	Aṣayan ẹbi ko tọ. Wo atokọ ti o ṣeeṣe ti awọn iye ni apejuwe aṣayan.

………… tesiwaju
Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0023	Paramita-ẹbi nsọnu iye	Aṣayan ẹbi jẹ pato laisi iye.
ERR0023	Paramita ti a beere—iyara nsọnu	Aṣayan iyara jẹ dandan ati pe o gbọdọ wa ni pato.
ERR0007	Iyara aimọ' '	Aṣayan iyara ko tọ. Wo atokọ ti o ṣeeṣe ti awọn iye ni apejuwe aṣayan.
ERR0023	Paramita—iyara nsọnu iye	Aṣayan iyara ti wa ni pato laisi iye.

Example
set_device -ebi {PolarFire} -die {MPF300T_ES} -iyara -1
set_device -ebi SmartFusion 2 -die M2S090T -iyara -1
9.1.3 kika_verilog (Beere ibeere kan)
Apejuwe
Ka Verilog kan file lilo Verific.
read_verilog [-lib ] [-mode ]fileorukọ>
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
-lib	Okun	Pato ile-ikawe ti o ni awọn modulu lati ṣafikun sinu ile-ikawe naa.
-mode	Okun	Pato idiwọn Verilog. Awọn iye to ṣeeṣe jẹ verilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. Awọn iye jẹ ọran aibikita. Aiyipada jẹ verilog_2k.
fileoruko	Okun	Verilog file oruko.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0023	Paramita-lib ti nsọnu iye	Aṣayan lib ti wa ni pato laisi iye.
ERR0023	Paramita—ipo nsọnu iye	Aṣayan ipo ti wa ni pato laisi iye.
ERR0015	Ipo aimọ' '	Ipo verilog pàtó kan jẹ aimọ. Wo atokọ ti o ṣee ṣe ipo verilog ni-iṣapejuwe aṣayan ipo.
ERR0023	Ti beere paramita file orukọ ti nsọnu	Ko si verilog file ona ti pese.
ERR0016	Kuna nitori atupalẹ Verific	Aṣiṣe sintasi ni verilog file. Atọka Verific le ṣe akiyesi ni console loke ifiranṣẹ aṣiṣe naa.
ERR0012	set_device ko pe	Alaye ẹrọ ko ni pato. Lo pipaṣẹ set_device lati ṣapejuwe ẹrọ naa.

Example
read_verilog -mode system_verilog {component/work/top/top.v}
read_verilog -mode system_verilog_mfcu design.v
9.1.4 kika_vhdl (Beere ibeere kan)
Apejuwe
Fi VHDL kan kun file sinu atokọ ti VHDL files.
read_vhdl [-lib ] [-mode ]fileorukọ>
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
-lib	—	Pato ile-ikawe ninu eyiti a gbọdọ ṣafikun akoonu naa.
-mode	—	Ni pato VHDL bošewa. Aiyipada jẹ VHDL_93. Awọn iye to ṣeeṣe jẹ vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. Awọn iye jẹ ọran aibikita.
fileoruko	—	VHDL file oruko.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0023	Paramita-lib ti nsọnu iye	Aṣayan lib ti wa ni pato laisi iye.
ERR0023	Paramita—ipo nsọnu iye	Aṣayan ipo ti wa ni pato laisi iye.
ERR0018	Ipo aimọ' '	Ipo VHDL pato jẹ aimọ. Wo atokọ ti ipo VHDL ti o ṣeeṣe ni apejuwe aṣayan ipo.
ERR0023	Ti beere paramita file orukọ ti nsọnu	Ko si VHDL file ona ti pese.
ERR0019	Ko le forukọsilẹ invalid_path.v file	VHDL ti a pato file ko si tẹlẹ tabi ko ni awọn igbanilaaye kika.
ERR0012	set_device ko pe	Alaye ẹrọ ko ni pato. Lo pipaṣẹ set_device lati ṣapejuwe ẹrọ naa.

Example
read_vhdl -modus vhdl_2008 osc2dfn.vhd
read_vhdl {hdl/top.vhd}
9.1.5 ṣeto_oke_ipele (Beere ibeere kan)
Apejuwe
Pato orukọ module oke-ipele ni RTL.
set_top_level [-lib ]
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
-lib	Okun	Ile-ikawe lati wa module tabi nkan ti o ga julọ (Aṣayan).
oruko	Okun	Module oke-ipele tabi orukọ nkankan.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0023	Ti beere ipele oke paramita ti sonu	Aṣayan ipele oke jẹ dandan ati pe o gbọdọ wa ni pato.
ERR0023	Paramita-lib ti nsọnu iye	Aṣayan lib ti wa ni pato laisi awọn iye.
ERR0014	Ko le wa ipele oke ni ìkàwé	Awọn pàtó kan oke-ipele module ti ko ba telẹ ninu awọn ìkàwé pese. Lati ṣatunṣe aṣiṣe yii, module oke tabi orukọ ile-ikawe gbọdọ wa ni atunṣe.
ERR0017	Iṣe alaye kuna	Aṣiṣe ni ilana imudara RTL. Ifiranṣẹ aṣiṣe le ṣe akiyesi lati console.

Example
ipele_oke_ipele {oke}
set_top_level -lib HD oke
9.1.6 read_sdc (Beere ibeere kan)
Apejuwe
Ka SDC kan file sinu database paati.
read_sdc -paatifileorukọ>
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
- paati	—	Eyi jẹ asia ti o jẹ dandan fun aṣẹ read_sdc nigba ti a ba gba awọn ihamọ.
fileoruko	Okun	Ona si SDC file.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0023	Ti beere paramita file orukọ ti nsọnu.	Aṣayan dandan file orukọ ko pato.
ERR0000	SDC file <file_path> kii ṣe kika.	SDC pàtó kan file ko ni awọn igbanilaaye kika.
ERR0001	Ko le ṣiifile_ọna> file.	SDC naa file ko si. Ọna naa gbọdọ ṣe atunṣe.
ERR0008	Aṣẹ set_component sonu ninufile_ọna> file	Awọn pato paati SDC file ko pato paati.

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0009	<List of errors from sdc file>	SDC naa file ni awọn pipaṣẹ sdc ti ko tọ ninu. Fun example, nigbati aṣiṣe ba wa ni idiwọ set_multicycle_path: Aṣiṣe lakoko ṣiṣe pipaṣẹ read_sdc: nifile_ọna> file: Aṣiṣe ni pipaṣẹ set_multicycle_path: Aimọ paramita [get_cells {reg_a}].

Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 read_ndc (Beere ibeere kan)
Apejuwe
Ka NDC kan file sinu database paati.
read_ndc -paatifileorukọ>
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
- paati	—	Eyi jẹ asia ti o jẹ dandan fun aṣẹ read_ndc nigba ti a ba gba awọn ihamọ.
fileoruko	Okun	Ona si NDC file.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0001	Ko le ṣiifile_ọna> file	NDC naa file ko si. Ọna naa gbọdọ ṣe atunṣe.
ERR0023	Paramita ti a beere-AtclParamO_ nsọnu.	Aṣayan dandan fileorukọ ko pato.
ERR0023	Iparamita ti a beere — paati ti nsọnu.	Aṣayan paati jẹ dandan ati pe o gbọdọ wa ni pato.
ERR0000	NDC file 'file_path>' kii ṣe kika.	Awọn pàtó NDC file ko ni awọn igbanilaaye kika.

Example
read_ndc -paati {paati/work/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 deive_constraints (Beere ibeere kan)
Apejuwe
Ese paati SDC files sinu oniru-ipele database.
deive_constraints
Awọn ariyanjiyan

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0013	Oke-ipele ti ko ba telẹ	Eyi tumọ si pe module oke-ipele tabi nkankan ko ni pato. Lati ṣatunṣe ipe yii, gbejade aṣẹ set_top_level ṣaaju aṣẹ derive_constraints.

Example
deive_constraints
9.1.9 write_sdc (Beere ibeere kan)
Apejuwe
Kọ ihamọ kan file ni SDC kika.
kọ_sdcfileorukọ>
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
<fileorukọ>	Okun	Ona si SDC file yoo wa ni ipilẹṣẹ. Eyi jẹ aṣayan dandan. Ti o ba ti file tẹlẹ, o yoo wa ni kọ.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0003	Ko le ṣiifile ọna> file.	File ọna ko tọ. Ṣayẹwo boya awọn ilana obi wa.
ERR0002	SDC file 'file ọna>' kii ṣe kikọ.	SDC pàtó kan file ko ni igbanilaaye kikọ.
ERR0023	Ti beere paramita file orukọ ti nsọnu.	SDC naa file ona jẹ dandan aṣayan ati ki o gbọdọ wa ni pato.

Example
Kọ_sdc “derived.sdc”
9.1.10 write_pdc (Beere ibeere kan)
Apejuwe
Kọ awọn idiwọ ti ara (Awọn ihamọ ti a gba nikan).
kọ_pdcfileorukọ>
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
<fileorukọ>	Okun	Ona si PDC file yoo wa ni ipilẹṣẹ. Eyi jẹ aṣayan dandan. Ti o ba ti file ona wa, o yoo wa ni kọ.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Awọn ifiranṣẹ aṣiṣe	Apejuwe
ERR0003	Ko le ṣiifile ọna> file	Awọn file ọna ko tọ. Ṣayẹwo boya awọn ilana obi wa.
ERR0002	PDC file 'file ọna>' kii ṣe kikọ.	PDC ti a ti sọ tẹlẹ file ko ni igbanilaaye kikọ.
ERR0023	Ti beere paramita file orukọ ti nsọnu	PDC naa file ona jẹ dandan aṣayan ati ki o gbọdọ wa ni pato.

Example
write_pdc “ti ariwa.pdc”
9.1.11 write_ndc (Beere ibeere kan)
Apejuwe
Kọ NDC inira sinu kan file.
kọ_ndcfileorukọ>
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
fileoruko	Okun	Ona si NDC file yoo wa ni ipilẹṣẹ. Eyi jẹ aṣayan dandan. Ti o ba ti file tẹlẹ, o yoo wa ni kọ.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Awọn ifiranṣẹ aṣiṣe	Apejuwe
ERR0003	Ko le ṣiifile_ọna> file.	File ọna ko tọ. Awọn ilana obi ko si.
ERR0002	NDC file 'file_path>' kii ṣe kikọ.	Awọn pàtó NDC file ko ni igbanilaaye kikọ.
ERR0023	paramita ti a beere _AtclParamO_ sonu.	NDC naa file ona jẹ dandan aṣayan ati ki o gbọdọ wa ni pato.

Example
Kọ_ndc “ti ariwa.ndc”
9.1.12 add_include_path (Beere ibeere kan)
Apejuwe
Ntọka ọna kan si wiwa pẹlu files nigba kika RTL files.
add_include_ona
Awọn ariyanjiyan

Paramita	Iru	Apejuwe
liana	Okun	Ntọka ọna kan si wiwa pẹlu files nigba kika RTL files. Aṣayan yii jẹ dandan.

Pada Iru	Apejuwe
0	Aṣẹ ṣe aṣeyọri.

Pada Iru	Apejuwe
1	Aṣẹ kuna. Asise kan wa. O le ṣe akiyesi ifiranṣẹ aṣiṣe ninu console.

Akojọ ti awọn aṣiṣe

Koodu aṣiṣe	Ifiranṣẹ aṣiṣe	Apejuwe
ERR0023	Paramita ti a beere pẹlu ọna ti nsọnu.	Aṣayan itọsọna jẹ dandan ati pe o gbọdọ pese.

Akiyesi: Ti ọna itọsọna ko tọ, lẹhinna add_include_path yoo kọja laisi aṣiṣe kan.
Sibẹsibẹ, read_verilog/read_vhd pipaṣẹ yoo kuna nitori Verific's parser.
Example
add_include_path paati/iṣẹ/COREABC0/COREABC0_0/rtl/vlog/mojuto

Itan Atunyẹwo (Beere ibeere kan)

Itan atunyẹwo ṣe apejuwe awọn iyipada ti a ṣe imuse ninu iwe-ipamọ naa. Awọn iyipada ti wa ni atokọ nipasẹ atunyẹwo, bẹrẹ pẹlu atẹjade lọwọlọwọ julọ.

Àtúnyẹwò	Ọjọ	Apejuwe
F	08/2024	Awọn ayipada wọnyi ni a ṣe ninu atunyẹwo yii: • Abala ti a ṣe imudojuiwọn Àfikún B-Ṣiṣewọle Awọn ile-ikawe Simulation sinu Ayika Simulation.
E	08/2024	Awọn ayipada wọnyi ni a ṣe ninu atunyẹwo yii: • Imudojuiwọn apakan Loriview. Abala imudojuiwọn Ti ari SDC File. • Abala ti a ṣe imudojuiwọn Àfikún B-Ṣiṣewọle Awọn ile-ikawe Simulation sinu Ayika Simulation.
D	02/2024	Iwe yii jẹ idasilẹ pẹlu Libero 2024.1 SoC Design Suite laisi awọn ayipada lati v2023.2. Imudojuiwọn apakan Nṣiṣẹ pẹlu derive_constraints IwUlO
C	08/2023	Iwe yii jẹ idasilẹ pẹlu Libero 2023.2 SoC Design Suite laisi awọn ayipada lati v2023.1.
B	04/2023	Iwe yii jẹ idasilẹ pẹlu Libero 2023.1 SoC Design Suite laisi awọn ayipada lati v2022.3.
A	12/2022	Atunyẹwo akọkọ.

Microchip FPGA Support
Ẹgbẹ awọn ọja Microchip FPGA ṣe atilẹyin awọn ọja rẹ pẹlu ọpọlọpọ awọn iṣẹ atilẹyin, pẹlu Iṣẹ alabara, Ile-iṣẹ Atilẹyin Imọ-ẹrọ Onibara, a webojula, ati ni agbaye tita ifiweranṣẹ.
A daba awọn alabara lati ṣabẹwo si awọn orisun ori ayelujara Microchip ṣaaju kikan si atilẹyin nitori o ṣee ṣe pupọ pe awọn ibeere wọn ti ni idahun tẹlẹ.
Kan si Technical Support Center nipasẹ awọn webojula ni www.microchip.com/support. Darukọ nọmba Apakan Ẹrọ FPGA, yan ẹka ọran ti o yẹ, ati apẹrẹ ikojọpọ files lakoko ṣiṣẹda ọran atilẹyin imọ-ẹrọ.
Kan si Iṣẹ Onibara fun atilẹyin ọja ti kii ṣe imọ-ẹrọ, gẹgẹbi idiyele ọja, awọn iṣagbega ọja, alaye imudojuiwọn, ipo aṣẹ, ati aṣẹ.

• Lati North America, pe 800.262.1060
• Lati iyoku agbaye, pe 650.318.4460
• Faksi, lati nibikibi ninu aye, 650.318.8044

Microchip Alaye
Microchip naa Webojula
Microchip pese atilẹyin ori ayelujara nipasẹ wa webojula ni www.microchip.com/. Eyi webojula ti wa ni lo lati ṣe files ati alaye awọn iṣọrọ wa si awọn onibara. Diẹ ninu akoonu ti o wa pẹlu:

• Atilẹyin Ọja – Awọn iwe data ati errata, awọn akọsilẹ ohun elo ati sample eto, oniru oro, olumulo ká itọsọna ati hardware support awọn iwe aṣẹ, titun software tu ati ki o gbepamo software
• Atilẹyin Imọ-ẹrọ Gbogbogbo - Awọn ibeere ti a beere nigbagbogbo (Awọn FAQ), awọn ibeere atilẹyin imọ-ẹrọ, awọn ẹgbẹ ijiroro lori ayelujara, atokọ awọn ọmọ ẹgbẹ eto alabaṣepọ apẹrẹ Microchip
• Iṣowo ti Microchip - Aṣayan ọja ati awọn itọsọna aṣẹ, awọn idasilẹ atẹjade Microchip tuntun, atokọ ti awọn apejọ ati awọn iṣẹlẹ, awọn atokọ ti awọn ọfiisi tita Microchip, awọn olupin kaakiri ati awọn aṣoju ile-iṣẹ

Ọja Change iwifunni Service
Iṣẹ ifitonileti iyipada ọja Microchip ṣe iranlọwọ lati jẹ ki awọn alabara wa lọwọlọwọ lori awọn ọja Microchip. Awọn alabapin yoo gba ifitonileti imeeli nigbakugba ti awọn ayipada ba wa, awọn imudojuiwọn, awọn atunyẹwo tabi errata ti o ni ibatan si ẹbi ọja kan tabi ohun elo idagbasoke ti iwulo. Lati forukọsilẹ, lọ si www.microchip.com/pcn ki o si tẹle awọn ilana ìforúkọsílẹ.

Onibara Support
Awọn olumulo ti awọn ọja Microchip le gba iranlọwọ nipasẹ awọn ikanni pupọ:

• Olupin tabi Aṣoju
• Agbegbe Sales Office
• Onimọ-ẹrọ Awọn ojutu ti a fi sii (ESE)
• Oluranlowo lati tun nkan se

Awọn onibara yẹ ki o kan si olupin wọn, aṣoju tabi ESE fun atilẹyin. Awọn ọfiisi tita agbegbe tun wa lati ṣe iranlọwọ fun awọn alabara. Atokọ ti awọn ọfiisi tita ati awọn ipo wa ninu iwe yii. Imọ support wa nipasẹ awọn webojula ni: www.microchip.com/support
Ẹya Idaabobo koodu Awọn ẹrọ Microchip
Ṣe akiyesi awọn alaye atẹle ti ẹya aabo koodu lori awọn ọja Microchip:

• Awọn ọja Microchip pade awọn pato ti o wa ninu Iwe Data Microchip pato wọn.
• Microchip gbagbọ pe ẹbi ti awọn ọja wa ni aabo nigba lilo ni ọna ti a pinnu, laarin awọn pato iṣẹ, ati labẹ awọn ipo deede.
• Awọn iye Microchip ati ibinu ṣe aabo awọn ẹtọ ohun-ini ọgbọn rẹ. Awọn igbiyanju lati irufin awọn ẹya aabo koodu ti ọja Microchip jẹ eewọ muna ati pe o le rú Ofin Aṣẹ-lori Ẹgbẹrun Ọdun Digital.
• Bẹni Microchip tabi eyikeyi olupese semikondokito miiran le ṣe iṣeduro aabo koodu rẹ. Idaabobo koodu ko tumọ si pe a n ṣe iṣeduro ọja naa jẹ “aibikita”. Idaabobo koodu ti wa ni idagbasoke nigbagbogbo. Microchip ti pinnu lati ni ilọsiwaju nigbagbogbo awọn ẹya aabo koodu ti awọn ọja wa.

Ofin Akiyesi
Atẹjade yii ati alaye ti o wa ninu rẹ le ṣee lo pẹlu awọn ọja Microchip nikan, pẹlu lati ṣe apẹrẹ, idanwo, ati ṣepọ awọn ọja Microchip pẹlu ohun elo rẹ. Lilo alaye yii ni ọna miiran ti o lodi si awọn ofin wọnyi. Alaye nipa awọn ohun elo ẹrọ ti pese fun irọrun rẹ nikan ati pe o le rọpo nipasẹ awọn imudojuiwọn. O jẹ ojuṣe rẹ lati rii daju pe ohun elo rẹ ni ibamu pẹlu awọn pato rẹ. Kan si ọfiisi tita Microchip agbegbe rẹ fun atilẹyin afikun tabi, gba atilẹyin afikun ni www.microchip.com/en-us/support/design-help/client-support-services.
ALAYE YI NI MICROCHIP “BI O SE WA”. MICROCHIP KO SE Aṣoju TABI ATILẸYIN ỌJA TI IRU KANKAN BOYA KIAKIA TABI TỌRỌ, KỌ TABI ẹnu, Ilana tabi Bibẹkọkọ, ti o jọmọ ALAYE NAA SUGBON KO NI OPIN SI KANKAN, LATI IKILỌWỌ, LATI IKILỌWỌ, FUN IDI PATAKI, TABI ATILẸYIN ỌJA JẸRẸ SI IPO RẸ, DARA, TABI IṢẸ. LAISI iṣẹlẹ ti yoo ṣe oniduro fun eyikeyi aiṣedeede, PATAKI, ijiya, isẹlẹ, tabi ipadanu, bibajẹ, iye owo, tabi inawo, tabi inawo ti eyikeyi iru ohunkohun ti o jọmọ si awọn alaye tabi anfani, ti o ba ti lo, ED TI SEESE TABI AWỌN IBAJE AWỌN NIPA. SI AWỌN NIPA NIPA NIPA TI OFIN, LAPAPA LAPAPO MICROCHIP LORI Gbogbo awọn ẹtọ ni ọna eyikeyi ti o jọmọ ALAYE TABI LILO RE KO NI JU OPO ỌWỌ, TI O BA KAN, PE O TI SANWO NIPA TODAJU SIROMỌ.
Lilo awọn ẹrọ Microchip ni atilẹyin igbesi aye ati/tabi awọn ohun elo aabo jẹ patapata ni ewu olura, ati pe olura gba lati daabobo, ṣe idalẹbi ati mu Microchip ti ko lewu lati eyikeyi ati gbogbo awọn bibajẹ, awọn ipele, awọn ipele, tabi awọn inawo ti o waye lati iru lilo. Ko si awọn iwe-aṣẹ ti a gbe lọ, laisọtọ tabi bibẹẹkọ, labẹ eyikeyi awọn ẹtọ ohun-ini imọ Microchip ayafi bibẹẹkọ ti sọ.
Awọn aami-išowo
Orukọ Microchip ati aami, aami Microchip, Adaptec, AVR, AVR logo, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXSty MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, logo PIC32, PolarFire, Prochip Designer, QTouch, SAM-BA, Segenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ati XMEGA jẹ aami-išowo ti a forukọsilẹ ti Microchip Technology Incorporated ni AMẸRIKA ati awọn orilẹ-ede miiran.
AgileSwitch, ClockWorks, Ile-iṣẹ Awọn Solusan Iṣakoso ti a fi sinu, EtherSynch, Flashtec, Iṣakoso Iyara Hyper, fifuye HyperLight, Libero, motorBench, mTouch, Powermite 3, Edge Precision, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, ati ZL jẹ aami-išowo ti a forukọsilẹ ti Microchip Technology Incorporated ni AMẸRIKA
Imukuro Bọtini nitosi, AKS, Analog-fun-The-Digital Age, Eyikeyi Kapasito, AnyIn, AnyOut, Yipada Augmented, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM Average, Matching Nẹtiwọọki. , DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGAT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Asopọmọra, JitterBlocker, Knob-on-Display, MarginryLink, o pọjuView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB aami ifọwọsi, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PureSilicon , QMatrix, GIDI yinyin, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total ìfaradà , Akoko igbẹkẹle, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ati ZENA jẹ aami-iṣowo ti Microchip Technology Incorporated ni AMẸRIKA ati awọn orilẹ-ede miiran.
SQTP jẹ aami iṣẹ ti Microchip Technology Incorporated ni AMẸRIKA
Aami Adaptec, Igbohunsafẹfẹ lori Ibeere, Imọ-ẹrọ Ibi ipamọ Silicon, ati Symmcom jẹ aami-išowo ti a forukọsilẹ ti Microchip Technology Inc. ni awọn orilẹ-ede miiran.
GestIC jẹ aami-iṣowo ti a forukọsilẹ ti Microchip Technology Germany II GmbH & Co.KG, oniranlọwọ ti Microchip Technology Inc., ni awọn orilẹ-ede miiran.
Gbogbo awọn aami-iṣowo miiran ti a mẹnuba ninu rẹ jẹ ohun-ini ti awọn ile-iṣẹ wọn.
2024, Microchip Technology Incorporated ati awọn ẹka rẹ. Gbogbo awọn ẹtọ wa ni ipamọ.
ISBN: 978-1-6683-0183-8
Didara Management System
Fun alaye nipa Awọn ọna iṣakoso Didara Microchip, jọwọ ṣabẹwo www.microchip.com/quality.
Ni agbaye Titaja ati Service

AMERIKA	ASIA/PACIFIC	ASIA/PACIFIC	EUROPE
Ile-iṣẹ Ile-iṣẹ 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tẹli: 480-792-7200 Faksi: 480-792-7277 Oluranlowo lati tun nkan se: www.microchip.com/support Web Adirẹsi: www.microchip.com Atlanta Duluth, GA Tẹli: 678-957-9614 Faksi: 678-957-1455 Austin, TX Tẹli: 512-257-3370 Boston Westborough, MA Tẹli: 774-760-0087 Faksi: 774-760-0088 Chicago Itasca, IL Tẹli: 630-285-0071 Faksi: 630-285-0075 Dallas Addison, TX Tẹli: 972-818-7423 Faksi: 972-818-2924 Detroit Novi, MI Tẹli: 248-848-4000 Houston, TX Tẹli: 281-894-5983 Indianapolis Noblesville, INU Tẹli: 317-773-8323 Faksi: 317-773-5453 Tẹli: 317-536-2380 Los Angeles Mission Viejo, CA Tẹli: 949-462-9523 Faksi: 949-462-9608 Tẹli: 951-273-7800 Raleigh, NC Tẹli: 919-844-7510 Niu Yoki, NY Tẹli: 631-435-6000 San Jose, CA Tẹli: 408-735-9110 Tẹli: 408-436-4270 Canada – Toronto Tẹli: 905-695-1980 Faksi: 905-695-2078	Australia – Sydney Tẹli: 61-2-9868-6733 Ilu China - Ilu Beijing Tẹli: 86-10-8569-7000 China – Chengdu Tẹli: 86-28-8665-5511 China – Chongqing Tẹli: 86-23-8980-9588 China – Dongguan Tẹli: 86-769-8702-9880 China – Guangzhou Tẹli: 86-20-8755-8029 China – Hangzhou Tẹli: 86-571-8792-8115 China – Hong Kong SAR Tẹli: 852-2943-5100 China – Nanjing Tẹli: 86-25-8473-2460 China – Qingdao Tẹli: 86-532-8502-7355 China – Shanghai Tẹli: 86-21-3326-8000 China - Shenyang Tẹli: 86-24-2334-2829 China – Shenzhen Tẹli: 86-755-8864-2200 China – Suzhou Tẹli: 86-186-6233-1526 China – Wuhan Tẹli: 86-27-5980-5300 China – Xian Tẹli: 86-29-8833-7252 China – Xiamen Tẹli: 86-592-2388138 China – Zhuhai Tẹli: 86-756-3210040	India – Bangalore Tẹli: 91-80-3090-4444 India – New Delhi Tẹli: 91-11-4160-8631 India - Pune Tẹli: 91-20-4121-0141 Japan - Osaka Tẹli: 81-6-6152-7160 Japan – Tokyo Tẹli: 81-3-6880-3770 Koria – Daegu Tẹli: 82-53-744-4301 Korea – Seoul Tẹli: 82-2-554-7200 Malaysia – Kuala Lumpur Tẹli: 60-3-7651-7906 Malaysia - Penang Tẹli: 60-4-227-8870 Philippines – Manila Tẹli: 63-2-634-9065 Singapore Tẹli: 65-6334-8870 Taiwan – Hsin Chu Tẹli: 886-3-577-8366 Taiwan – Kaohsiung Tẹli: 886-7-213-7830 Taiwan – Taipei Tẹli: 886-2-2508-8600 Thailand - Bangkok Tẹli: 66-2-694-1351 Vietnam - Ho Chi Minh Tẹli: 84-28-5448-2100	Austria – Wels Tẹli: 43-7242-2244-39 Faksi: 43-7242-2244-393 Denmark – Copenhagen Tẹli: 45-4485-5910 Faksi: 45-4485-2829 Finland – Espoo Tẹli: 358-9-4520-820 Faranse - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Jẹmánì – Garching Tẹli: 49-8931-9700 Jẹmánì – Haan Tẹli: 49-2129-3766400 Jẹmánì – Heilbronn Tẹli: 49-7131-72400 Jẹmánì – Karlsruhe Tẹli: 49-721-625370 Jẹmánì – München Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Jẹmánì – Rosenheim Tẹli: 49-8031-354-560 Israeli - Hod Hasharon Tẹli: 972-9-775-5100 Italy – Milan Tẹli: 39-0331-742611 Faksi: 39-0331-466781 Italy – Padova Tẹli: 39-049-7625286 Netherlands - Drunen Tẹli: 31-416-690399 Faksi: 31-416-690340 Norway – Trondheim Tẹli: 47-72884388 Poland - Warsaw Tẹli: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain – Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden – Gothenberg Tel: 46-31-704-60-40 Sweden – Dubai Tẹli: 46-8-5090-4654 UK – Wokingham Tẹli: 44-118-921-5800 Faksi: 44-118-921-5820

Awọn iwe aṣẹ / Awọn orisun

MICROCHIP DS00004807F PolarFire Ìdílé FPGA Custom Sisan [pdf] Itọsọna olumulo DS00004807F PolarFire Ìdílé FPGA Aṣa Sisan, DS00004807F, PolarFire Idile FPGA Aṣa Sisan, Sisan Aṣa Aṣa FPGA, Sisan Aṣa, Sisan

Awọn itọkasi

• Itọsọna olumulo