PolarFire Family FPGA Custom Flow User Guide
Libero SoC v2024.2

Selelekela (Botsa Potso)

Software ea Libero System-on-Chip (SoC) e fana ka tikoloho ea moralo e kopantsoeng ka botlalo ea Field Programmable Gate Array (FPGA). Leha ho le joalo, basebelisi ba 'maloa ba kanna ba batla ho sebelisa lisebelisoa tsa mokha oa boraro le lisebelisoa tsa papiso kantle ho tikoloho ea Libero SoC. Libero joale e ka kopanngoa le tikoloho ea moralo oa FPGA. Ho khothaletsoa ho sebelisa Libero SoC ho tsamaisa phallo eohle ea moralo oa FPGA.
Tataiso ena ea mosebelisi e hlalosa Phallo e Tloaelehileng bakeng sa lisebelisoa tsa Lelapa la PolarFire le PolarFire SoC, mokhoa oa ho kopanya Libero e le karolo ea phallo e kholo ea moralo oa FPGA. Supported Device Families® Tafole e latelang e thathamisa malapa a lisebelisoa ao Libero SoC e a tšehetsang. Leha ho le joalo, lintlha tse ling tataisong ena li ka sebetsa feela ho sehlopha se itseng sa lisebelisoa. Tabeng ena, boitsebiso bo joalo bo tsejoa ka ho hlaka.
Letlapa la 1. Malapa a Lisebelisoa a Tšehetsoeng ke Libero SoC

Lelapa la Sesebelisoa	Tlhaloso
PolarFire®	Li-FPGA tsa PolarFire li fana ka matla a tlase a indasteri maemong a mahareng ka polokeho le ts'epo e ikhethang.
PolarFire SoC	PolarFire SoC ke SoC FPGA ea pele e nang le sehlopha sa deterministic, se lumellanang sa RISC-V CPU, le tsamaiso ea memori ea L2 e nolofalletsang Linux® le lisebelisoa tsa nako ea sebele.

Fetileview (Botsa Potso)

Le ha Libero SoC e fana ka tikoloho ea moralo oa pheletso e kopaneng ka botlalo ho nts'etsapele meralo ea SoC le FPGA, e boetse e fana ka maemo a bonolo a ho tsamaisa motsoako le papiso ka lisebelisoa tsa mokha oa boraro kantle ho tikoloho ea Libero SoC. Leha ho le joalo, mehato e meng ea moralo e tlameha ho lula ka har'a tikoloho ea Libero SoC.
Tafole e latelang e thathamisa mehato e meholo ho phallo ea moralo oa FPGA mme e bonts'a mehato eo Libero SoC e lokelang ho sebelisoa ho eona.
Lethathamo la 1-1. Phallo ea Moralo oa FPGA

Mohato oa Phallo ea Moralo	E tlameha ho sebelisa Libero	Tlhaloso
Moqapi oa Moqapi: HDL	Che	Sebelisa sesebelisoa sa mohlophisi/checker sa motho oa boraro sa HDL kantle ho Libero® SoC haeba u lakatsa.
Moqapi oa Moqapi: Li-Configurators	Ee	Theha projeke ea pele ea Libero bakeng sa tlhahiso ea karolo ea mantlha ea lethathamo la IP.
Ho hlahisa lithibelo tsa PDC/SDC ka boiketsetso	Che	Lithibelo tse nkiloeng li hloka HDL eohle files le derive_constraints utility ha e etsoa ka ntle ho Libero SoC, joalokaha ho hlalositsoe ho Sehlomathiso sa C—Derive Constraints.
Ketsiso	Che	Sebelisa sesebelisoa sa motho oa boraro kantle ho Libero SoC, haeba u lakatsa. E hloka ho khoasolla lilaebrari tse hlophisitsoeng esale pele bakeng sa sesebelisoa se shebiloeng, simulator e shebiloeng, le mofuta oa Libero o sebelisoang bakeng sa ts'ebetso ea morao-rao.
Synthesis	Che	Sebelisa sesebelisoa sa motho oa boraro kantle ho Libero SoC haeba u lakatsa.
Ts'ebetsong ea Moralo: Laola Litšitiso, Kopanya Netlist, Sebaka le Tsela (shebaview)	Ee	Theha morero oa bobeli oa Libero bakeng sa ts'ebetsong ea backend.
Nako le netefatso ea Matla	Ee	Lula morerong oa bobeli oa Libero.
Lokisa Lintlha tsa ho Qala Moralo le Mehopolo	Ee	Sebelisa sesebelisoa sena ho laola mefuta e fapaneng ea mehopolo le ho qala moralo sesebelisoa. Lula morerong oa bobeli.
Lenaneo File Moloko	Ee	Lula morerong oa bobeli.

Bohlokoa: Uena tlameha ho khoasolla lilaebrari tse hlophisitsoeng esale pele tse fumanehang ho Lilaebrari tsa Ketsiso tsa PreCompiled leqepheng la ho sebelisa simulator ea motho oa boraro.
Ka phallo e hloekileng ea Lesela la FPGA, kenya moralo oa hau u sebelisa HDL kapa keno ea moralo 'me u e fetise ka kotloloho
ho lisebelisoa tsa ho kopanya. Phallo e ntse e tšehetsoa. Li-FPGA tsa PolarFire le PolarFire SoC li na le bohlokoa
Li-block tsa IP tse thata tse hlokang ts'ebeliso ea li-cores (SgCores) ho tsoa ho Libero SoC IP.
lethathamo la libuka. Ho hlokahala ts'ebetso e khethehileng bakeng sa li-blocks tse nang le ts'ebetso ea SoC:

• PolarFire
  – PF_UPROM
  – PF_SYSTEM_SERVICES
  – PF_CCC
  - PF CLK DIV
  – PF_CRYPTO
  – PF_DRI
  – PF_INIT_MONITOR
  – PF_NGMUX
  – PF_OSC
  - Li-RAM (TPSRAM, DPSRAM, URAM)
  – PF_SRAM_AHBL_AXI
  – PF_XCVR_ERM
  – PF_XCVR_REF_CLK
  – PF_TX_PLL
  – PF_PCIE
  – PF_IO
  – PF_IOD_CDR
  – PF_IOD_CDR_CCC
  – PF_IOD_GENERIC_RX
  – PF_IOD_GENERIC_TX
  – PF_IOD_GENERIC_TX_CCC
  – PF_RGMII_TO_GMII
  – PF_IOD_OCTAL_DDR
  – PF_DDR3
  – PF_DDR4
  – PF_LPDDR3
  – PF_QDR
  – PF_CORESMARTBERT
  – PF_TAMPER
  – PF_TVS, joalo-joalo.

Ntle le li-SgCores tse thathamisitsoeng pele, ho na le li-IP tse ngata tse bonolo tsa DirectCore tse fumanehang bakeng sa malapa a lisebelisoa tsa PolarFire le PolarFire SoC ho Libero SoC Catalogue e sebelisang lisebelisoa tsa lesela la FPGA.
Bakeng sa ho kenngoa ha moralo, haeba u sebelisa e 'ngoe ea likarolo tse fetileng, u tlameha ho sebelisa Libero SoC bakeng sa karolo ea ho kenya moqapi (Component Configuration), empa u ka tsoela pele ka Moqapi oa hau (HDL, joalo-joalo) ka ntle ho Libero. Ho laola phallo ea moralo oa FPGA kantle ho Libero, latela mehato e fanoeng ho tataiso ena kaofela.
1.1 Karolo ea Bophelo ba potoloho (Botsa Potso)
Mehato e latelang e hlalosa potoloho ea bophelo ea karolo ea SoC mme e fana ka litaelo tsa ho sebetsana le data.

1. Hlahisa karolo u sebelisa configurator ea eona ho Libero SoC. Sena se hlahisa mefuta e latelang ea data:
   - HDL files
   – Sehopotso files
   - Khothatso le Ketsiso files
   – Karolo ea SDC file
2. Bakeng sa HDL files, li netefatse le ho li kopanya ho tse ling tsa moralo oa HDL u sebelisa sesebelisoa sa ho kenya moralo oa kantle.
3. Fana ka memori files le tshusumetso files ho sesebelisoa sa hau sa ketsiso.
4. Theko ea thepa SDC file ho Fumana sesebelisoa sa Constraint bakeng sa Constraint Generation. Sheba Sehlomathiso C—Derive Constraints bakeng sa lintlha tse ling.
5. O tlameha ho theha projeke ea bobeli ea Libero, moo o kenyang lethathamo la marang-rang la post-Synthesis le metadata ea karolo ea hau, ka hona o phethela khokahano lipakeng tsa seo o se hlahisitseng le seo o se hlophisang.

1.2 Tlhahiso ea Morero oa Libero SoC (Botsa Potso)
Mehato e meng ea moralo e tlameha ho tsamaisoa kahare ho tikoloho ea Libero SoC (Letlapa la 1-1). Hore mehato ena e sebetse, o tlameha ho theha merero e 'meli ea Libero SoC. Morero oa pele o sebelisetsoa tlhophiso ea likarolo tsa moralo le tlhahiso, 'me morero oa bobeli ke oa ho kenya tšebetsong moralo oa boemo bo holimo.
1.3 Phallo e Tloaelehileng (Botsa Potso)
Setšoantšo se latelang se bontša:

• Libero SoC e ka kopanngoa e le karolo ea phallo e kholo ea moralo oa FPGA le lisebelisoa tsa mokha oa boraro le lisebelisoa tsa papiso kantle ho tikoloho ea Libero SoC.
• Mehato e fapa-fapaneng e amehang phallong, ho qala ho tloha pōpong ea moralo le ho roka ho ea ho lenaneo la sesebelisoa.
• Phapanyetsano ea data (lintho le liphetho) tse tlamehang ho etsahala mohatong o mong le o mong oa phallo ea moralo.

Keletso:

1. SNVM.cfg, UROMM.cfg
2. *.mem file moloko bakeng sa Simulation: pa4rtupromgen.exe nka UPROM.cfg e le input le hlahisa UPROM.mem.

E latelang ke mehato ea phallo e tloaelehileng:

1. Tlhophiso le tlhahiso ea karolo:
   a. Theha projeke ea pele ea Libero (ho sebetsa joalo ka Morero oa Reference).
   b. Khetha Core ho Catalog. Tobetsa konopo habeli ho e fa karolo ea lebitso le ho lokisa karolo.
   Sena se romela kantle ho naha data ea karolo le files. A Component Manifests e boetse e hlahisoa. Sheba Lipontšo tsa Karolo bakeng sa lintlha. Bakeng sa lintlha tse ling, sheba Component Configuration.
2. Tlatsa moralo oa hau oa RTL kantle ho Libero:
   a. Kenya karolo ea HDL files.
   b. Sebaka sa HDL files e thathamisitsoe ho Component Manifests files.
3. Hlahisa lithibelo tsa SDC bakeng sa likarolo. Sebelisa lisebelisoa tsa Derive Constraints ho hlahisa tšitiso ea nako file(SDC) e ipapisitse le:
   a. Karolo ea HDL files
   b. Karolo ea SDC files
   c. HDL ea basebelisi files
   Bakeng sa lintlha tse ling, sheba Sehlomathiso C—Derive Constraints.
4. Sesebelisoa sa Synthesis / ketsiso:
   a. Fumana HDL files, tšusumetso files, le lintlha tsa likarolo tse tsoang libakeng tse ikhethileng joalo ka ha ho boletsoe ho Lipontšo tsa Karolo.
   b. Kopanya le ho etsisa moralo ka lisebelisoa tsa motho oa boraro kantle ho Libero SoC.
5. Theha morero oa hau oa bobeli (Tšebetsong) oa Libero.
6. Tlosa motsoako ho tswa ho ketane ea lisebelisoa tsa ho phalla (Project> Settings Project> Design Flow> hlakola lebokose la ho hlahloba la Enable Synthesis).
7. Kenya mohloli oa moralo files (post-synthesis *.vm netlist ho tsoa ho synthesis tool):
   - Kenya li-post-synthesis *.vm netlist (File>Import> Synthesized Verilog Netlist (VM)).
   – Metadata ea karolo *.cfg files bakeng sa uPROM le/kapa sNVM.
8. Kenya karolo efe kapa efe ea block ea Libero SoC files. The block files e tlameha ho ba ho *.cxz file sebopeho.
   Bakeng sa tlhaiso-leseling e batsi mabapi le mokhoa oa ho theha block, bona PolarFire Block Flow User Guide.
9. Kenya litšitiso tsa moralo:
   - Thibelo ea ho kenya I/O kantle ho naha files (Motsamaisi oa Litšitiso > I/OAttributes > Reka).
   – Reka moralo oa fatše *.pdc files (Motsamaisi oa Lithibelo> Floor Planner> Ho lata).
   – Theha *.sdc thibelo ea nako files (Motsamaisi oa Lithibelo> Nako > Ho Romela). Ho tsoa kantle ho naha ea SDC file e hlahisoa ka sesebelisoa sa Derive Constraint.
   – Theha *.ndc thibelo files (Constraints Manager > NetlistAttributes > Import), haeba e teng.
10. Tšitiso file le mokhatlo oa lisebelisoa
    – Ho Constraint Manager, amahanya le *.pdc files ho beha le tsela, *.sdc files ho beha le litsela le netefatso ea nako, le *.ndc files ho Kopanya Netlist.
11. Phetha ts'ebetsong ea moralo
    - Sebaka le tsela, netefatsa nako le matla, hlophisa lintlha le mehopolo ea ho qala moralo, le mananeo file moloko.
12. Netefatsa moralo
    - Netefatsa moralo ho FPGA le ho lokisa liphoso ha ho hlokahala u sebelisa lisebelisoa tsa moralo tse fanoeng ka suite ea moralo oa Libero SoC.

Tlhophiso ea Karolo (Botsa Potso)

Mohato oa pele oa phallo ea moetlo ke ho hlophisa likarolo tsa hau u sebelisa projeke ea litšupiso ea Libero (eo hape e bitsoang projeke ea pele ea Libero ho Lethathamo la 1-1). Mehatong e latelang, o sebelisa lintlha tse tsoang morerong ona oa litšupiso.
Haeba u sebelisa likarolo life kapa life tse thathamisitsoeng pejana, tlasa Overview moralong oa hau, etsa mehato e hlalositsoeng karolong ena.
Haeba u sa sebelise leha e le efe ea likarolo tse ka holimo, u ka ngola RTL ea hau ka ntle ho Libero 'me ua e kenya ka ho toba lisebelisoa tsa hau tsa Synthesis le Simulation. Joale o ka tsoela pele ho karolo ea post-synthesis mme o kenya feela post-synthesis *.vm netlist ho morero oa hau oa ho qetela oa ts'ebetsong oa Libero (hape o bitsoa morero oa bobeli oa Libero ho Lethathamo la 1-1).
2.1 Tlhophiso ea Karolo e Sebelisang Libero (Botsa Potso)
Kamora ho khetha likarolo tse lokelang ho sebelisoa lethathamong le fetileng, etsa mehato e latelang:

1. Theha morero o mocha oa Libero (Core Configuration le Generation): Khetha Sesebelisoa le Lelapa leo u lebileng moralo oa hau oa ho qetela ho lona.
2. Sebelisa e le 'ngoe kapa tse ngata tsa li-cores tse boletsoeng ho Custom Flow.
   a. Theha SmartDesign 'me u lokise motheo o lakatsehang' me u e kenye karolong ea SmartDesign.
   b. Phahamisa lipini tsohle ho ea maemong a holimo.
   c. Hlahisa SmartDesign.
   d. Tobetsa habeli sesebelisoa sa Simulate (leha e le efe ea likhetho tsa Pre-Synthesis kapa Post-Synthesis kapa Post-Layout) ho kopa simulator. U ka tsoa ho simulator ka mor'a hore e kopitsoe. Mohato ona o hlahisa ketsiso filee hlokahalang bakeng sa morero oa hau.

Keletso: Uena o tlameha ho etsa mohato ona haeba o batla ho etsisa moralo oa hau kantle ho Libero.
Ho fumana lintlha tse ling, sheba Ho etsisa Moralo oa Hao.
e. Boloka projeke ea hau — ena ke projeke ea hau ea litšupiso.
2.2 Lipontšo tsa likarolo (Botsa Potso)
Ha o hlahisa likarolo tsa hau, sehlopha sa files e hlahisoa bakeng sa karolo ka 'ngoe. Tlaleho ea Component Manifest e qaqisa sete ea files e hlahisoang le ho sebelisoa mohatong o mong le o mong o latelang (Synthesis, Simulation, Firmware Generation, joalo-joalo). Tlaleho ena e u fa libaka tsa tsohle tse hlahisitsoeng files e hlokahalang ho tsoela pele ka Custom Flow. O ka fihlella karolo ea manifesto sebakeng sa Litlaleho: Tobetsa Moralo > Litlaleho ho bula tab ea Litlaleho. Ka har'a tab ea Litlaleho, u bona sehlopha sa manifest.txt files (Ho fetaview), e le 'ngoe bakeng sa karolo e' ngoe le e 'ngoe eo u e hlahisitseng.
Keletso: O tlameha ho seta karolo kapa mojule joalo ka '”root”' ho bona karolo e hlahang file dikahare ho tab ya Litlaleho.
Ntle le moo, o ka fihlella tlaleho ea motho ka mong files bakeng sa karolo ka 'ngoe ea mantlha e hlahisoang kapa karolo ea SmartDesign ho tsoa ho /karolo/mosebetsi/ / / _manifest.txt kapa /karolo/mosebetsi/ / _manifest.txt. U ka boela ua kena ho manifest file litaba tsa karolo e 'ngoe le e' ngoe e hlahisoang ho tsoa ho tab e ncha ea Likahare ho Libero, moo file libaka li boleloa mabapi le bukana ea morero.Tsepamisa maikutlo litlalehong tse latelang tsa Component Manifest:

• Haeba u kentse li-cores ho SmartDesign, bala faele ea file _manifest.txt.
• Haeba u thehile likarolo tsa li-cores, bala lintlha tsa _manifest.txt.

U tlameha ho sebelisa litlaleho tsohle tsa Component Manifest tse sebetsang moahong oa hau. Bakeng sa mohlalaample, haeba projeke ea hau e na le SmartDesign e nang le karolo e le 'ngoe kapa ho feta ea mantlha e kentsoeng ho eona mme u ikemiselitse ho e sebelisa kaofela moralong oa hau oa ho qetela, o tlameha ho khetha. files tse thathamisitsoeng litlalehong tsa Component Manifests tsa likarolo tseo kaofela hore li sebelisoe molemong oa phallo ea moralo oa hau.
2.3 Ho Hlalosa Ponahatso FilesBotsa Potso)
Ha o bula karolo e bonts'ang file, u bona litsela tsa ho files morerong oa hau oa Libero le litsupa tsa hore na moralo o phalla hokae ho li sebelisa. U ka bona mefuta e latelang ea files ka ponahalo file:

• Mohloli oa HDL files bakeng sa lisebelisoa tsohle tsa Synthesis le Simulation
• Khothatso files bakeng sa lisebelisoa tsohle tsa Simulation
• Tšitiso files

Se latelang ke Karolo ea Manifest ea karolo ea mantlha ea PolarFire.Mofuta o mong le o mong oa file hoa hlokahala ho theosa le molapo ho phallo ea hau ea moralo. Likarolo tse latelang li hlalosa kopanyo ea files ho tloha ponahatsong ho kena ho phallo ea hau ea moralo.

Constraint Generation (Botsa Potso)

Ha o etsa tlhophiso le tlhahiso, etsa bonnete ba ho ngola / ho hlahisa lithibelo tsa SDC/PDC/NDC files hore moralo o li fetisetse ho Synthesis, Place-and-Route, le Netefatsa lisebelisoa tsa Nako.
Sebelisa lisebelisoa tsa Derive Constraints ka ntle ho tikoloho ea Libero ho hlahisa litšitiso ho e-na le ho li ngola ka letsoho. Ho sebelisa sesebelisoa sa Derive Constraint kantle ho tikoloho ea Libero, o tlameha ho:

• Fana ka HDL ea basebelisi, karolo ea HDL, le karolo ea SDC e thibelang files
• Hlalosa mojule oa boemo bo holimo
• Hlalosa sebaka moo ho ka hlahisoang tšitiso e nkiloeng files

Lithibelo tsa karolo ea SDC li fumaneha tlasa /karolo/mosebetsi/ / / directory ka mor'a tlhophiso ea karolo le tlhahiso.
Bakeng sa lintlha tse ling mabapi le mokhoa oa ho hlahisa litšitiso bakeng sa moralo oa hau, bona Sehlomathiso C—Derive Constraints.

Ho kopanya Moralo oa Hao (Botsa Potso)

E 'ngoe ea likarolo tsa mantlha tsa Custom Flow ke ho u lumella ho sebelisa motsoako oa motho oa boraro
sesebelisoa ka ntle ho Libero. Phallo e tloaelehileng e tšehetsa tšebeliso ea Synopsys SynplifyPro. Ho synthesize hao
morero, sebelisa mokhoa o latelang:

1. Theha projeke e ncha ho sesebelisoa sa hau sa Synthesis, u tobane le lelapa le le leng la sesebelisoa, ho shoa, le sephutheloana joalo ka projeke ea Libero eo u e thehileng.
   a. Kenya RTL ea hau files joalo ka ha u tloaetse ho etsa.
   b. Beha tlhahiso ea Synthesis hore e be Structural Verilog (.vm).
   Keletso: Sebopeho Verilog (.vm) ke eona feela e tšehetsoeng ke sebopeho sa tlhahiso ea motsoako ho PolarFire.
2. Kenya Karolo ea HDL files ho morero oa hau oa Synthesis:
   a. Bakeng sa Tlaleho e 'ngoe le e 'ngoe ea Manifests ea Karolo: Bakeng sa e 'ngoe le e 'ngoe file tlas'a mohloli oa HDL files bakeng sa lisebelisoa tsohle tsa Synthesis le Simulation, kenya thepa ea file ho Morero oa hau oa Synthesis.
3. Kenya thepa ea ka ntle file polarfire_syn_comps.v (haeba o sebelisa Synopsys Synplify) ho tloha
   Sebaka sa ho kenya>/data/aPA5M morerong oa hau oa Synthesis.
4. Reka SDC e entsweng pele file ka sesebelisoa sa Derived Constraint (sheba Sehlomathiso
   A—Sample SDC Constraints) ho sesebelisoa sa Synthesis. Thibelo ena file e thibela sesebelisoa sa ho kopanya ho fihlela ho koaloa ha nako ka boiteko bo fokolang le ho fokotseha ho fokolang ha moralo.

Bohlokoa: 

• Haeba u rera ho sebelisa e tšoanang *.sdc file ho qobella Sebaka-le-Tsela nakong ea mohato oa ts'ebetsong ea moralo, o tlameha ho kenya *.sdc ena morerong oa ho kopanya. Sena ke ho etsa bonnete ba hore ha ho na lebitso la moralo le sa lumellaneng lethathamong la marang-rang le kopaneng le lithibelo tsa Sebaka le Tsela nakong ea ts'ebetso ea ts'ebetso ea moralo. Haeba u sa kenyelle *.sdc ena file mohatong oa Synthesis, lenane la marang-rang le hlahisitsoeng ho tsoa ho Synthesis le ka hloleha mohato oa Sebaka le Tsela ka lebaka la ho se lumellane ha lebitso la ntho.
  a. Kenya Netlist Attributes *.ndc, haeba e teng, ho sesebelisoa sa Synthesis.
  b. Matha Synthesis.
• Sebaka sa tlhahiso ea sesebelisoa sa Synthesis se na le *.vm netlist file tlhahiso ea poso Synthesis. U tlameha ho kenya lenane la marang-rang ho Morero oa Ts'ebetsong oa Libero ho tsoela pele ka ts'ebetso ea meralo.

Ho etsisa Moralo oa Hao (Botsa Potso)

Ho etsisa moralo oa hau kantle ho Libero (ke hore, ho sebelisa tikoloho ea hau ea papiso le simulator), etsa mehato e latelang:

1. Moralo Files:
   a. Ketsiso ea Pre-Synthesis:
   • Kenya RTL ya hao morerong wa hao wa ketsiso.
   • Bakeng sa Karolo ka 'ngoe ea Tlaleho ea Manifest.
   – Kenya e nngwe le e nngwe file tlas'a mohloli oa HDL files bakeng sa lisebelisoa tsohle tsa Synthesis le Simulation morerong oa hau oa papiso.
   • Kopanya tsena files ho latela litaelo tsa simulator ea hau.
   b. Ketsiso ea Post-synthesis:
   • Kenya post-synthesis *.vm netlist (e hlahisitsoeng ho Synthesizing Your Design) morerong oa hau oa ketsiso le ho e bokella.
   c. Ketsiso ea morao-rao:
   • Ntlha ea pele, tlatsa moralo oa hau (sheba Ho Kenyelletsa Moralo oa Hao). Netefatsa hore projeke ea hau ea ho qetela ea Libero e maemong a morao-rao.
   • Penya habeli Hlahisa BackAnnotated Files fensetereng ea Libero Design Flow. E hlahisa tse peli files:
   /moqapi/ / _ba.v/vhd /moqapi/
   / _ba.sdf
   • Reka tsena ka bobeli files ho sesebelisoa sa hau sa ketsiso.
2. Khothatso le Tlhophiso files:
   a. Bakeng sa Karolo ka 'ngoe ea Tlaleho ea Manifest:
   • Kopitsa kaofela files tlas'a Tšusumetso Files bakeng sa likarolo tsohle tsa Simulation Tools ho mohloli oa mohloli oa morero oa hau oa Simulation.
   b. Etsa bonnete ba hore Tcl efe kapa efe files lethathamong le tlang pele (mohatong oa 2.a) li etsoa pele, pele ho qalisoa ha papiso.
   c. UUPROM.mem: Haeba u sebelisa motheo oa UPROM moralong oa hau ka khetho Sebelisa dikahare bakeng sa papiso e nolofalitsoeng bakeng sa moreki a le mong kapa ba bangata ba polokelo ea data eo u lakatsang ho e etsisa, o tlameha ho sebelisa pa4rtupromgen e phethisoang (pa4rtupromgen.exe lifensetereng) ho hlahisa UPROM.mem file. Pa4rtupromgen e phethisoang e nka UPROM.cfg file joalo ka litlatsetso ka script ea Tcl file mme e hlahisa UROMM.mem file e hlokahalang bakeng sa ketsiso. Sena ke UROM.mem file e tlameha ho kopitsoa foldareng ea papiso pele ho ts'ebetso ea papiso. ExampLe e bonts'ang ts'ebeliso ea ts'ebeliso ea pa4rtupromgen e fanoe ka mehato e latelang. The UROM.cfg file e fumaneha bukeng /karolo/mosebetsi/ / morerong oa Libero oo u o sebelisitseng ho hlahisa karolo ea UPROM.
   d. snvm.mem: Haeba u sebelisa motheo oa Litšebeletso tsa Sistimi moralong oa hau 'me u lokiselitse tabo ea sNVM ka har'a mantlha ka khetho Sebelisa litaba bakeng sa papiso e lumelletsoeng bakeng sa moreki a le mong kapa ho feta eo u lakatsang ho e etsisa, snvm.mem file e hlahisoa ka tsela e iketsang ho
   directory /karolo/mosebetsi/ / morerong oa Libero oo u o sebelisitseng ho hlahisa karolo ea Litšebeletso tsa Sistimi. Sena snvm.mem file e tlameha ho kopitsoa foldareng ea papiso pele ho ts'ebetso ea papiso.
3. Theha foldara e sebetsang le foldara e nyane e bitsoang simulation tlasa foldara e sebetsang.
   Pa4rtupromgen e phethisoang e lebella ho ba teng ha foldara e nyane ea ketsiso foldareng e sebetsang mme * .tcl script e behiloe ka har'a foldara e nyane ea ketsiso.
4. Kopitsa faele ea UROMM.cfg file ho tloha morerong oa pele oa Libero o entsoeng bakeng sa tlhahiso ea likarolo ho foldareng e sebetsang.
5. Beha litaelo tse latelang ho *.tcl script 'me ue behe foldareng ea papiso e entsoeng mohatong oa 3.
   Sample *.tcl bakeng sa lisebelisoa tsa PolarFire le PolarFire Soc Family ho hlahisa URPOM.mem file
   ho tsoa ho UROM.cfg
   set_device -fam - shoa -pkg
   set_input_cfg -tsela
   set_sim_mem -tselaFile/UPROM.mem>
   gen_sim -use_init bohata
   Bakeng sa lebitso le nepahetseng la ka hare le ka sebelisoang bakeng sa die le sephutheloana, bona *.prjx file ea morero oa pele oa Libero (o sebelisetsoang ho hlahisa likarolo).
   Khang use_init e tlameha ho hlophisoa ho ba bohata.
   Sebelisa set_sim_mem taelo ho hlakisa tsela ea tlhahiso file UPROM.mem ke hore
   e hlahisoang ha ho etsoa script file ka pa4rtupromgen e ka phethahatsoang.
6. Ka taelo ea kapele kapa terminal ea cygwin, e-ea bukeng ea ho sebetsa e entsoeng mohatong oa 3.
   Phetha taelo ea pa4rtupromgen ka khetho ea-script 'me u fetisetse ho eona *.tcl script e entsoeng mohatong o fetileng.
   Bakeng sa Windows
   /designer/bin/pa4rtupromgen.exe
   –script./simulation/ .tcl
   Bakeng sa Linux:
   /bin/pa4rtupromgen
   –script./simulation/ .tcl
7. Kamora ho sebetsa ka katleho ha pa4rtupromgen e ka phethisoang, hlahloba hore na UPROM.mem file e hlahisoa sebakeng se boletsoeng taelong ea set_sim_mem ho *.tcl script.
8. Ho etsisa sNVM, kopitsa faele ea snvm.mem file ho tsoa ho projeke ea hau ea pele ea Libero (e sebelisetsoang tlhophiso ea likarolo) ho foldara ea boemo bo holimo ea ketsiso ea projeke ea hau ea papiso ho tsamaisa papiso (kantle ho Libero SoC). Ho etsisa litaba tsa UROM, kopitsa UROMM.mem e entsoeng file ka har'a foldara ea boemo bo holimo ea ketsiso ea projeke ea hau ea ho etsa papiso (kantle ho Libero SoC).

Bohlokoa: Ho etsisa ts'ebetso ea SoC Components, khoasolla lilaebrari tse hlophisitsoeng esale pele tsa PolarFire 'me u li kenye sebakeng sa hau sa papiso joalo ka ha ho hlalositsoe mona. Bakeng sa lintlha tse ling, bona Sehlomathiso sa B—Ho Importing Lilaebrari tsa Ketsiso ho Tikoloho ea Ketsiso.

Ho phethahatsa Moralo oa Hao (Botsa Potso)

Kamora ho qeta papiso ea Synthesis le Post-Synthesis tikolohong ea hau, o tlameha ho sebelisa Libero hape ho kenya tšebetsong moralo oa hau, ho tsamaisa nako le tlhahlobo ea matla, le ho hlahisa mananeo a hau. file.

1. Theha morero o mocha oa Libero bakeng sa ts'ebetsong ea 'mele le moralo oa moralo. Netefatsa hore o shebisisa sesebelisoa se ts'oanang le projeke ea litšupiso eo u e entseng ho Component Configuration.
2. Ka mor'a ho theha morero, tlosa Synthesis ho tswa ho ketane ea lisebelisoa fensetereng ea Phallo ea Moralo (Projeke> Litlhophiso tsa Morero> Phallo ea Moralo> Tlosa Cheka Enable Synthesis).
3.  Kenya tlhahiso ea hau ea morao-rao *.vm file morerong ona, (File > Theha > Synthesized Verilog Netlist (VM)).
   Keletso: Ho kgothaletswa hore o thehe sehokelo ho sena file, e le hore haeba u tsosolosa moralo oa hau, Libero e lula e sebelisa lethathamo la morao-rao la post-synthesis.
   a. Fensetereng ea Hierarchy ea Moralo, hlokomela lebitso la mojule oa motso.
4. Kenya litšitiso ho projeke ea Libero. Sebelisa Constraint Manager ho kenya *.pdc/*.sdc/*.ndc lithibelo.
   a. Kenya I/O *.pdc contraindication files (Motsamaisi oa Lithibelo> Litšobotsi tsa I/O> Ho kenya).
   b. Kenya Floorplanning *.pdc constraint files (Motsamaisi oa Lithibelo> Floor Planner > Import).
   c. Kenya *.sdc thibelo ea nako files (Motsamaisi wa Dithibelo > Nako > Reka). Haeba moralo oa hau o na le li-cores tse thathamisitsoeng ho Overview, etsa bonnete ba ho kenya SDC kantle ho naha file e entsoeng ka sesebelisoa sa derive constraint.
   d. Kenya *.ndc thibelo files (Motsamaisi oa Litšitiso > Litšoaneleho tsa Netlist > Kena).
5. Kopanya Litšitiso Files ho rala lisebelisoa.
   a. Open Constraint Manager (Laola Lithibelo> Bula Lithibelo tsa Laola View).
   Sheba lebokose la ho hlahloba la Sebaka-le-Tsela le Tiiso ea Nako haufi le thibelo file ho theha tšitiso file le mokhatlo oa lisebelisoa. Amahanya *.pdc thibelo ho Place-andRoute le *.sdc ho bobeli ba Sebaka-le-Tsela le Tiiso ea Nako. Amahanya le *.ndc file ho Kopanya Netlist.
   Keletso: Haeba Sebaka le Route ha li atlehe ka *.sdc contraindications file, ebe u kenya eona *.sdc file ho kopanya le ho tsamaisa bocha.
6. Tobetsa Kopanya Netlist ebe o Beha le Tsela ho phethela mohato oa moralo.
7. Sesebelisoa sa Configure Design Initialization Data le Memories se u lumella ho qala li-block tsa meralo, joalo ka LSRAM, µSRAM, XCVR (transceivers), le PCIe u sebelisa data e bolokiloeng ho µPROM, sNVM, kapa memori ea kantle ea SPI Flash. Sesebelisoa se na le li-tab tse latelang bakeng sa ho hlalosa tlhaloso ea tatellano ea ho qalisoa ha moralo, litlhaloso tsa bareki ba ho qala, bareki ba data ea basebelisi.
   - Taba ea ho qala moralo
   – µPROM tab
   - sNVM tab
   - Taba ea SPI Flash
   - Taba ea li-RAM tsa masela
   Sebelisa li-tab tse ka har'a sesebelisoa ho hlophisa lintlha le mehopolo ea ho qala moralo.Kamora ho qeta tlhophiso, etsa mehato e latelang ho hlophisa data ea ho qala:
   • Hlahisa bareki ba ho qala
   • Hlahisa kapa ho romela kantle ho bitstream
   • Lenaneo la sesebelisoa
   Bakeng sa lintlha tse qaqileng mabapi le mokhoa oa ho sebelisa sesebelisoa sena, bona Libero SoC Design Flow User Guide. Bakeng sa tlhaiso-leseling e batsi mabapi le litaelo tsa Tcl tse sebelisoang ho hlophisa li-tab tse fapaneng sesebelisoa le ho hlakisa tlhophiso ea memori. files (*.cfg), bona Tcl Commands Reference Guide.
8. Hlahisa Lenaneo File ho tsoa projekeng ena 'me u e sebelise ho hlophisa FPGA ea hau.

Sehlomathiso A—SampLe SDC Constraints (Botsa Potso

Libero SoC e hlahisa lithibelo tsa nako ea SDC bakeng sa li-cores tse ling tsa IP, tse kang CCC, OSC, Transceiver joalo-joalo. Ho fetisa litšitiso tsa SDC ho etsa lisebelisoa ho eketsa monyetla oa ho koala nako ka boiteko bo fokolang le ho fokotseha ho fokolang ha moralo. Tsela e felletseng ea maemo a holimo ho tsoa maemong a holimo e fanoe bakeng sa lintho tsohle tsa moralo tse boletsoeng ho lithibelo.
7.1 Litšitiso tsa Nako ea SDC (Botsa Potso)
Morerong oa litšupiso oa mantlha oa Libero IP, tšitiso ena ea boemo bo holimo ea SDC file e fumaneha ho tswa ho Constraint Manager (Morero Phallo> Open Laola Constraint View > Nako > Fumana Ditshitiso).
Bohlokoa: Bona sena file ho beha lithibelo tsa SDC haeba moralo oa hau o na le CCC, OSC, Transceiver, le likarolo tse ling. Fetola tsela e felletseng ea maemo, ha ho hlokahala, ho tsamaisana le maemo a moralo oa hau kapa sebelisa ts'ebeliso ea Derive_Constraints le mehato e ho Sehlomathiso C—Derive Constraints boemong ba karolo ea SDC. file.
Boloka the file ho lebitso le fapaneng le ho reka kantle ho naha SDC file ho sesebelisoa sa ho kopanya, Sesebelisoa sa Sebaka le Tsela, le Litiiso tsa Nako, joalo ka lithibelo tse ling tsa SDC. files.
7.1.1 SDC e nkiloeng File (Botsa Potso)
#Sena file e entsoe ho latela mohloli o latelang oa SDC files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
TRANSMIT_PLL/TRANSMIT_PLL_0/TRANSMIT_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PCIE_INITIATOR/PCIE_INITIATOR_0/PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** Liphetoho life kapa life ho sena file e tla lahleha haeba lithibelo tse nkiloeng li phethiloe hape. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} -nako ea 6.25
[ fumana_phini { CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } ] create_clock -name {REF_CLK_PAD_P} -nako 10 [ get_ports { REF_CLK_PAD_P } ] create_clock -name {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_ist_PLL/TRANSMIT_is_PLL
DIV_CLK} -nako ea 8
[ get_pins { CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CCp_CLK_CLK_CLK_CLL_0_CLL_0
OUT0} -katisetsa_ka 25 -arola_ka 32 -mohloli
[ fumana_phini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -mohato 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_CLL_Cll_0CLL_CLL_0
OUT1} -katisetsa_ka 25 -arola_ka 32 -mohloli
[ fumana_phini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -mohato 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_CLL_Cll_0CLL_CLL_0
OUT2} -katisetsa_ka 25 -arola_ka 32 -mohloli
[ fumana_phini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -mohato 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_CLL_Cll_0CLL_CLL_0
OUT3} -katisetsa_ka 25 -arola_ka 64 -mohloli
[ fumana_phini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -mohato 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_80MHz/CLK_CD_0CD_XNUMX
Y_DIV} -arola_ka 2 -mohloli
[ fumana_phini { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CLK_DIV_0/I_CD/A } ] [ fumana_phini { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/DIV_CD_CD_CD_CD_CD_CD set_false_path -through [ get_nets { DMA_INITIATOR_inst_0/ARESETN* } ] set_false_path -from [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray* } ] -ho [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1* } ] set_false_path -ho tloha [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray* } ] -ho [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1* } ] set_false_path -through [ get_nets { FIC0_INITIATOR_inst_0/ARESETN* } ] set_false_path -ho [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[0] PCIE/PCIE/PF_0PF_0
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/PCIE_1/MPERST_N } ] set_false_path -from [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/TL_CLK } ] set_false_path -through [get_stNTIATOR/PCIE] Sehlomathiso B—Ho Kenya Lilaebrari tsa Ketsiso ho Tikoloho ea Ketsiso (Botsa Potso)
Simulator ea kamehla bakeng sa papiso ea RTL le Libero SoC ke ModelSim ME Pro.
Lilaebrari tse hlophisitsoeng esale pele bakeng sa simulator ea kamehla lia fumaneha ka ho kenya Libero bukeng ea libuka /Designer/lib/modelsimpro/precompiled/vlog for® malapa a tšehetsoeng. Libero SoC e boetse e ts'ehetsa likhatiso tse ling tsa mokha oa boraro oa ModelSim, Questasim, VCS, Xcelium.
, HDL e sebetsang, le Riviera Pro. Khoasolla lilaebrari tse hlophisitsoeng esale pele ho tsoa ho Libero SoC v12.0 le hamorao e ipapisitse le simulator le mofuta oa eona.
E ts'oanang le tikoloho ea Libero, run.do file e tlameha ho etsoa ho tsamaisa papiso kantle ho Libero.
Etsa e bonolo run.do file e nang le litaelo tsa ho theha laeborari bakeng sa liphetho tsa pokello, 'mapa oa laeborari, pokello, le papiso. Latela mehato ea ho theha run.do ea motheo file.

1. Theha laeborari e utloahalang ho boloka liphetho tsa pokello u sebelisa vlib command vlib presynth.
2. 'Mapa lebitso la laebrari le utloahalang ho buka ea laebrari e hlophisitsoeng esale pele u sebelisa vmap command vmap .
3. Kopanya mohloli files-sebelisa litaelo tse ikhethileng tsa puo ho bokella moralo files ho directory ea ho sebetsa.
   – vlog bakeng sa .v/.sv
   – vcom bakeng sa .vhd
4. Laola moralo oa papiso o sebelisa taelo ea vsim ka ho hlakisa lebitso la mojule ofe kapa ofe oa boemo bo holimo.
5. Etsisa moralo o sebelisa run command.
   Kamora ho kenya moralo, nako ea ketsiso e behiloe ho zero, 'me u ka kenya taelo ea ho matha ho qala papiso.
   Fesetereng ea sengoloa sa simulator, phethisa run.do file joalo ka run.etsa ketsiso. Sample matha.etsa file ka mokoa o latelang.

seta ACTELLIBNAME PolarFire ka khutso seta PROJECT_DIR "W:/Test/basic_test" haeba
{[file e teng presynth/_info]} {echo “INFO: Ketsiso ea laeborari ea presynth e teng” } tse ling
{ file hlakola -force presynth vlib presynth } vmap presynth vmap PolarFire
"X:/Libero/Designer/lib/modelsimpro/precompiled/vlog/PolarFire" vlog -sv -work presynth
“${PROJECT_DIR}/hdl/top.v” vlog “+incdir+${PROJECT_DIR}/stimulus” -sv -work presynth “$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb eketsa wave /tb/*
matha 1000ns log /tb/* tsoa

Sehlomathiso C—Derive Constraints (Botsa Potso)

Sehlomathiso sena se hlalosa litaelo tsa Derive Constraints Tcl.
9.1 Fumana Litaelo tsa Tcl (Botsa Potso)
Ts'ebeliso ea derive_constraints e u thusa ho fumana litšitiso ho tsoa ho RTL kapa configurator kantle ho tikoloho ea moralo oa Libero SoC. Ho hlahisa litšitiso bakeng sa moralo oa hau, o hloka HDL ea Mosebelisi, HDL ea Karolo, le Litšitiso tsa Karolo. files. Litšitiso tsa karolo ea SDC files li fumaneha tlas'a /karolo/mosebetsi/ / / directory ka mor'a tlhophiso ea karolo le tlhahiso.
Karolo e 'ngoe le e 'ngoe ea lithibelo file e na le set_component tcl taelo (e hlalosa lebitso la motsoako) le lethathamo la lithibelo tse hlahisoang ka mor'a ho hlophisoa. Litšitiso li hlahisoa ho ipapisitsoe le tlhophiso mme li tobane le karolo ka 'ngoe.
Example 9-1. Tšitiso ea Karolo File bakeng sa PF_CCC Core
Ex ke enaample ea motsoako oa motsoako file bakeng sa motheo oa PF_CCC:
set_component PF_CCC_C0_PF_CCC_C0_0_PF_CCC
# Microchip Corp.
# Letsatsi: 2021-Oct-26 04:36:00
# Oache ea motheo bakeng sa PLL #0
create_clock -period 10 [ get_pins { pll_inst_0/REF_CLK_0 } ] create_generated_clock -divide_by 1 -source [ get_pins {pll_inst_0/
REF_CLK_0 } ] -phase 0 [ get_pins {pll_inst_0/OUT0 } ] Mona, create_clock and create_generated_clock ke litšupiso le lithibelo tsa oache ea tlhahiso ka ho latellana, tse hlahisoang ho ipapisitsoe le tlhophiso.
9.1.1 Ho sebetsa le deive_constraints Utility (Botsa Potso)
Litšitiso li feta ka har'a moralo le ho fana ka lithibelo tse ncha bakeng sa mohlala o mong le o mong oa karolo ho ipapisitsoe le karolo e fanoeng pele ea SDC. files. Bakeng sa lioache tsa litšupiso tsa CCC, e tsoela pele ka moralo ho fumana mohloli oa oache ea litšupiso. Haeba mohloli ke I/O, thibelo ea oache e tla beoa ho I/O. Haeba e le tlhahiso ea CCC kapa mohloli o mong oa oache (bakeng sa mohlalaample, Transceiver, oscillator), e sebelisa oache ho tsoa karolong e 'ngoe mme e tlaleha temoso haeba linako tse sa lumellaneng. Litšitiso li tla fana ka lithibelo bakeng sa li-macros tse ling joalo ka on-chip oscillator haeba u na le tsona ho RTL ea hau.
Ho phethahatsa ts'ebeliso ea derive_constraints, o tlameha ho fana ka .tcl file khang ea mola oa taelo e nang le lintlha tse latelang ka tatellano e boletsoeng.

1. Hlakisa lintlha tsa sesebelisoa u sebelisa lintlha tse karolong ea set_device.
2. Hlalosa tsela e eang ho RTL filee sebelisa lintlha tse karolong ea read_verilog kapa read_vhdl.
3. Seta mojule oa boemo bo holimo u sebelisa lintlha tse karolong set_top_level.
4. Hlalosa tsela ea karolo ea SDC filee sebelisa lintlha tse karolong ea read_sdc kapa read_ndc.
5. Phetha the filee sebelisa lintlha tse karolong deive_constraints.
6.  Hlalosa tsela e lebisang ho lithibelo tse nkiloeng ho SDC file ho sebelisa lintlha tse karolong ea write_sdc kapa write_pdc kapa write_ndc.

Example 9-2. Phethahatso le Litaba tsa derive.tcl File
Se latelang ke example khang ea mola oa taelo ho phethahatsa ts'ebeliso ea deive_constraints.
$ /bin{64}/derive_constraints deive.tcl
Likahare tsa derive.tcl file:
# Litaba tsa sesebelisoa
set_device -family PolarFire -die MPF100T -speed -1
#RTL files
bala_verilog -mode system_verilog project/component/work/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
bala_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
bala_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
bala_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
bala_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd}
#Karolo ea SDC files
set_top_level {xcvr1}
bala_sdc -karolo {project/component/work/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
bala_sdc -karolo {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
# Sebelisa taelo ea derive_constraint
deive_constraints
#SDC/PDC/NDC sephetho files
write_sdc {project/constraint/xcvr1_derived_constraints.sdc}
ngola_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 set_device (Botsa Potso)
Tlhaloso
Hlalosa lebitso la lelapa, lebitso la moratuoa, le boemo ba lebelo.
set_device -lelapa - shoa - lebelo
Likhang

Paramethara	Mofuta	Tlhaloso
-lelapa	Khoele	Hlalosa lebitso la lelapa. Maemo a ka bang teng ke PolarFire®, PolarFire SoC.
- shoa	Khoele	Hlalosa lebitso la lefu.
- lebelo	Khoele	Hlalosa boemo ba lebelo la sesebelisoa. Maemo a ka bang teng ke STD kapa -1.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0023	Paramethara e hlokahalang-fa ha e eo	Khetho ea "die" e tlamehile 'me e tlameha ho hlalosoa.
ERR0005	Lefu le sa tsejoeng 'MPF30'	Boleng ba -die khetho ha boa nepahala. Sheba lenane le ka bang teng la boleng tlhalosong ea khetho.
ERR0023	Parameter-die ha e na boleng	Khetho ea die e hlalositsoe ntle le boleng.
ERR0023	Paramethara e hlokahalang-lelapa ha le eo	Khetho ea lelapa e tlamaha 'me e tlameha ho hlalosoa.
ERR0004	Lelapa le sa tsejoeng 'PolarFire®'	Khetho ea lelapa ha ea nepahala. Sheba lenane le ka bang teng la boleng tlhalosong ea khetho.

………… e ile ea tsoela pele
Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0023	Paramethara—lelapa ha le na boleng	Khetho ea lelapa e hlalositsoe ntle le boleng.
ERR0023	Paramethara e hlokahalang-lebelo ha le teng	Khetho ea lebelo ke e tlamang 'me e tlameha ho boleloa.
ERR0007	Lebelo le sa tsejweng ' '	Khetho ea lebelo ha ea nepahala. Sheba lenane le ka bang teng la boleng tlhalosong ea khetho.
ERR0023	Paramethara-lebelo ha le na boleng	Khetho ea lebelo e hlalosoa ntle le boleng.

Example
set_device -family {PolarFire} -fa {MPF300T_ES} -lebelo -1
set_device -family SmartFusion 2 -die M2S090T -speed -1
9.1.3 bala_verilog (Botsa Potso)
Tlhaloso
Bala Verilog file sebelisa Verific.
bala_verilog [-lib ] [-mokhoa ]filelebitso>
Likhang

Paramethara	Mofuta	Tlhaloso
-lib	Khoele	Hlalosa laeborari e nang le li-module tse tla kengoa laebraring.
-mokgwa	Khoele	Hlalosa maemo a Verilog. Maemo a ka bang teng ke verilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. Boleng ha bo na taba. Ea kamehla ke verilog_2k.
filelebitso	Khoele	Verilog file lebitso.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0023	Paramethara-lib ha e na boleng	Khetho ea lib e hlalositsoe ntle le boleng.
ERR0023	Paramethara-mode ha e na boleng	Khetho ea mokhoa o boletsoeng ntle le boleng.
ERR0015	Mokhoa o sa tsejoeng ' '	Mokhoa o boletsoeng oa verilog ha o tsejoe. Sheba lenane la mekhoa ea verilog e ka khonehang ka mokhoa oa tlhaloso ea khetho.
ERR0023	Paramethara e hlokahalang file lebitso ha le yo	Ha ho verilog file tsela e fanoa.
ERR0016	E hlolehile ka lebaka la mohlahlobi oa Verific	Phoso ea syntax ho verilog file. Verific's parser e ka bonoa ho khomphutha e kaholimo ho molaetsa oa phoso.
ERR0012	set_device ha e bitsoe	Lintlha tsa sesebelisoa ha lia hlalosoa. Sebelisa set_device taelo ho hlalosa sesebelisoa.

Example
bala_verilog -mode system_verilog {component/work/top/top.v}
bala_verilog -mode system_verilog_mfcu design.v
9.1.4 bala_vhdl (Botsa Potso)
Tlhaloso
Kenya VHDL file lethathamong la VHDL files.
bala_vhdl [-lib ] [-mokhoa ]filelebitso>
Likhang

Paramethara	Mofuta	Tlhaloso
-lib	—	Hlalosa laebrari eo litaba li tlamehang ho eketsoa ho eona.
-mokgwa	—	E hlalosa maemo a VHDL. Ka ho feletseng ke VHDL_93. Maemo a ka bang teng ke vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. Boleng ha bo na taba.
filelebitso	—	VHDL file lebitso.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0023	Paramethara-lib ha e na boleng	Khetho ea lib e hlalositsoe ntle le boleng.
ERR0023	Paramethara-mode ha e na boleng	Khetho ea mokhoa o boletsoeng ntle le boleng.
ERR0018	Mokhoa o sa tsejoeng ' '	Mokhoa o boletsoeng oa VHDL ha o tsejoe. Sheba lenane la mekhoa ea VHDL e ka khonehang ka mokhoa oa tlhaloso ea khetho.
ERR0023	Paramethara e hlokahalang file lebitso ha le yo	Ha ho VHDL file tsela e fanoa.
ERR0019	Ha e khone ho ngolisa invalid_path.v file	VHDL e boletsoeng file ha e teng kapa ha e na tumello ea ho bala.
ERR0012	set_device ha e bitsoe	Lintlha tsa sesebelisoa ha lia hlalosoa. Sebelisa set_device taelo ho hlalosa sesebelisoa.

Example
bala_vhdl -mode vhdl_2008 osc2dfn.vhd
bala_vhdl {hdl/top.vhd}
9.1.5 set_top_level (Botsa Potso)
Tlhaloso
Hlalosa lebitso la mojule oa boemo bo holimo ho RTL.
set_top_level [-lib ]
Likhang

Paramethara	Mofuta	Tlhaloso
-lib	Khoele	Laeborari ea ho batla mojule oa boemo bo holimo kapa setheo (Ho ikhethela).
lebitso	Khoele	Mojule oa boemo bo holimo kapa lebitso la mokhatlo.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0023	Boemo bo holimo ba paramethara ha bo yo	Khetho ea boemo bo holimo ke e tlamang 'me e tlameha ho boleloa.
ERR0023	Paramethara-lib ha e na boleng	Khetho ea lib e hlalositsoe ntle le litekanyetso.
ERR0014	Ha e khone ho fumana boemo bo holimo ka laebraring	Mojule oa boemo bo holimo ha o hlalosoe laebraring e fanoeng. Ho lokisa phoso ena, mojule oa holimo kapa lebitso la laebrari le tlameha ho lokisoa.
ERR0017	Tlhaloso e hlōlehile	Phoso ts'ebetsong ea tlhaloso ea RTL. Molaetsa oa phoso o ka bonoa ho tsoa ho console.

Example
set_top_level {top}
set_top_level -lib hdl holimo
9.1.6 bala_sdc (Botsa Potso)
Tlhaloso
Bala SDC file ho database ea likarolo.
bala_sdc -karolofilelebitso>
Likhang

Paramethara	Mofuta	Tlhaloso
-karolo	—	Ena ke folakha e tlamang bakeng sa taelo ea read_sdc ha re fumana lithibelo.
filelebitso	Khoele	Tsela ea ho ea SDC file.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0023	Paramethara e hlokahalang file lebitso ha le yo.	Khetho e tlamang file lebitso ha lea hlalosoa.
ERR0000	SDC file <file_path> ha e balehe.	SDC e boletsoeng file ha e na tumello ea ho bala.
ERR0001	Ha e khone ho bulafile_tsela> file.	Sehlopha sa SDC file ha e yo. Tsela e tlameha ho lokisoa.
ERR0008	Taelo ea set_component e sieofile_tsela> file	Karolo e boletsoeng ea SDC file ha e hlalose karolo.

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0009	<List of errors from sdc file>	Sehlopha sa SDC file e na le litaelo tse fosahetseng tsa sdc. Bakeng sa mohlalaample, ha ho na le phoso ho set_multicycle_path constraint: Phoso ha o ntse o etsa taelo read_sdc: infile_tsela> file: Phoso taelong set_multicycle_path: Paramethara e sa tsejoeng [get_cells {reg_a}].

Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 bala_ndc (Botsa Potso)
Tlhaloso
Bala NDC file ho database ea likarolo.
bala_ndc -karolofilelebitso>
Likhang

Paramethara	Mofuta	Tlhaloso
-karolo	—	Ena ke folakha e tlamang bakeng sa taelo ea read_ndc ha re fumana lithibelo.
filelebitso	Khoele	Tsela ea ho ea NDC file.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0001	Ha e khone ho bulafile_tsela> file	Mokhatlo oa NDC file ha e yo. Tsela e tlameha ho lokisoa.
ERR0023	Paramethara e hlokahalang—AtclParamO_ ha e eo.	Khetho e tlamang filelebitso ha lea hlalosoa.
ERR0023	Paramethara e hlokahalang-karolo ha e eo.	Khetho ea karolo e tlama ebile e tlameha ho hlalosoa.
ERR0000	NDC file 'file_path>' ha e balehe.	NDC e boletsoeng file ha e na tumello ea ho bala.

Example
bala_ndc -karolo {component/work/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 deive_constraints (Botsa Potso)
Tlhaloso
Theha karolo ea SDC files ho database ea boemo ba moralo.
deive_constraints
Likhang

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0013	Boemo bo holimo ha bo hlalosoa	Sena se bolela hore mojule oa boemo bo holimo kapa setheo ha sea hlalosoa. Ho lokisa mohala ona, fana ka set_top_level taelo pele ho taelo ea deive_constraints.

Example
deive_constraints
9.1.9 ngola_sdc (Botsa Potso)
Tlhaloso
E ngola tšitiso file ka sebopeho sa SDC.
ngola_sdcfilelebitso>
Likhang

Paramethara	Mofuta	Tlhaloso
<filelebitso>	Khoele	Tsela ea ho ea SDC file e tla hlahisoa. Ena ke khetho e tlamang. Haeba e file e teng, e tla hlakoloa.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0003	Ha e khone ho bulafile tsela> file.	File tsela ha ea nepahala. Sheba hore na litataiso tsa batsoali li teng.
ERR0002	SDC file 'file path>' ha e ngoloe.	SDC e boletsoeng file ha e na tumello ea ho ngola.
ERR0023	Paramethara e hlokahalang file lebitso ha le yo.	Sehlopha sa SDC file tsela ke khetho e tlamang 'me e tlameha ho hlalosoa.

Example
write_sdc "derved.sdc"
9.1.10 write_pdc (Botsa Potso)
Tlhaloso
E ngola litšitiso tsa 'mele (Derive Constraints feela).
ngola_pdcfilelebitso>
Likhang

Paramethara	Mofuta	Tlhaloso
<filelebitso>	Khoele	Tsela ea ho PDC file e tla hlahisoa. Ena ke khetho e tlamang. Haeba e file tsela e teng, e tla hlakoloa.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Melaetsa ea Phoso	Tlhaloso
ERR0003	Ha e khone ho bulafile tsela> file	The file tsela ha ea nepahala. Sheba hore na litataiso tsa batsoali li teng.
ERR0002	PDC file 'file path>' ha e ngoloe.	PDC e boletsoeng file ha e na tumello ea ho ngola.
ERR0023	Paramethara e hlokahalang file lebitso ha le yo	Setšoantšo sa PDC file tsela ke khetho e tlamang 'me e tlameha ho hlalosoa.

Example
write_pdc "derved.pdc"
9.1.11 ngola_ndc (Botsa Potso)
Tlhaloso
E ngola litšitiso tsa NDC hore e be a file.
ngola_ndcfilelebitso>
Likhang

Paramethara	Mofuta	Tlhaloso
filelebitso	Khoele	Tsela ea ho ea NDC file e tla hlahisoa. Ena ke khetho e tlamang. Haeba e file e teng, e tla hlakoloa.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Melaetsa ea Phoso	Tlhaloso
ERR0003	Ha e khone ho bulafile_tsela> file.	File tsela ha ea nepahala. Likhokahano tsa batsoali ha li eo.
ERR0002	NDC file 'file_path>' ha e ngoloe.	NDC e boletsoeng file ha e na tumello ea ho ngola.
ERR0023	Karolo e hlokahalang _AtclParamO_ ha e eo.	Mokhatlo oa NDC file tsela ke khetho e tlamang 'me e tlameha ho hlalosoa.

Example
write_ndc "derved.ndc"
9.1.12 eketsa_include_path (Botsa Potso)
Tlhaloso
E hlalosa tsela ea ho batla e kenyelletsa files ha u bala RTL files.
eketsa_kenyelletsa_tsela
Likhang

Paramethara	Mofuta	Tlhaloso
directory	Khoele	E hlalosa tsela ea ho batla e kenyelletsa files ha u bala RTL files. Khetho ena ke e tlamang.

Mofuta oa ho Khutlisa	Tlhaloso
0	Taelo e atlehile.

Mofuta oa ho Khutlisa	Tlhaloso
1	Taelo e hlolehile. Ho na le phoso. U ka bona molaetsa oa phoso ho console.

Lethathamo la Liphoso

Khoutu ea Phoso	Molaetsa oa Phoso	Tlhaloso
ERR0023	E hlokehang parameter e kenyeletsang tsela ha e eo.	Khetho ea directory e tlamehile 'me e tlameha ho fanoa.

Tlhokomeliso: Haeba tsela ea li-directory ha e nepahale, joale add_include_path e tla fetisoa ntle le phoso.
Leha ho le joalo, bala_verilog/read_vhd litaelo li tla hloleha ka lebaka la mohlahlobi oa Verific.
Example
add_include_path component/work/CORABC0/CORABC0_0/rtl/vlog/core

Nalane ea Tlhabollo (Botsa Potso)

Nalane ea ntlafatso e hlalosa liphetoho tse kentsoeng tšebetsong tokomaneng. Liphetoho li thathamisitsoe ka ntlafatso, ho qala ka khatiso ea morao-rao.

Khatiso	Letsatsi	Tlhaloso
F	08/2024	Liphetoho tse latelang li entsoe tokisong ena: • Karolo e ntlafalitsoeng ea Sehlomathiso sa B—Ho Reka Lilaebrari tsa Ketsiso ho Tikoloho ea Ketsiso.
E	08/2024	Liphetoho tse latelang li entsoe tokisong ena: • Karolo e ntlafalitsoeng Ho fetaview. • Karolo e nchafalitsoeng e nkiloeng ho SDC File. • Karolo e ntlafalitsoeng ea Sehlomathiso sa B—Ho Reka Lilaebrari tsa Ketsiso ho Tikoloho ea Ketsiso.
D	02/2024	Tokomane ena e lokolloa ka Libero 2024.1 SoC Design Suite ntle le liphetoho tse tsoang ho v2023.2. Karolo e ntlafalitsoeng Ho sebetsa le derive_constraints Utility
C	08/2023	Tokomane ena e lokolloa ka Libero 2023.2 SoC Design Suite ntle le liphetoho tse tsoang ho v2023.1.
B	04/2023	Tokomane ena e lokolloa ka Libero 2023.1 SoC Design Suite ntle le liphetoho tse tsoang ho v2022.3.
A	12/2022	Phetolelo ea Pele.

Tšehetso ea Microchip FPGA
Sehlopha sa lihlahisoa tsa Microchip FPGA se tšehetsa lihlahisoa tsa sona ka lits'ebeletso tse fapaneng tsa tšehetso, ho kenyeletsoa Ts'ebeletso ea Bareki, Setsi sa Ts'ehetso ea Tekheniki ea Bareki, a websebaka, le liofisi tsa thekiso lefatšeng ka bophara.
Bareki ba khothaletsoa ho etela lisebelisoa tsa Marang-rang tsa Microchip pele ba ikopanya le tšehetso kaha ho ka etsahala hore ebe lipotso tsa bona li se li arajoa.
Ikopanye le Setsi sa Tšehetso ea Setsebi ka ho website at www.microchip.com/support. Bolela nomoro ea Karolo ea Sesebelisoa sa FPGA, khetha mofuta o nepahetseng oa linyeoe, 'me u hlophise moralo files ha u ntse u theha nyeoe ea tšehetso ea tekheniki.
Ikopanye le Tshebeletso ya Bareki bakeng sa tshehetso ya dihlahiswa tseo e seng tsa botekgeniki, jwalo ka ditheko tsa sehlahiswa, dintlafatso tsa sehlahiswa, tlhahisoleseding e ntjhafatsa, boemo ba odara, le tumello.

• Ho tsoa Amerika Leboea, letsetsa 800.262.1060
• Ho tsoa lefats'eng lohle, letsetsa 650.318.4460
• Fax, ho tsoa kae kapa kae lefatšeng, 650.318.8044

Boitsebiso ba Microchip
Microchip Websebaka
Microchip e fana ka tšehetso ea inthaneteng ka rona website at www.microchip.com/. Sena websebaka se sebedisoang ho etsa files le tlhahisoleseding e fumaneha habonolo ho bareki. Tse ling tsa litaba tse fumanehang li kenyelletsa:

• Tšehetso ea Sehlahisoa - Lipampiri tsa data le errata, lintlha tsa kopo le sample mananeo, lisebelisoa tsa moralo, litataiso tsa basebelisi le litokomane tsa tšehetso ea hardware, lintlafatso tsa morao-rao tsa software le li-archived software
• Tšehetso e Akaretsang ea Tekheniki - Lipotso Tse Botsoang Khafetsa (FAQs), likopo tsa tšehetso ea tekheniki, lihlopha tsa lipuisano tsa inthaneteng, lethathamo la litho tsa lenaneo la balekane ba Microchip
• Khoebo ea Microchip - Mokhethoa oa lihlahisoa le litataiso tsa ho odara, likhatiso tsa morao-rao tsa khatiso tsa Microchip, lethathamo la lithupelo le liketsahalo, lethathamo la liofisi tsa thekiso ea Microchip, barekisi le baemeli ba feme.

Ts'ebeletso ea Tsebiso ea Phetoho ea Sehlahisoa
Ts'ebeletso ea tsebiso ea phetoho ea sehlahisoa sa Microchip e thusa ho boloka bareki ba le teng ka lihlahisoa tsa Microchip. Ba ngolisitseng ba tla fumana tsebiso ea lengolo-tsoibila neng kapa neng ha ho na le liphetoho, lintlafatso, lintlafatso kapa liphoso tse amanang le sehlahisoa se itseng sa lelapa kapa sesebelisoa sa ntlafatso sa thahasello. Ho ngolisa, ea ho www.microchip.com/pcn mme o latele ditaelo tsa ngodiso.

Tšehetso ea Bareki
Basebelisi ba lihlahisoa tsa Microchip ba ka fumana thuso ka likanale tse 'maloa:

• Morekisi kapa Moemedi
• Ofisi ea Thekiso ea Lehae
• Embedded Solutions Engineer (ESE)
• Tšehetso ea tekheniki

Bareki ba lokela ho ikopanya le mofani oa bona oa thepa, moemeli kapa ESE bakeng sa tšehetso. Liofisi tsa thekiso ea lehae le tsona li teng ho thusa bareki. Lethathamo la liofisi tsa thekiso le libaka li kenyelelitsoe tokomaneng ena. Tšehetso ea tekheniki e fumaneha ka ho websebaka ho: www.microchip.com/support
Karolo ea Tšireletso ea Khoutu ea Lisebelisoa tsa Microchip
Ela hloko lintlha tse latelang tsa ts'ireletso ea khoutu lihlahisoa tsa Microchip:

• Lihlahisoa tsa Microchip li kopana le litlhaloso tse fumanehang ho Microchip Data Sheet ea bona.
• Microchip e lumela hore lihlahisoa tsa eona li sireletsehile ha li sebelisoa ka mokhoa o reriloeng, ka har'a litlhaloso tsa ts'ebetso, le tlas'a maemo a tloaelehileng.
• E boloka boleng ba Microchip mme ka mabifi e sireletsa litokelo tsa eona tsa thepa ea mahlale. Boiteko ba ho tlola likarolo tsa ts'ireletso ea khoutu ea sehlahisoa sa Microchip bo thibetsoe ka thata 'me bo ka tlola Molao oa Copyright oa Millennium oa Digital.
• Ha ho Microchip kapa moetsi ofe kapa ofe oa semiconductor ea ka netefatsang ts'ireletso ea khoutu ea eona. Tšireletso ea khoutu ha e bolele hore re tiisa hore sehlahisoa "se ke ke sa robeha". Tšireletso ea khoutu e lula e fetoha. Microchip e ikemiselitse ho tsoela pele ho ntlafatsa likarolo tsa ts'ireletso ea khoutu ea lihlahisoa tsa rona.

Tsebiso ea Molao
Khatiso ena le lintlha tse mona li ka sebelisoa feela le lihlahisoa tsa Microchip, ho kenyeletsoa ho rala, ho leka, le ho kopanya lihlahisoa tsa Microchip le kopo ea hau. Tšebeliso ea tlhahisoleseling ena ka tsela efe kapa efe e tlola melaoana ena. Lintlha mabapi le lits'ebetso tsa sesebelisoa li fanoe molemong oa hau feela 'me li ka nkeloa sebaka ke liapdeite. Ke boikarabello ba hau ho netefatsa hore kopo ea hau e kopana le litlhaloso tsa hau. Ikopanye le ofisi ea thekiso ea Microchip ea lehae bakeng sa tšehetso e eketsehileng kapa, fumana tšehetso e eketsehileng ho www.microchip.com/en-us/support/design-help/client-support-services.
TSEBISO ENA E FUMANA KE MICROCHIP "JOALOKAHA E LE". MICROCHIP HA E ETSE LITLHAHISO KAPA LITIISETSO TSA MOFUTA OFE kapa Ofe Ebang E BONAHALA KAPA E BONAHALA, E NGOLOA KAPA MOLOMO, MOLAO KAPA HANG-HANG, E Amanang le tlhahisoleseding e kenyellelitsoeng EMPA E SA LEkanyetsoa HO EFE KAOFELA TIISETSO, TLHOKOMELISO, TLHOKOMELISO, TLHOKOMELISO LE TLHAHISO. MORERO OA RONA, KAPA LITIISETSO E Amanang le MAEMO, BOLEMO, KAPA KETSAHALO EA EONA. HA HO LE TSATSAHALO, MICROCHIP E TLA BA MOTHO OA MOLATO BAKENG SA LITABA LIFE, TSE KHETHEHILENG, TSA KOTSO, TSATSAHALO, KAPA TAHLEHELO E LATELANG, TŠENYEHO, LITŠEnyehelo, KAPA LITJEHO TSA MOFUTA OO O MANG KAPA O MANG LE LITSEBISO KAPA TŠEBELETSO EA LONA, LE HO KA ETSAHALA KETSAHALO E ETSANG. TSE KA E KA ETSAHANG KAPA MESEKO E BONAHALA. HO FIHLELA KA BOKGOLO KA HO FETISISA KA MOLAO, BOIKARABELO KAOFELA BA MICROCHIP HO LIKELETSO KAOFELA KA TSELA EFE KAPA E MABAPI LE BOITSEBISO KAPA TŠEBELETSO EA YONA E KE KE EA FEELA BOLIMO BA LITEFO, HAEBA LI LE TENG, TSEO O LI LEFILENG KA THOHLO HO ETSA TSEBISO.
Tšebeliso ea lisebelisoa tsa Microchip ts'ehetso ea bophelo le/kapa lits'ebetso tsa ts'ireletso e kotsing ea moreki, 'me moreki o lumela ho sireletsa, ho qosa le ho boloka Microchip e se nang kotsi ho tsoa lits'enyehelong tsohle, likoloto, lisutu, kapa litšenyehelo tse bakoang ke ts'ebeliso e joalo. Ha ho lilaesense tse fetisoang, ka mokhoa o hlakileng kapa ka tsela e 'ngoe, tlasa litokelo life kapa life tsa thepa ea mahlale a Microchip ntle le ha ho boletsoe ka tsela e ngoe.
Matšoao a khoebo
Lebitso le logo ea Microchip, logo ea Microchip, Adaptec, AVR, logo ea AVR, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXSty Media, Micrologos, Micrologo, MOXSty , MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, tradeSource ea XME, Tichyon, TradeSource ea XME ea UNITED, UNITED TRADING, TXME, TEKSTO, TEKNOX, TEKS E kenyelelitsoe USA le linaheng tse ling.
AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, logo ea ProASIC Plus, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, le ZL ke matshwao a kgwebo a ngodisitsweng a Microchip Technology Incorporated in the USA.
Khatello e Haufi ea Key, AKS, Analog-for-the-Digital Age, AnyCapacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEMAverage, dsPICDEMverage.net, , DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCripto-Display, Marc. maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PureSimart , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Kakaretso ea Mamello , Nako e Tšeptjoang, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, le ZENA ke matshwao a kgwebo a Microchip Technology Incorporated USA le dinaheng tse ding.
SQTP ke letšoao la ts'ebeletso la Microchip Technology Incorporated USA
Letšoao la Adaptec, Frequency on Demand, Silicon Storage Technology, le Symmcom ke matšoao a ngolisitsoeng a khoebo a Microchip Technology Inc. linaheng tse ling.
GestIC ke letshwao la kgwebo le ngodisitsweng la Microchip Technology Germany II GmbH & Co. KG, e leng lekala la Microchip Technology Inc., dinaheng tse ding.
Matšoao a mang kaofela a boletsoeng mona ke thepa ea lik'hamphani tse fapaneng.
2024, Microchip Technology Incorporated le lithuso tsa eona. Litokelo tsohle li sirelelitsoe.
ISBN: 978-1-6683-0183-8
Tsamaiso ea Tsamaiso ea Boleng
Ho fumana leseli mabapi le Tsamaiso ea Tsamaiso ea Boleng ea Microchip, ka kopo etela www.microchip.com/quality.
Lithekiso le Tšebeletso ea Lefatše Lohle

LIMAKASE	ASIA/PACIFIC	ASIA/PACIFIC	ULAYA
Ofisi ea Khoebo 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Mohala: 480-792-7200 Fax: 480-792-7277 Tšehetso ea tekheniki: www.microchip.com/support Web Aterese: www.microchip.com Atlanta Duluth, GA Mohala: 678-957-9614 Fax: 678-957-1455 Austin, TX Mohala: 512-257-3370 Boston Westborough, MA Mohala: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Mohala: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Mohala: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Mohala: 248-848-4000 Houston, TX Mohala: 281-894-5983 Indianapolis Noblesville, IN Mohala: 317-773-8323 Fax: 317-773-5453 Mohala: 317-536-2380 Los Angeles Mission Viejo, CA Mohala: 949-462-9523 Fax: 949-462-9608 Mohala: 951-273-7800 Raleigh, NC Mohala: 919-844-7510 New York, NY Mohala: 631-435-6000 San Jose, CA Mohala: 408-735-9110 Mohala: 408-436-4270 Canada - Toronto Mohala: 905-695-1980 Fax: 905-695-2078	Australia - Sydney Mohala: 61-2-9868-6733 China - Beijing Mohala: 86-10-8569-7000 China - Chengdu Mohala: 86-28-8665-5511 China - Chongqing Mohala: 86-23-8980-9588 China - Dongguan Mohala: 86-769-8702-9880 China - Guangzhou Mohala: 86-20-8755-8029 China - Hangzhou Mohala: 86-571-8792-8115 China - Hong Kong SAR Mohala: 852-2943-5100 China - Nanjing Mohala: 86-25-8473-2460 China - Qingdao Mohala: 86-532-8502-7355 China - Shanghai Mohala: 86-21-3326-8000 China - Shenyang Mohala: 86-24-2334-2829 China - Shenzhen Mohala: 86-755-8864-2200 China - Suzhou Mohala: 86-186-6233-1526 China - Wuhan Mohala: 86-27-5980-5300 China - Xian Mohala: 86-29-8833-7252 China - Xiamen Mohala: 86-592-2388138 China - Zhuhai Mohala: 86-756-3210040	India - Bangalore Mohala: 91-80-3090-4444 India - New Delhi Mohala: 91-11-4160-8631 India - Pune Mohala: 91-20-4121-0141 Japane - Osaka Mohala: 81-6-6152-7160 Japane - Tokyo Mohala: 81-3-6880-3770 Korea - Daegu Mohala: 82-53-744-4301 Korea - Seoul Mohala: 82-2-554-7200 Malaysia - Kuala Lumpur Mohala: 60-3-7651-7906 Malaysia - Penang Mohala: 60-4-227-8870 Philippines - Manila Mohala: 63-2-634-9065 Singapore Mohala: 65-6334-8870 Taiwan - Hsin Chu Mohala: 886-3-577-8366 Taiwan - Kaohsiung Mohala: 886-7-213-7830 Taiwan - Taipei Mohala: 886-2-2508-8600 Thailand - Bangkok Mohala: 66-2-694-1351 Vietnam - Ho Chi Minh Mohala: 84-28-5448-2100	Austria - Wels Mohala: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Mohala: 45-4485-5910 Fax: 45-4485-2829 Finland - Espoo Mohala: 358-9-4520-820 Fora - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Jeremane - Ho khabisa Mohala: 49-8931-9700 Jeremane - Haan Mohala: 49-2129-3766400 Jeremane - Heilbronn Mohala: 49-7131-72400 Jeremane - Karlsruhe Mohala: 49-721-625370 Jeremane - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Jeremane - Rosenheim Mohala: 49-8031-354-560 Iseraele - Hod Hasharon Mohala: 972-9-775-5100 Italy - Milan Mohala: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Mohala: 39-049-7625286 Netherlands - Drunen Mohala: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Mohala: 47-72884388 Poland - Warsaw Mohala: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Mohala: 46-8-5090-4654 UK - Wokingham Mohala: 44-118-921-5800 Fax: 44-118-921-5820

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