PolarFire Iyali FPGA Jagorar Mai Amfani da Yawo na Musamman
Libero SoC v2024.2

Gabatarwa (Yi Tambaya)

Software na Libero System-on-Chip (SoC) yana ba da cikakkiyar yanayin ƙira Filin Shirye-shiryen Ƙofar Array (FPGA). Koyaya, ƴan masu amfani za su so yin amfani da haɗin gwiwar ɓangare na uku da kayan aikin kwaikwayo a wajen yanayin Libero SoC. Yanzu ana iya haɗa Libero cikin yanayin ƙirar FPGA. Ana ba da shawarar yin amfani da Labero SoC don sarrafa gabaɗayan ƙirar ƙirar FPGA.
Wannan jagorar mai amfani yana bayyana Ƙararren Ƙararren don PolarFire da PolarFire SoC na'urorin Iyali, tsari don haɗa Libero a matsayin wani ɓangare na mafi girma na ƙirar ƙirar FPGA. Families na Na'ura da ake Tallafawa Teburin da ke gaba yana lissafin iyalan na'urar da Libero SoC ke tallafawa. Koyaya, wasu bayanai a cikin wannan jagorar na iya aiki ga takamaiman dangin na'urori kawai. A wannan yanayin, ana gano irin waɗannan bayanan a fili.
Tebur 1. Iyalan Na'ura da Libero SoC ke Tallafawa

Iyalin Na'ura	Bayani
PolarFire®	PolarFire FPGAs suna isar da mafi ƙarancin ƙarfin masana'antar a matsakaicin matsakaicin matsakaici tare da ingantaccen tsaro da aminci.
PolarFire SoC	PolarFire SoC shine farkon SoC FPGA tare da ƙayyadaddun ƙididdiga, haɗin gwiwar RISC-V CPU cluster, da ƙayyadaddun tsarin ƙwaƙwalwar ajiya na L2 wanda ke ba da damar Linux® da aikace-aikacen lokaci-lokaci.

Ƙarsheview (Yi Tambaya)

Yayin da Libero SoC ke ba da cikakkiyar yanayin ƙira na ƙarshen-zuwa-ƙarshe don haɓaka ƙirar SoC da FPGA, kuma yana ba da sassauci don gudanar da ƙira da kwaikwaya tare da kayan aikin ɓangare na uku a waje da yanayin Libero SoC. Koyaya, dole ne wasu matakan ƙira su kasance a cikin yanayin Libero SoC.
Tebur mai zuwa yana lissafin manyan matakai a cikin tsarin ƙirar FPGA kuma yana nuna matakan da dole ne a yi amfani da Libero SoC.
Tebur 1-1. FPGA Tsare Tsara

Zane Mataki Mataki	Dole ne a yi amfani da Libero	Bayani
Saukewa: HDL	A'a	Yi amfani da editan HDL na ɓangare na uku / kayan aikin dubawa a wajen Libero® SoC idan ana so.
Shigar da ƙira: Configurator	Ee	Ƙirƙiri aikin Libero na farko don ƙayyadaddun bayanai na IP na asali.
Ƙirƙirar ƙuntataccen PDC/SDC ta atomatik	A'a	Abubuwan da aka samo suna buƙatar duk HDL files da kuma abin amfani da abubuwan da aka samu_constraints lokacin da aka yi su a wajen Libero SoC, kamar yadda aka bayyana a cikin Karin Bayani C — Ƙuntatawa.
kwaikwayo	A'a	Yi amfani da kayan aikin ɓangare na uku a wajen Libero SoC, idan ana so. Yana buƙatar zazzage dakunan karatu na kwaikwaiyo da aka riga aka haɗa don na'urar da aka yi niyya, na'urar kwaikwayo da aka yi niyya, da sigar Libero da aka yi amfani da ita don aiwatar da baya.
Magana	A'a	Yi amfani da kayan aikin ɓangare na uku a wajen Libero SoC idan ana so.
Aiwatar da ƙira: Sarrafa Ƙuntatawa, Haɗa jerin layi, Wuri da Hanya (duba Samaview)	Ee	Ƙirƙiri aikin Libero na biyu don aiwatar da baya.
Lokaci da Tabbatar da Wuta	Ee	Kasance cikin aikin Libero na biyu.
Saita Ƙirƙirar Ƙirƙirar Bayanan Farko da Tunawa	Ee	Yi amfani da wannan kayan aikin don sarrafa nau'ikan tunani daban-daban da ƙaddamar da ƙira a cikin na'urar. Tsaya a cikin aiki na biyu.
Shirye-shirye File Tsari	Ee	Tsaya a cikin aiki na biyu.

Muhimmi: Kai dole ne a zazzage dakunan karatu da aka riga aka shirya a wurin Dakunan karatu na Simulators da aka riga aka gama shafi don amfani da na'urar kwaikwayo ta ɓangare na uku.
A cikin madaidaicin Fabric FPGA, shigar da ƙirar ku ta amfani da HDL ko shigarwar tsari kuma wuce wancan kai tsaye
zuwa kayan aikin haɗin gwiwa. Har yanzu ana goyan bayan kwararar. PolarFire da PolarFire SoC FPGAs suna da mahimmanci
Tubalan IP masu wuyar mallakar mallaka waɗanda ke buƙatar amfani da ƙirar ƙira (SgCores) daga Libero SoC IP
kasida. Ana buƙatar kulawa ta musamman don kowane tubalan da suka ƙunshi ayyukan SoC:

• PolarFire
  - PF_UPROM
  - PF_SYSTEM_SERVICES
  - PF_CCC
  - PF CLK DIV
  - PF_CRYPTO
  - PF_DRI
  - PF_INIT_MONITOR
  - PF_NGMUX
  - PF_OSC
  - RAM (TPSRAM, DPSRAM, URAM)
  - PF_SRAM_AHBL_AXI
  - PF_XCVR_ERM
  - PF_XCVR_REF_CLK
  - PF_TX_PLL
  - PF_PCIE
  - PF_IO
  - PF_IOD_CDR
  - PF_IOD_CDR_CCC
  - PF_IOD_GENERIC_RX
  - PF_IOD_GENERIC_TX
  - PF_IOD_GENERIC_TX_CCC
  - PF_RGII_TO_GMII
  - PF_IOD_OCTAL_DDR
  - PF_DDR3
  - PF_DDR4
  - PF_LPDDR3
  - PF_QDR
  - PF_CORESMARTBERT
  - PF_TAMPER
  - PF_TVS, da sauransu.

Baya ga na baya da aka jera SgCores, akwai da yawa DirectCore taushi IPs samuwa ga PolarFire da PolarFire iyalai na na'urar SoC a cikin Libero SoC Catalog waɗanda ke amfani da albarkatun masana'anta na FPGA.
Don shigarwar ƙira, idan kun yi amfani da ɗaya daga cikin abubuwan da suka gabata, dole ne ku yi amfani da Libero SoC don wani ɓangare na shigarwar ƙira (Hanyar Ƙirar), amma kuna iya ci gaba da sauran Shigarwar Zane (shigarwa HDL, da sauransu) a wajen Libero. Don sarrafa tsarin FPGA a wajen Libero, bi matakan da aka bayar a sauran wannan jagorar.
1.1 Zagayowar Rayuwa (Yi Tambaya)
Matakan da ke biyowa suna bayyana yanayin rayuwar wani ɓangaren SoC kuma suna ba da umarni kan yadda ake sarrafa bayanan.

1. Ƙirƙirar ɓangaren ta amfani da mai daidaita shi a cikin Libero SoC. Wannan yana haifar da nau'ikan bayanai masu zuwa:
   - HDL files
   – Ƙwaƙwalwar ajiya files
   - Ƙarfafawa da Kwaikwayo files
   - Bangaren SDC file
2. don HDL files, nan take da haɗa su cikin sauran ƙirar HDL ta amfani da kayan aikin shigarwa / tsari na waje.
3. Ƙwaƙwalwar ajiya files da kara kuzari files zuwa kayan aikin kwaikwayo na ku.
4. Abubuwan da ake bayarwa SDC file zuwa Samar da kayan aiki don Ƙarfafa Ƙuntatawa. Dubi Shafi C — Samar da Ƙuntatawa don ƙarin cikakkun bayanai.
5. Dole ne ku ƙirƙiri aikin Libero na biyu, inda za ku shigo da netlist bayan-Synthesis da metadata na bangaren ku, don haka kammala haɗin tsakanin abin da kuka ƙirƙira da abin da kuka tsara.

1.2 Labero SoC Project Ƙirƙirar (Yi Tambaya)
Dole ne a gudanar da wasu matakan ƙira a cikin yanayin Libero SoC (Table 1-1). Don waɗannan matakan su gudana, dole ne ku ƙirƙiri ayyukan Libero SoC guda biyu. Ana amfani da aikin na farko don daidaitawar sassan ƙira da tsarawa, kuma aikin na biyu shine don aiwatar da jiki na ƙirar matakin sama.
1.3 Tafiya ta Musamman (Yi Tambaya)
Hoto mai zuwa yana nuna:

• Za a iya haɗa Libero SoC a matsayin wani ɓangare na mafi girma na ƙirar ƙirar FPGA tare da haɗin ɓangare na uku da kayan aikin kwaikwayo a waje da yanayin Libero SoC.
• Matakai daban-daban da ke tattare da kwarara, farawa daga ƙirƙira ƙira da ɗinki har zuwa tsara na'urar.
• Musayar bayanai (masu shigarwa da fitarwa) wanda dole ne ya faru a kowane mataki na kwararar ƙira.

Tukwici:

1. SNVM.cfg, UPROM.cfg
2. *.mem file tsara don Simulation: pa4rtupromgen.exe yana ɗaukar UPROM.cfg azaman shigarwa kuma yana haifar da UPROM.mem.

Wadannan su ne matakai a cikin al'ada ta gudana:

1. Tsare-tsare da ƙira:
   a. Ƙirƙiri aikin Libero na farko (don zama aikin Magana).
   b. Zaɓi Core daga Catalog. Danna sau biyu don ba shi sunan bangaren kuma saita bangaren.
   Wannan yana fitar da bayanan sassa ta atomatik kuma files. Hakanan ana haifar da Bayyanawar Ƙarfafawa. Dubi Bayanin Bangaren don cikakkun bayanai. Don ƙarin cikakkun bayanai, duba Kanfigareshan Sashe.
2. Kammala ƙirar RTL ɗinku a wajen Libero:
   a. Ƙaddamar da sashin HDL files.
   b. Wurin da HDL files an jera su a cikin Ma'anar Ma'anar Ma'anar files.
3. Ƙirƙirar ƙuntatawar SDC don abubuwan haɗin gwiwa. Yi amfani da mai amfani Constraints don samar da ƙuntataccen lokaci file(SDC) bisa:
   a. Abubuwan da aka bayar na HDL files
   b. Bangaren SDC files
   c. HDL mai amfani files
   Don ƙarin cikakkun bayanai, duba Karin Bayani C — Ƙuntatawa.
4. Kayan aikin haɗin gwiwa / kayan aikin kwaikwayo:
   a. Farashin HDL files, kara kuzari files, da bayanan sassa daga takamaiman wurare kamar yadda aka gani a cikin Mahimman Bayanan.
   b. Haɗa da kwaikwaya ƙira tare da kayan aikin ɓangare na uku a wajen Libero SoC.
5. Ƙirƙiri aikin Libero na biyu (Aiwatarwa).
6. Cire kira daga sarkar kayan aiki mai gudana (Project> Saitunan Aiki> Tsara Tsara> share Akwatin rajistan Haɗawa).
7. Shigo tushen ƙira files (bayan kira * .vm netlist daga kayan aikin haɗawa):
   - Shigo bayan kira * .vm netlist (File> Shigowa> Lissafin Tattaunawa na Verilog (VM)).
   - metadata na ɓangaren * .cfg files don uPROM da/ko sNVM.
8. Shigo da kowane ɓangaren toshewar Libero SoC files. Toshe files dole ne ya kasance a cikin * .cxz file tsari.
   Don ƙarin bayani kan yadda ake ƙirƙirar block, duba Jagorar Mai Amfani PolarFire Block Flow.
9. Shigo da ƙayyadaddun ƙira:
   – Shigo da ƙuntatawar I/O files (Constraint Manager> I/OAtributes> Shigo).
   – Shigo da shirin ƙasa *.pdc files (Mai sarrafa ƙuntatawa> Mai tsara bene> Shigo).
   – Shigo da * .sdc ƙuntata lokaci files (Constraint Manager> Lokaci> Shigo). Shigo da SDC file wanda aka samar ta hanyar kayan aiki na Constraint.
   – Shigo da *.ndc takura files (Constraint Manager> NetlistAttributes> Shigo), idan akwai.
10. Takura file da ƙungiyar kayan aiki
    – A cikin Constraint Manager, haɗa * .pdc files zuwa wuri da hanya, da * .sdc files zuwa wuri da hanya da tabbatarwar lokaci, da * .ndc files zuwa Haɗa Netlist.
11. Cikakken aiwatar da ƙira
    - Wuri da hanya, tabbatar da lokaci da iko, saita bayanan ƙaddamar da ƙira da abubuwan tunawa, da shirye-shirye file tsara.
12. Tabbatar da ƙira
    - Tabbatar da ƙira akan FPGA kuma zazzage kamar yadda ya cancanta ta amfani da kayan aikin ƙira da aka bayar tare da rukunin ƙirar Libero SoC.

Kanfigareshan Na'ura (Yi Tambaya)

Mataki na farko a cikin kwararar al'ada shine saita kayan aikin ku ta amfani da aikin tunani na Libero (wanda kuma ake kira aikin Libero na farko a cikin Tebu 1-1). A matakai na gaba, kuna amfani da bayanai daga wannan aikin tunani.
Idan kana amfani da duk wasu abubuwan da aka lissafa a baya, ƙarƙashin Overview a cikin ƙirar ku, yi matakan da aka bayyana a cikin wannan sashe.
Idan ba kwa amfani da kowane ɗayan abubuwan da ke sama, zaku iya rubuta RTL ɗinku a wajen Libero kuma kai tsaye shigo da shi cikin kayan aikin Synthesis da Simulation. Sannan zaku iya ci gaba zuwa sashin bayan-kirki sannan kawai shigo da jerin abubuwan da kuka biyo bayan kira *.vm netlist cikin aikin aiwatar da Libero na karshe (wanda kuma ake kira aikin Libero na biyu a cikin Tebura 1-1).
2.1 Kanfigareshan Na'ura Ta Amfani da Libero (Yi Tambaya)
Bayan zabar abubuwan da dole ne a yi amfani da su daga lissafin da suka gabata, yi matakai masu zuwa:

1. Ƙirƙirar sabon aikin Libero (Tsarin Kanfigareshan da Ƙarni): Zaɓi Na'ura da Iyali waɗanda kuka yi niyya don ƙirar ku ta ƙarshe.
2. Yi amfani da ɗaya ko fiye daga cikin maƙallan da aka ambata a cikin Tsarin Al'ada.
   a. Ƙirƙiri SmartDesign kuma saita ainihin abin da ake so kuma sanya shi cikin sashin SmartDesign.
   b. Haɓaka duk fil zuwa babban matakin.
   c. Ƙirƙirar SmartDesign.
   d. Danna sau biyu kayan aikin Simulate (kowane na Pre-Synthesis ko Post-Synthesis ko Zaɓuɓɓukan Bayan-Layout) don kiran na'urar kwaikwayo. Kuna iya fita daga na'urar kwaikwayo bayan an kira shi. Wannan mataki yana haifar da simulation fileya zama dole don aikin ku.

Tukwici: ka dole ne kuyi wannan matakin idan kuna son kwaikwayi ƙirar ku a wajen Libero.
Don ƙarin bayani, duba Simulating Your Design.
e. Ajiye aikinku - wannan shine aikin tunani.
2.2 Bayanin Bangaren (Yi Tambaya)
Lokacin da kuke samar da abubuwan haɗin ku, saitin files ana samarwa ga kowane bangare. Rahoton Bayanin Ƙarfafawa yayi cikakken bayani game da saitin files haifar da amfani a kowane mataki na gaba (Synthesis, Simulation, Firmware Generation, da sauransu). Wannan rahoton yana ba ku wuraren duk abubuwan da aka samar files da ake buƙata don ci gaba tare da Ƙwararren Ƙwararren. Kuna iya samun damar bayanan bayanan a cikin yankin Rahotanni: Danna Zane> Rahotanni don buɗe shafin Rahotanni. A cikin shafin Rahotanni, kuna ganin saitin manifest.txt files (Naview), ɗaya ga kowane ɓangaren da kuka ƙirƙira.
Tukwici: Dole ne ku saita sashi ko module azaman '' tushen '' don ganin ɓangaren ya bayyana file abubuwan da ke cikin shafin Rahotanni.
A madadin, zaku iya samun dama ga rahoton bayyanannen mutum ɗaya files ga kowane ainihin bangaren da aka samar ko bangaren SmartDesign daga /bangaren/aiki/ / / _manifest.txt ko /bangaren/aiki/ / _bayyana.txt. Hakanan zaka iya samun dama ga bayanan file abubuwan da ke cikin kowane ɓangaren da aka samar daga sabon shafin abubuwan da aka haɗa a cikin Libero, inda file an ambaci wurare game da kundin tsarin aiki.Mayar da hankali kan rahotannin Bayyanar Abubuwan Mahimmanci:

• Idan kun sanya maƙallan ƙira a cikin SmartDesign, karanta file _bayyana.txt.
• Idan kun ƙirƙiri abubuwan haɗin gwiwa don muryoyin, karanta _bayyana.txt.

Dole ne ku yi amfani da duk bayanan Bayanan Abubuwan da suka shafi ƙirar ku. Don misaliampTo, idan aikinku yana da SmartDesign tare da ɗaya ko fiye da abubuwan da aka gyara a ciki kuma kuna da niyyar amfani da su duka a ƙirar ku ta ƙarshe, to dole ne ku zaɓi. files da aka jera a cikin Rahoton Bayanan Abubuwan Abubuwan Duk waɗannan abubuwan haɗin gwiwa don amfani a cikin ƙirar ƙira.
2.3 Bayyanar Fassarar Files (Yi Tambaya)
Lokacin da ka buɗe bayanan bayanan file, ka ga hanyoyi zuwa files a cikin aikin ku na Libero da masu nuni akan inda cikin ƙirar ƙira don amfani da su. Kuna iya ganin irin waɗannan nau'ikan files a cikin bayyanar file:

• HDL asalin files don duk kayan aikin haɗin gwiwa da kwaikwaiyo
• Ƙarfafawa files don duk kayan aikin kwaikwayo
• Takura files

Mai zuwa shine Bayanin Bangaren PolarFire core.Kowane irin file wajibi ne a ƙasa a cikin ƙirar ku. Sassan da ke gaba suna bayyana haɗin kai na files daga bayyanuwar cikin ƙirar ƙirar ku.

Ƙarfafa Ƙaddara (Yi Tambaya)

Lokacin aiwatar da tsari da tsarawa, tabbatar da rubutawa/samar da ƙuntatawar SDC/PDC/NDC files don ƙira don ƙaddamar da su zuwa Ƙarfafawa, Wuri da Hanya, da Tabbatar da kayan aikin lokaci.
Yi amfani da kayan aikin Ƙarfafa Ƙuntatawa a wajen yanayin Libero don haifar da ƙuntatawa maimakon rubuta su da hannu. Don amfani da kayan aikin Ƙarfafawa a waje da yanayin Libero, dole ne ku:

• Mai amfani mai bayarwa HDL, bangaren HDL, da ƙuntatawar bangaren SDC files
• Ƙayyade babban matakin matakin
• Ƙayyade wurin da za a haifar da ƙuntatawa da aka samu files

Ƙuntataccen ɓangaren SDC yana samuwa a ƙarƙashin /bangaren/aiki/ / / directory bayan tsarin tsari da tsarawa.
Don ƙarin cikakkun bayanai kan yadda ake samar da ƙuntatawa don ƙirar ku, duba Karin Bayani C — Ƙuntatawa.

Haɗin Zane Naku (Yi Tambaya)

Ɗaya daga cikin manyan fasalulluka na Flow ɗin Custom shine don ba ku damar yin amfani da haɗin ɓangare na uku
kayan aiki a wajen Libero. Gudun al'ada yana goyan bayan amfani da Synopsys SynplifyPro. Don haɗa naku
aikin, yi amfani da hanya mai zuwa:

1. Ƙirƙiri sabon aiki a cikin kayan aikin haɗin gwiwar ku, wanda ke nufin dangin na'ura iri ɗaya, mutu, da fakitin kamar aikin Libero da kuka ƙirƙira.
   a. Shigo naku RTL filekamar yadda kuka saba yi.
   b. Saita fitowar Haɓaka ta zama Verilog Structural (.vm).
   Tukwici: Tsarin tsari Verilog (.vm) shine kawai tsarin fitarwa na haɗin kai mai goyan baya a cikin PolarFire.
2. Shigo Bangaren HDL files cikin aikin Synthesis ɗin ku:
   a. Ga kowane ɓangaren Bayyanawar Rahoton: Ga kowane file karkashin HDL tushen files don duk kayan aikin Synthesis da Simulation, shigo da file a cikin aikin haɗin gwiwar ku.
3. Shigo da file polarfire_syn_comps.v (idan ana amfani da Synopsys Synplify) daga
   Wurin shigarwa>/data/aPA5M zuwa aikin haɗin gwiwar ku.
4. Shigo da SDC da aka samar a baya file ta hanyar Kayan aikin Ƙuntatawa (duba Karin Bayani
   A- Sample SDC Constraints) a cikin kayan aikin Synthesis. Wannan takura file yana ƙuntata kayan aikin haɗawa don cimma rufewar lokaci tare da ƙarancin ƙoƙari da ƙarancin ƙira.

Muhimmi: 

• Idan kuna shirin amfani da wannan *.sdc file don ƙuntata Wuri-da-Hanyar hanya a lokacin aiwatar da ƙira, dole ne ku shigo da wannan *.sdc cikin aikin haɗin gwiwa. Wannan shi ne don tabbatar da cewa babu wani abin ƙira da bai dace da sunan abin ƙira a cikin haɗaɗɗiyar netlist da ƙuntatawa na Wuri-da-Hanyoyi yayin aiwatar da tsarin ƙira. Idan baku haɗa wannan *.sdc file a cikin matakin Ƙaddamarwa, jerin saƙon da aka ƙirƙira daga Synthesis na iya gazawa a matakin Wuri da Hanya saboda rashin daidaituwar sunan abu.
  a. Shigo da Halayen Netlist *.ndc, idan akwai, cikin kayan aikin haɗin gwiwa.
  b. Run Synthesis.
• Wurin fitowar kayan aikin haɗin gwiwar ku yana da * .vm netlist file generated post Synthesis. Dole ne ku shigo da jerin rukunin yanar gizon zuwa cikin Ayyukan Aiwatar da Libero don ci gaba da tsarin ƙira.

Simulating Your Design (Yi Tambaya)

Don kwaikwayi ƙirar ku a wajen Libero (wato, ta yin amfani da yanayin simintin ku da na'urar kwaikwayo), yi matakai masu zuwa:

1. Zane Files:
   a. Simulation Pre-Synthesis:
   • Shigo RTL ɗinku cikin aikin simintin ku.
   • Ga kowane ɓangaren Bayyanawar Rahoton.
   – Shigo kowane file karkashin HDL tushen files don duk Ƙirƙiri da kayan aikin kwaikwayo a cikin aikin simintin ku.
   • Haɗa waɗannan files bisa ga umarnin na'urar kwaikwayo.
   b. Kwaikwayo bayan kira:
   • Shigo da bayanan da aka yi *.vm netlist (wanda aka ƙirƙira a cikin Tsarin Zane naku) cikin aikin simintin ku kuma haɗa shi.
   c. Kwaikwayo bayan-tsari:
   • Da farko, kammala aiwatar da ƙirar ku (duba Aiwatar da Zane naku). Tabbatar cewa aikin Libero ɗin ku na ƙarshe yana cikin yanayin bayan-bayanin.
   • Danna Sau biyu Ƙirƙirar Baya Annotated Files a cikin taga Flow Design na Libero. Yana haifar da biyu files:
   /mai tsarawa/ / _ba.v/vhd /mai tsarawa/
   / _ba.sdf
   • Shigo da waɗannan biyun files cikin kayan aikin kwaikwayo na ku.
2. Ƙarfafawa da Kanfigareshan files:
   a. Ga kowane Sahibin Bayanin Rahoton:
   Kwafi duka files ƙarƙashin Ƙarfafawa Files don duk sassan Kayan aikin Simulation zuwa tushen littafin aikin kwaikwayo na ku.
   b. Tabbatar cewa kowane Tcl files a cikin lissafin da suka gabata (a mataki na 2.a) ana aiwatar da su da farko, kafin fara simulation.
   c. UPROM.mem: Idan kuna amfani da ainihin UPROM a cikin ƙirar ku tare da zaɓi Yi amfani da abun ciki don simulation da aka kunna don ɗaya ko fiye da abokan ciniki na ajiyar bayanai waɗanda kuke son kwaikwaya, dole ne kuyi amfani da pa4rtupromgen mai aiwatarwa (pa4rtupromgen.exe akan windows) don samar da UPROM.mem file. The pa4rtupromgen executable daukan UPROM.cfg file a matsayin shigarwa ta hanyar rubutun Tcl file kuma yana fitar da UPROM.mem file da ake buƙata don kwaikwayo. Wannan UPROM.mem file dole ne a kwafi zuwa babban fayil na simulation kafin gudanar da simintin. Example nuna pa4rtupromgen executable amfani da aka bayar a cikin wadannan matakai. UPROM.cfg file yana samuwa a cikin kundin adireshi /bangaren/aiki/ / a cikin aikin Libero wanda kuka yi amfani da shi don samar da bangaren UPROM.
   d. snvm.mem: Idan kuna amfani da ainihin Sabis na System a cikin ƙirar ku kuma ku saita shafin sNVM a cikin ainihin tare da zaɓi Yi amfani da abun ciki don kwaikwaya da aka kunna don ɗaya ko fiye abokan ciniki waɗanda kuke son kwaikwaya, snvm.mem file ana haifar dashi ta atomatik zuwa
   littafin directory /bangaren/aiki/ / a cikin aikin Libero wanda kuka yi amfani da shi don samar da sashin Sabis na Tsarin. Wannan snvm.mem file dole ne a kwafi zuwa babban fayil na simulation kafin gudanar da simintin.
3. Ƙirƙiri babban fayil mai aiki da babban babban fayil mai suna kwaikwayo a ƙarƙashin babban fayil ɗin aiki.
   Mai aiwatarwa na pa4rtupromgen yana tsammanin kasancewar babban fayil ɗin simulation a cikin babban fayil ɗin aiki kuma an sanya rubutun * .tcl a cikin babban fayil ɗin simulation.
4. Kwafi UPROM.cfg file daga farkon aikin Libero wanda aka ƙirƙira don tsara kayan aikin cikin babban fayil ɗin aiki.
5. Manna waɗannan umarni a cikin rubutun * .tcl kuma sanya shi a cikin babban fayil ɗin simulation da aka ƙirƙira a mataki na 3.
   Sample *.tcl don PolarFire da PolarFire Soc na'urorin Iyali don samar da URPOM.mem file
   daga UPROM.cfg
   saitin_na'urar -fam - mutu pkg
   saita_input_cfg -hanyar
   saita_sim_mem -hanyarFile/UPROM.mem>
   gen_sim -use_init karya
   Don ingantaccen sunan ciki don amfani da mutu da kunshin, duba *.prjx file na aikin Libero na farko (an yi amfani da shi don samar da sassan).
   Dole ne a saita hujja use_init zuwa karya.
   Yi amfani da umarnin set_sim_mem don tantance hanyar zuwa fitarwa file UPROM.mem wato
   haifar da aiwatar da rubutun file tare da pa4rtupromgen executable.
6. A umarni da sauri ko tashar cygwin, je zuwa kundin aiki da aka ƙirƙira a mataki na 3.
   Yi umarnin pa4rtupromgen tare da zaɓin rubutun kuma wuce zuwa gare shi rubutun * .tcl da aka ƙirƙira a matakin baya.
   Don Windows
   /designer/bin/pa4rtupromgen.exe \
   -script./simulations/ .tcl
   Don Linux:
   /bin/pa4rtupromgen
   -script./simulations/ .tcl
7. Bayan nasarar aiwatar da pa4rtupromgen executable, duba cewa UPROM.mem file An ƙirƙira shi a cikin wurin da aka ƙayyade a cikin umarnin set_sim_mem a cikin rubutun * .tcl.
8. Don kwaikwayi sNVM, kwafi snvm.mem file daga aikinka na farko na Libero (wanda aka yi amfani da shi don daidaitawar bangaren) zuwa babban babban fayil na simulation na aikin simintin ku don gudanar da simulation (a wajen Libero SoC). Don kwaikwayi abubuwan da ke cikin UPROM, kwafi UPROM.mem da aka samar file cikin babban babban fayil na simulation na aikin simintin ku don gudanar da simulation (a wajen Libero SoC).

Muhimmi: To kwaikwayi ayyukan SoC Components, zazzage dakunan karatu na siminti na PolarFire da shigo da su cikin yanayin simintin ku kamar yadda aka bayyana anan. Don ƙarin cikakkun bayanai, duba Karin Bayani na B—Shigo da Laburaren Kwaikwayi zuwa Mahalli na Kwaikwayi.

Aiwatar da Tsarin ku (Yi Tambaya)

Bayan kammala simulation na Synthesis da Post-Synthesis a cikin mahallin ku, dole ne ku sake amfani da Libero don aiwatar da ƙirar ku ta jiki, gudanar da nazarin lokaci da ikon bincike, da samar da shirye-shiryen ku. file.

1. Ƙirƙirar sabon aikin Libero don aiwatarwa ta jiki da kuma tsarin zane. Tabbatar yin niyya na na'ura iri ɗaya kamar a cikin aikin tunani da kuka ƙirƙira a cikin Kanfigareshan Na'ura.
2. Bayan ƙirƙirar aikin, cire Synthesis daga sarkar kayan aiki a cikin taga Flow Design (Project> Saitunan Ayyuka> Tsarin Tsara> Cire Haɓakawa Haɗawa).
3.  Shigo bayanan bayanan ku *.vm file cikin wannan aikin, (File > Shigowa > Rukunin Lissafin Sadarwar Sadarwar Verilog (VM)).
   Tukwici: Ana ba da shawarar cewa ka ƙirƙiri hanyar haɗi zuwa wannan file, ta yadda idan kun sake tsara ƙirar ku, Libero ko da yaushe yana amfani da sabon saƙon netlist na baya-bayan nan.
   a. A cikin Tagar Tsara Tsara, lura da sunan tushen tsarin.
4. Shigo da ƙuntatawa cikin aikin Libero. Yi amfani da Constraint Manager don shigo da *.pdc/*.sdc/*.ndc constraints.
   a. Shigo I/O * .pdc takura files (Constraint Manager> I/O Halaye> Shigo).
   b. Shigo da Tsarin ƙasa * .pdc ƙuntatawa files (Mai sarrafa ƙuntatawa> Mai tsara bene> Shigo).
   c. Shigo da * .sdc takurawar lokaci files (Constraint Manager> Lokaci> Shigo). Idan ƙirar ku tana da ɗaya daga cikin abubuwan da aka jera a Overview, tabbatar da shigo da SDC file wanda aka samar ta hanyar kayan aiki na ƙuntatawa.
   d. Shigo da *.ndc takura files (Constraint Manager> Netlist Halayen> Shigo).
5. Matsalolin haɗin gwiwa Files don tsara kayan aikin.
   a. Buɗe Manajan Ƙuntatawa (Sarrafa Ƙuntatawa> Buɗe Sarrafa ƙuntatawa View).
   Duba wuri-da-Hanyar hanya da Tabbatar da Tabbatarwa Lokaci kusa da takura file don kafa takura file da ƙungiyar kayan aiki. Haɗa ƙaƙƙarfan * .pdc zuwa Wuri-da Hanya da *.sdc zuwa duka Wuri da Hanya da Tabbatarwa Lokaci. Haɗa * .ndc file don Haɗa Netlist.
   Tukwici: Idan Wuri da Hanya sun kasa tare da wannan ƙuntatawa * .sdc file, sannan shigo da wannan *.sdc file don haɗawa da sake yin kira.
6. Danna Haɗa Netlist sannan kuma Wuri da Hanya don kammala matakin shimfidar wuri.
7. Ƙirƙirar Ƙirƙirar Ƙirƙirar Bayanan Ƙaddamarwa da kayan aiki na Memories yana ba ku damar fara ginshiƙan ƙira, kamar LSRAM, µSRAM, XCVR (transceivers), da PCIe ta amfani da bayanan da aka adana a cikin µPROM, sNVM, ko ƙwaƙwalwar ajiyar SPI Flash na waje. Kayan aiki yana da shafuka masu zuwa don ƙayyade ƙayyadaddun tsarin ƙaddamar da ƙira, ƙayyadaddun abokan ciniki na farawa, abokan ciniki na bayanan mai amfani.
   – Zane Fara shafin
   - µPROM tab
   - sNVM tab
   – SPI Flash tab
   - Fabric RAMs tab
   Yi amfani da shafuka a cikin kayan aiki don saita bayanan ƙaddamar da ƙira da abubuwan tunawa.Bayan kammala saitin, aiwatar da matakai masu zuwa don tsara bayanan farawa:
   • Ƙirƙirar abokan ciniki na farko
   • Ƙirƙirar ko fitarwa da bitstream
   • Shirya na'urar
   Don cikakkun bayanai kan yadda ake amfani da wannan kayan aikin, duba Jagorar Mai amfani da Zane na Zane na Libero SoC. Don ƙarin bayani kan umarnin Tcl da aka yi amfani da su don saita shafuka daban-daban a cikin kayan aiki da ƙayyadadden tsarin ƙwaƙwalwar ajiya files (*.cfg), duba Tcl Jagoran Magana.
8. Ƙirƙirar Shirye-shiryen File daga wannan aikin kuma yi amfani da shi don tsara FPGA ɗin ku.

Bayanin A-Sampda Matsalolin SDC (Yi Tambaya

Libero SoC yana haifar da ƙayyadaddun lokacin SDC don wasu abubuwan haɗin IP, kamar CCC, OSC, Transceiver da sauransu. Wucewa ƙaƙƙarfan SDC don ƙira kayan aikin yana ƙara damar haɗuwa da rufe lokaci tare da ƙarancin ƙoƙari da ƙarancin ƙira. An ba da cikakkiyar hanyar matsayi daga babban matakin misali don duk abubuwan ƙira da aka ambata a cikin ƙuntatawa.
7.1 SDC Ƙuntataccen Lokaci (Yi Tambaya)
A cikin aikin tunani na Libero IP, wannan babban matakin SDC takura file yana samuwa daga Manajan Ƙuntatawa (Tsarin Zane> Buɗe Sarrafa Ƙuntatawa View > Lokaci > Ƙarfafawa).
Muhimmi: Duba wannan file don saita ƙuntatawar SDC idan ƙirarku ta ƙunshi CCC, OSC, Transceiver, da sauran abubuwan haɗin gwiwa. Canza cikakkiyar hanyar matsayi, idan ya cancanta, don dacewa da tsarin ƙirar ku ko amfani da kayan amfani na Derive_Constraints da matakai a cikin Karin Bayani C — Samar da Ƙuntatawa akan matakin SDC file.
Ajiye file zuwa wani suna daban kuma shigo da SDC file zuwa kayan aikin haɗin kai, Kayan aikin Wuri-da-Hanyar hanya, da Tabbatarwar Lokaci, kamar kowane ƙuntatawar SDC. files.
7.1.1 An samo SDC File (Yi Tambaya)
# Wannan file an ƙirƙira ta bisa tushen SDC mai zuwa files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/bangaren/aiki/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/bangaren/aiki/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/bangaren/aiki/
TRANSMIT_PLL / TRANSMIT_PLL_0 / TRANSMIT_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/bangaren/aiki/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/bangaren/aiki/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/bangaren/aiki/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/bangaren/aiki/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/bangaren/aiki/
PCIE_INITIATOR/ PCIE_INITIATOR_0/ PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** Duk wani gyare-gyare ga wannan file za a yi asara idan aka sake gudanar da matsalolin da aka samu. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} -lokaci 6.25
[samu_pin {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } Create_clock -name {REF_CLK_PAD_P} -lokaci 10 [samun_ports {REF_CLK_PAD_P} ] ƙirƙirar_clock -suna {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/tx
DIV_CLK} -lokaci na 8
[samu_pin {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK} ] ƙirƙirar_generated_clock -suna {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_int_CC
OUT0} - ninka_ta 25 -raba_ta 32 -source
[samu_pin {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -phase 0
[samu_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0} ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT1} - ninka_ta 25 -raba_ta 32 -source
[samu_pin {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -phase 0
[samu_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1} ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT2} - ninka_ta 25 -raba_ta 32 -source
[samu_pin {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -phase 0
[samu_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2} ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT3} - ninka_ta 25 -raba_ta 64 -source
[samu_pin {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -phase 0
[samu_pin {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3} ] ƙirƙirar_generated_clock -suna {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_DIMZ
Y_DIV} -raba_ta 2 - tushe
[samu_pin {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_zuwa_CLK_80MHz/CLK_DIV_0/I_CD/A} ] [samu_pin {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_zuwa_CLK_80VD_DIV_DIV set_false_path -ta hanyar [samun_nets { DMA_INITIATOR_inst_0/ARESETN*} ] saita_fanse_hanyar_daga [ samu_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray*}] -ga [samun_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1*} ] saita_fanse_hanya -daga [samun_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray*}] -ga [samun_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1*} ] saita_false_path -ta hanyar [samun_nets {FIC0_INITIATOR_inst_0/ARESETN*} ] saita_fanse_hanyar_zuwa [samun_pins { PCIE/PF_PCIE_C0_0/ PCIE_1/INTERRUPT[0] PCIE/PF_0/C0
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/ PCIE_1/MPERST_N } ] set_false_path -daga [samu_pins { PCIE/PF_PCIE_C0_0/ PCIE_1/TL_CLK}] set_false_path -ta hanyar [samun_nets { PCIE_NITIA] Shafi B — Ana Shigo da Dakunan karatu na Kwaikwayi cikin Mahalli na Kwaikwayi (Yi Tambaya)
Tsohuwar na'urar kwaikwayo don simintin RTL tare da Libero SoC shine ModelSim ME Pro.
Ana samun ɗakunan karatu da aka riga aka haɗa don tsoho na'urar kwaikwayo tare da shigarwar Libero a directory /Designer/lib/modelsimpro/precompiled/vlog for® goyon bayan iyalai. Libero SoC kuma yana goyan bayan wasu nau'ikan simulators na ɓangare na uku na ModelSim, Questasim, VCS, Xcelium
, HDL mai aiki, da Riviera Pro. Zazzage dakunan karatu da aka riga aka haɗa daga Libero SoC v12.0 kuma daga baya dangane da na'urar kwaikwayo da sigar sa.
Kama da muhallin Libero, run.do file dole ne a ƙirƙira don gudanar da simulation a wajen Libero.
Ƙirƙirar gudu mai sauƙi.do file wanda ke da umarni don kafa ɗakin karatu don tattara sakamakon, taswirar ɗakin karatu, haɗawa, da kwaikwayo. Bi matakan don ƙirƙirar run.do na asali file.

1. Ƙirƙiri ɗakin karatu na ma'ana don adana sakamakon tattarawa ta amfani da vlib umurnin vlib presynth.
2. Taswirar sunan ɗakin karatu na ma'ana zuwa kundin adireshin ɗakin karatu da aka riga aka haɗa ta amfani da vmap umurnin vmap .
3. Haɗa tushe files — yi amfani da takamaiman umarni masu tara harshe don haɗa ƙira files cikin kundin aiki.
   - vlog don .v/.sv
   – vcom don .vhd
4. Load da ƙira don kwaikwaiyo ta amfani da umarnin vsim ta hanyar tantance sunan kowane babban matakin matakin.
5. Yi kwaikwayon ƙira ta amfani da umarnin gudu.
   Bayan loda ƙirar, lokacin simintin yana saita zuwa sifili, kuma zaku iya shigar da umarnin gudu don fara simulation.
   A cikin taga kwafin na'urar kwaikwayo, aiwatar da run.do file kamar yadda run.do gudanar da simulation. Sampda run.do file mai bi.

a hankali saita ACTELLIBNAME PolarFire a hankali saita PROJECT_DIR "W:/Test/basic_test" idan
{[file akwai presynth/_info]} {echo"INFO: Presynth library presynth wanzu"} wani
{ file share -force presynth vlib presynth } vmap presynth presynth vmap PolarFire
"X:/Libero/Designer/lib/modelsimpro/precompiled/vlog/PolarFire" vlog -sv -work presynth
"${PROJECT_DIR}/hdl/top.v" vlog "+incdir+${PROJECT_DIR}/stimulus" -sv -aiki presynth "$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb ƙara kalaman /tb/*
gudu 1000ns log /tb/* fita

Shafi C — Samar da Matsaloli (Yi Tambaya)

Wannan karin bayani yana bayyana umarnin Tcl Deive Constraints.
9.1 Samar da Matsalolin Tcl Dokokin (Yi Tambaya)
Mai amfani da derive_constraints yana taimaka muku samun ƙuntatawa daga RTL ko mai daidaitawa a wajen yanayin ƙirar Libero SoC. Don samar da ƙuntatawa don ƙirar ku, kuna buƙatar mai amfani HDL, Bangaren HDL, da Ƙaƙƙarfan Abu files. Bangaren SDC yana takura files suna samuwa a ƙarƙashin /bangaren/aiki/ / / directory bayan tsarin tsari da tsarawa.
Kowane ɓangaren ƙuntatawa file ya ƙunshi umarnin tcl set_component (yana ƙayyadadden sunan bangaren) da jerin ƙuntatawa da aka haifar bayan daidaitawa. Ana haifar da ƙuntatawa bisa ga tsari kuma suna da takamaiman ga kowane bangare.
Exampku 9-1. Ƙuntataccen sashi File don PF_CCC Core
Ga wani tsohonample na wani bangaren ƙuntata file don ainihin PF_CCC:
saitin_component PF_CCC_C0_PF_CCC_C0_0_PF_CCC
#Microchip Corp.
# Ranar: 2021-Oktoba-26 04:36:00
# Agogon tushe don PLL #0
Create_clock -period 10 [samu_pins {pll_inst_0/REF_CLK_0}] ƙirƙirar_generated_clock -divide_by 1 -source [samu_pins {pll_inst_0/
REF_CLK_0} ] -phase 0 [get_pins {pll_inst_0/OUT0} ] Anan, ƙirƙirar_clock da ƙirƙirar_generated_clock sune ƙuntatawa na agogo da fitarwa bi da bi, waɗanda aka ƙirƙira bisa ga tsari.
9.1.1 Yin aiki tare da abubuwan da ake buƙata.Yi Tambaya)
Ƙirar ƙaƙƙarfan ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun ƙayyadaddun abubuwan da aka samar a baya sun dogara da SDC. files. Don agogon nuni na CCC, yana yaɗa baya ta hanyar ƙira don nemo tushen agogon tunani. Idan tushen I/O ne, za a saita ƙuntatawar agogon tunani akan I/O. Idan fitarwa ce ta CCC ko wani tushen agogo (misaliample, Transceiver, oscillator), yana amfani da agogo daga ɗayan ɓangaren kuma yana ba da rahoton gargadi idan tazara bai dace ba. Ƙunƙasassun ƙuntatawa kuma za su keɓance ƙuntatawa ga wasu macros kamar on-chip oscillators idan kuna da su a cikin RTL ɗinku.
Don aiwatar da amfanin derive_constraints, dole ne ku samar da .tcl file gardamar layin umarni tare da bayanai masu zuwa a cikin ƙayyadadden tsari.

1. Ƙayyade bayanan na'ura ta amfani da bayanin a cikin sashe set_device.
2. Ƙayyade hanyar zuwa RTL files ta amfani da bayanin a cikin sashe read_verilog ko read_vhdl.
3. Saita babban matakin matakin ta amfani da bayanin da ke cikin sashe set_top_level.
4. Ƙayyade hanya zuwa bangaren SDC files ta amfani da bayanin a cikin sashe read_sdc ko read_ndc.
5. aiwatar da fileAna amfani da bayanan da ke cikin sashin derive_constraints.
6.  Ƙayyade hanya zuwa ƙuntatawa da aka samo SDC file ta amfani da bayanin da ke cikin sashe write_sdc ko write_pdc ko write_ndc.

Exampku 9-2. Aiwatar da abubuwan da aka samo asali.tcl File
Mai zuwa shine tsohonampLe gardamar layin umarni don aiwatar da amfanin derive_constraints.
$ /bin{64}/samun_constraints derive.tcl
Abubuwan da ke cikin abin da aka samo.tcl file:
# Bayanin na'ura
set_na'urar -family PolarFire -die MPF100T -speed -1
# RTL files
read_verilog -mode system_verilog project/bangaren/aiki/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
read_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
karanta_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd}
# Bangaren SDC files
set_top_level {xcvr1}
read_sdc -bangaren {project/component/work/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
read_sdc -bangaren {project/component/aiki/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
#Yi amfani da umarnin hanawa
samu_constraints
Sakamakon # SDC/PDC/NDC files
rubuta_sdc {project/constraint/xcvr1_derived_constraints.sdc}
rubuta_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 saitin_na'urar (Yi Tambaya)
Bayani
Ƙayyade sunan iyali, sunan mutu, da matakin saurin gudu.
saitin_na'urar - iyali - mutu -gudu
Hujja

Siga	Nau'in	Bayani
-iyali	Zaren	Ƙayyade sunan iyali. Mahimman ƙididdiga sune PolarFire®, PolarFire SoC.
- mutu	Zaren	Ƙayyade sunan mutu.
-gudu	Zaren	Ƙayyade ƙimar saurin na'urar. Ƙididdiga masu yiwuwa su ne STD ko -1.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0023	Sigar da ake buƙata—mutu ya ɓace	Zaɓin mutu ya zama dole kuma dole ne a ƙayyade.
Saukewa: ERR0005	Mutuwar da ba a sani ba 'MPF30'	Ƙimar zaɓin -die ba daidai ba ne. Dubi yiwuwar lissafin ƙimar a cikin bayanin zaɓi.
Saukewa: ERR0023	Siga — mutu ya ɓace ƙimar	An ƙayyade zaɓin mutu ba tare da ƙima ba.
Saukewa: ERR0023	Sigar da ake buƙata—iyali ya ɓace	Zaɓin iyali ya zama dole kuma dole ne a ƙayyade.
Saukewa: ERR0004	Iyalin da ba a sani ba 'PolarFire®'	Zaɓin iyali bai dace ba. Dubi yiwuwar lissafin ƙimar a cikin bayanin zaɓi.

………… ci gaba
Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0023	Siga—iyali ya ɓace darajar	An ƙayyade zaɓin iyali ba tare da ƙima ba.
Saukewa: ERR0023	Sigar da ake buƙata—gudun ya ɓace	Zaɓin gudun ya zama tilas kuma dole ne a ƙayyade.
Saukewa: ERR0007	Gudun da ba a sani ba' '	Zaɓin gudun ba daidai ba ne. Dubi yiwuwar lissafin ƙimar a cikin bayanin zaɓi.
Saukewa: ERR0023	Siga—gudun yana ɓacewa ƙima	An ƙayyade zaɓin gudun ba tare da ƙima ba.

Example
set_device -family {PolarFire} -die {MPF300T_ES} -speed -1
set_na'urar -iyali SmartFusion 2 -die M2S090T -speed -1
9.1.3 karanta_verilog (Yi Tambaya)
Bayani
Karanta Verilog file amfani da Verific.
karanta_verilog [-lib ] [-mode ]filesuna>
Hujja

Siga	Nau'in	Bayani
-lib	Zaren	Ƙayyade ɗakin karatu wanda ke ƙunshe da kayan aikin da za a ƙara a cikin ɗakin karatu.
- yanayin	Zaren	Ƙayyade mizanin Verilog. Mahimman ƙima sune verilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. Ƙimar ba ta da hankali. Default shine verilog_2k.
filesuna	Zaren	Verilog file suna.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0023	Siga-lib ya ɓace darajar	An ƙayyade zaɓin lib ba tare da ƙima ba.
Saukewa: ERR0023	Siga—yanayin ba shi da ƙima	An ƙayyade zaɓin yanayin ba tare da ƙima ba.
Saukewa: ERR0015	Yanayin da ba a sani ba' '	Ba a san ƙayyadadden yanayin verilog ba. Duba jerin yiwuwar yanayin verilog a cikin - bayanin zaɓin yanayin.
Saukewa: ERR0023	Sigar da ake buƙata file suna ya ɓace	Babu verilog file an bayar da hanya.
Saukewa: ERR0016	Ba a yi nasara ba saboda tantancewar Verific	Kuskuren syntax a cikin verilog file. Ana iya lura da fassarwar Verific a cikin na'ura mai kwakwalwa sama da saƙon kuskure.
Saukewa: ERR0012	set_na'urar ba a kira	Ba a bayyana bayanin na'urar ba. Yi amfani da umarnin set_device don kwatanta na'urar.

Example
read_verilog -mode system_verilog {bangaren/aiki/top/top.v}
read_verilog -mode system_verilog_mfcu design.v
9.1.4 karanta_vhdlYi Tambaya)
Bayani
Ƙara VHDL file cikin jerin VHDL files.
karanta_vhdl [-lib ] [-mode ]filesuna>
Hujja

Siga	Nau'in	Bayani
-lib	—	Ƙayyade ɗakin karatu wanda dole ne a ƙara abun ciki a ciki.
- yanayin	—	Yana ƙayyade ma'aunin VHDL. Tsohuwar shine VHDL_93. Mahimman ƙima sune vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. Ƙimar ba ta da hankali.
filesuna	—	VHDL file suna.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0023	Siga-lib ya ɓace darajar	An ƙayyade zaɓin lib ba tare da ƙima ba.
Saukewa: ERR0023	Siga—yanayin ba shi da ƙima	An ƙayyade zaɓin yanayin ba tare da ƙima ba.
Saukewa: ERR0018	Yanayin da ba a sani ba' '	Ba a san ƙayyadadden yanayin VHDL ba. Duba jerin yuwuwar yanayin VHDL a cikin bayanin zaɓin yanayin.
Saukewa: ERR0023	Sigar da ake buƙata file suna ya ɓace	Babu VHDL file an bayar da hanya.
Saukewa: ERR0019	An kasa yin rajistar invalid_path.v file	VHDL da aka ƙayyade file babu ko bashi da izinin karantawa.
Saukewa: ERR0012	set_na'urar ba a kira	Ba a bayyana bayanin na'urar ba. Yi amfani da umarnin set_device don kwatanta na'urar.

Example
karanta_vhdl -yanayin vhdl_2008 osc2dfn.vhd
karanta_vhdl {hdl/top.vhd}
9.1.5 set_top_level (Yi Tambaya)
Bayani
Ƙayyade sunan babban matakin matakin a cikin RTL.
set_top_level [-lib ]
Hujja

Siga	Nau'in	Bayani
-lib	Zaren	Laburaren don nemo babban matakin matakin ko mahallin (Na zaɓi).
suna	Zaren	Babban matakin module ko sunan mahaluki.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0023	Babban matakin siga da ake buƙata ya ɓace	Zaɓin babban matakin wajibi ne kuma dole ne a ƙayyade.
Saukewa: ERR0023	Siga-lib ya ɓace darajar	An ƙayyade zaɓin lib ba tare da ƙima ba.
Saukewa: ERR0014	An kasa samun babban matakin a cikin ɗakin karatu	Ba a bayyana ƙayyadadden ƙirar matakin matakin ba a cikin ɗakin karatu da aka bayar. Don gyara wannan kuskuren, dole ne a gyara babban tsarin ko sunan ɗakin karatu.
Saukewa: ERR0017	Fahimtar ya kasa	Kuskure a cikin tsarin bayanin RTL. Ana iya lura da saƙon kuskure daga na'urar wasan bidiyo.

Example
saitin_top_level { saman}
set_top_level -lib hdl saman
9.1.6 read_sdc (Tambaya Tambaya)
Bayani
Karanta SDC file a cikin bangaren bayanai.
read_sdc -bangarenfilesuna>
Hujja

Siga	Nau'in	Bayani
-bangaren	—	Wannan tuta ce ta tilas don umarnin read_sdc lokacin da muka sami takura.
filesuna	Zaren	Hanyar zuwa SDC file.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0023	Sigar da ake buƙata file suna ya ɓace.	Zabin wajibi file ba a bayyana suna ba.
Saukewa: ERR0000	SDC file <file_path> ba a iya karantawa.	SDC da aka ƙayyade file bashi da izinin karantawa.
Saukewa: ERR0001	An kasa buɗewafile_tafarki> file.	Farashin SDC file babu shi. Dole ne a gyara hanyar.
Saukewa: ERR0008	Ba a rasa umarnin saitin_component a cikifile_tafarki> file	Abubuwan da aka ƙayyade na SDC file bai fayyace bangaren ba.

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0009	<List of errors from sdc file>	Farashin SDC file ya ƙunshi umarnin sdc ba daidai ba. Don misaliample, lokacin da aka sami kuskure a cikin ƙuntatawar set_multicycle_path: Kuskure yayin aiwatar da umarnin read_sdc: infile_tafarki> file: Kuskure a cikin umarni set_multicycle_path: Sigar da ba a sani ba [get_cells {reg_a}].

Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 read_ndc (Tambaya Tambaya)
Bayani
Karanta NDC file a cikin bangaren bayanai.
read_ndc -bangarenfilesuna>
Hujja

Siga	Nau'in	Bayani
-bangaren	—	Wannan tuta ce ta tilas don umarnin read_ndc lokacin da muka sami takura.
filesuna	Zaren	Hanyar zuwa NDC file.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0001	An kasa buɗewafile_tafarki> file	Farashin NDC file babu shi. Dole ne a gyara hanyar.
Saukewa: ERR0023	Sigar da ake buƙata-AtclParamO_ ya ɓace.	Zabin wajibi fileba a bayyana suna ba.
Saukewa: ERR0023	Sigar da ake buƙata—bangaren ya ɓace.	Zaɓin ɓangaren ya zama dole kuma dole ne a ƙayyade.
Saukewa: ERR0000	NDC file 'file_path>' ba za a iya karantawa ba.	Ƙididdigar NDC file bashi da izinin karantawa.

Example
read_ndc -bangaren {bangare/aiki/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 Abubuwan da aka samu (Tambaya Tambaya)
Bayani
Sashin gaggawa na SDC files a cikin matakin ƙira database.
samu_constraints
Hujja

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0013	Ba a bayyana babban matakin ba	Wannan yana nufin cewa ba a kayyade matakin babban matakin ko mahallin ba. Don gyara wannan kiran, fitar da umarnin set_top_level kafin umarnin derive_constraints.

Example
samu_constraints
9.1.9 write_sdc (Tambaya Tambaya)
Bayani
Ya rubuta takura file a cikin tsarin SDC.
rubuta_sdcfilesuna>
Hujja

Siga	Nau'in	Bayani
<filesuna>	Zaren	Hanyar zuwa SDC file za a samar. Wannan zaɓi ne na wajibi. Idan da file akwai, za a sake rubuta shi.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0003	An kasa buɗewafile hanyar> file.	File hanya ba daidai ba. Bincika ko akwai kundayen adireshi na iyaye.
Saukewa: ERR0002	SDC file 'file hanya>' ba a rubuta ba.	SDC da aka ƙayyade file ba shi da izinin rubutawa.
Saukewa: ERR0023	Sigar da ake buƙata file suna ya ɓace.	Farashin SDC file hanya zaɓi ne na wajibi kuma dole ne a ƙayyade.

Example
rubuta_sdc "derived.sdc"
9.1.10 write_pdc (Tambaya Tambaya)
Bayani
Yana rubuta ƙuntatawa ta jiki (Ƙananan Ƙuntatawa kawai).
rubuta_pdcfilesuna>
Hujja

Siga	Nau'in	Bayani
<filesuna>	Zaren	Hanyar zuwa PDC file za a samar. Wannan zaɓi ne na wajibi. Idan da file hanyar akwai, za a sake rubuta shi.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙonnin Kuskure	Bayani
Saukewa: ERR0003	An kasa buɗewafile hanyar> file	The file hanya ba daidai ba. Bincika ko akwai kundayen adireshi na iyaye.
Saukewa: ERR0002	PDC file 'file hanya > '' ba za a iya rubutawa ba.	PDC da aka ƙayyade file ba shi da izinin rubutawa.
Saukewa: ERR0023	Sigar da ake buƙata file suna ya ɓace	Farashin PDC file hanya zaɓi ne na wajibi kuma dole ne a ƙayyade.

Example
rubuta_pdc "derived.pdc"
9.1.11 rubuta_ndc (Tambaya Tambaya)
Bayani
Yana rubuta ƙuntatawa na NDC zuwa cikin a file.
rubuta_ndcfilesuna>
Hujja

Siga	Nau'in	Bayani
filesuna	Zaren	Hanyar zuwa NDC file za a samar. Wannan zaɓi ne na wajibi. Idan da file akwai, za a sake rubuta shi.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙonnin Kuskure	Bayani
Saukewa: ERR0003	An kasa buɗewafile_tafarki> file.	File hanya ba daidai ba. Babu kundayen adireshi na iyaye.
Saukewa: ERR0002	NDC file 'file_path>' ba a iya rubutawa.	Ƙididdigar NDC file ba shi da izinin rubutawa.
Saukewa: ERR0023	Sigar da ake buƙata _AtclParamO_ ya ɓace.	Farashin NDC file hanya zaɓi ne na wajibi kuma dole ne a ƙayyade.

Example
rubuta_ndc "derived.ndc"
9.1.12 add_include_hanya (Yi Tambaya)
Bayani
Yana ƙayyadadden hanya don bincika ya haɗa da files lokacin karanta RTL files.
add_hada_hanyar
Hujja

Siga	Nau'in	Bayani
directory	Zaren	Yana ƙayyadadden hanya don bincika ya haɗa da files lokacin karanta RTL files. Wannan zabin ya zama dole.

Nau'in Komawa	Bayani
0	Umurnin ya yi nasara.

Nau'in Komawa	Bayani
1	Umurnin ya kasa. Akwai kuskure. Kuna iya lura da saƙon kuskure a cikin na'ura wasan bidiyo.

Jerin Kurakurai

Lambar Kuskure	Saƙon kuskure	Bayani
Saukewa: ERR0023	Sigar da ake buƙata sun haɗa da bacewar hanya.	Zaɓin kundin adireshi ya zama dole kuma dole ne a ba da shi.

Note: Idan Hanyar shugabanci ba daidai ba ne, sannan add_include_path za a wuce ba tare da kuskure ba.
Koyaya, umarnin read_verilog/read_vhd ba zai yi nasara ba saboda tantancewar Verific.
Example
add_include_path bangaren/aiki/COREABC0/COREABC0_0/rtl/vlog/core

Tarihin Bita (Yi Tambaya)

Tarihin bita ya bayyana canje-canjen da aka aiwatar a cikin takaddar. Canje-canjen an jera su ta bita, farawa da mafi kyawun ɗaba'ar.

Bita	Kwanan wata	Bayani
F	08/2024	Ana yin canje-canje masu zuwa a cikin wannan bita: Sashen da aka sabunta Shafi B — Shigo da Laburaren Kwaikwayi zuwa Mahalli na Kwaikwayi.
E	08/2024	Ana yin canje-canje masu zuwa a cikin wannan bita: Sashen da aka sabunta ya ƙareview. Sashin da aka sabunta Ya Samo SDC File. Sashen da aka sabunta Shafi B — Shigo da Laburaren Kwaikwayi zuwa Mahalli na Kwaikwayi.
D	02/2024	An fitar da wannan takaddar tare da Libro 2024.1 SoC Design Suite ba tare da canje-canje daga v2023.2. Sashin da aka sabunta yana Aiki tare da Utility derive_constraints
C	08/2023	An fitar da wannan takaddar tare da Libro 2023.2 SoC Design Suite ba tare da canje-canje daga v2023.1.
B	04/2023	An fitar da wannan takaddar tare da Libro 2023.1 SoC Design Suite ba tare da canje-canje daga v2022.3.
A	12/2022	Bita na farko.

Tallafin FPGA Microchip
Ƙungiyar samfuran Microchip FPGA tana goyan bayan samfuran ta tare da sabis na tallafi daban-daban, gami da Sabis na Abokin Ciniki, Cibiyar Tallafin Fasaha ta Abokin Ciniki, a website, da ofisoshin tallace-tallace na duniya.
Ana ba abokan ciniki shawarar ziyartar albarkatun kan layi na Microchip kafin tuntuɓar tallafi saboda da yuwuwar an riga an amsa tambayoyinsu.
Tuntuɓi Cibiyar Tallafawa Fasaha ta hanyar websaiti a www.microchip.com/support. Ambaci lambar Sashe na Na'urar FPGA, zaɓi nau'in shari'ar da ta dace, da ƙaddamar da ƙira files yayin ƙirƙirar shari'ar tallafin fasaha.
Tuntuɓi Sabis na Abokin Ciniki don tallafin samfur mara fasaha, kamar farashin samfur, haɓaka samfur, sabunta bayanai, matsayin tsari, da izini.

• Daga Arewacin Amirka, kira 800.262.1060
• Daga sauran duniya, kira 650.318.4460
• Fax, daga ko'ina cikin duniya, 650.318.8044

Bayanin Microchip
Microchip Website
Microchip yana ba da tallafin kan layi ta hanyar mu websaiti a www.microchip.com/. Wannan webana amfani da site don yin files da bayanai cikin sauƙin samuwa ga abokan ciniki. Wasu daga cikin abubuwan da ake samu sun haɗa da:

• Tallafin samfur - Taswirar bayanai da errata, bayanin kula da aikace-aikace da sampshirye-shirye, albarkatun ƙira, jagororin mai amfani da takaddun tallafi na hardware, sabbin fitattun software da software da aka adana
• Gabaɗaya Taimakon Fasaha - Tambayoyin da ake Yi akai-akai (FAQs), buƙatun tallafin fasaha, ƙungiyoyin tattaunawa kan layi, jerin membobin shirin abokan hulɗa na Microchip
• Kasuwancin Microchip - Mai zaɓin samfur da jagororin ba da oda, sabbin fitowar manema labarai na Microchip, jerin tarukan karawa juna sani da abubuwan da suka faru, jerin ofisoshin tallace-tallace na Microchip, masu rarrabawa da wakilan masana'anta

Sabis ɗin Sanarwa Canjin samfur
Sabis ɗin sanarwar canjin samfur na Microchip yana taimakawa abokan ciniki su kasance a halin yanzu akan samfuran Microchip. Masu biyan kuɗi za su karɓi sanarwar imel a duk lokacin da aka sami canje-canje, sabuntawa, bita ko ƙirƙira masu alaƙa da ƙayyadadden dangin samfur ko kayan aikin haɓaka na ban sha'awa. Don yin rajista, je zuwa www.microchip.com/pcn kuma bi umarnin rajista.

Tallafin Abokin Ciniki
Masu amfani da samfuran Microchip na iya samun taimako ta hanyoyi da yawa:

• Mai Rarraba ko Wakili
• Ofishin Talla na Gida
• Injiniyan Magance Ciki (ESE)
• Goyon bayan sana'a

Abokan ciniki yakamata su tuntuɓi mai rarraba su, wakilin ko ESE don tallafi. Hakanan akwai ofisoshin tallace-tallace na gida don taimakawa abokan ciniki. An haɗa lissafin ofisoshin tallace-tallace da wurare a cikin wannan takaddar. Ana samun tallafin fasaha ta hanyar websaiti a: www.microchip.com/support
Siffar Kariyar Lambar Na'urorin Microchip
Kula da cikakkun bayanai masu zuwa na fasalin kariyar lambar akan samfuran Microchip:

• Samfuran Microchip sun haɗu da ƙayyadaddun bayanai da ke ƙunshe a cikin takamaiman takaddar bayanan Microchip ɗin su.
• Microchip ya yi imanin cewa dangin samfuran sa suna da tsaro lokacin da aka yi amfani da su ta hanyar da aka yi niyya, cikin ƙayyadaddun aiki, da kuma ƙarƙashin yanayi na yau da kullun.
• Ƙimar Microchip kuma tana kare haƙƙin mallaka na fasaha da ƙarfi. Ƙoƙarin keta fasalulluka na kariyar lambar samfurin Microchip an haramta shi sosai kuma yana iya keta dokar haƙƙin mallaka na Millennium Digital.
• Babu Microchip ko duk wani masana'anta na semiconductor ba zai iya tabbatar da amincin lambar sa ba. Kariyar lambar ba yana nufin muna ba da garantin cewa samfurin “ba zai karye ba”. Kariyar lambar tana ci gaba da haɓakawa. Microchip ya himmatu don ci gaba da haɓaka fasalin kariyar lambar samfuranmu.

Sanarwa na Shari'a
Ana iya amfani da wannan ɗaba'ar da bayanin nan tare da samfuran Microchip kawai, gami da ƙira, gwadawa, da haɗa samfuran Microchip tare da aikace-aikacenku. Amfani da wannan bayanin ta kowace hanya ya saba wa waɗannan sharuɗɗan. Bayani game da aikace-aikacen na'ura an bayar da shi ne kawai don jin daɗin ku kuma ana iya maye gurbinsu da sabuntawa. Alhakin ku ne don tabbatar da cewa aikace-aikacenku ya dace da ƙayyadaddun bayananku. Tuntuɓi ofishin tallace-tallace na Microchip na gida don ƙarin tallafi ko, sami ƙarin tallafi a www.microchip.com/en-us/support/design-help/client-support-services.
WANNAN BAYANI AN BAYAR DA MICROCHIP "KAMAR YADDA". MICROCHIP BA YA YI WAKILI KO GARANTIN KOWANE IRIN KOWANE KO BAYANI, RUBUTU KO BAKI, DOKA KO SAURAN BAYANIN BAYANIN HARDA AMMA BAI IYA IYAKA GA WANI GARGADI BA. GAME DA SHAFINSA, KYAUTA, KO AIKINSA. BABU ABUBUWAN DA MICROCHIP ZA SU IYA DOKA GA DUK WANI BAYANI NA MUSAMMAN, HUKUNCI, FASAHA, FASUWA, KO SABODA RASHI, LALACEWA, KUDI, KO KUDI KOWANE IRIN ABINDA YAKE DANGANTA GA BAYANIN KO HARKAR AMFANINSA, YIWU KO LALACEWAR ANA GABA. ZUWA CIKAKKIYAR DOKA, JAMA'AR DOKAR MICROCHIP A KAN DUK DA'AWA A KOWANE HANYA DAKE DANGANTA BAYANI KO AMFANINSA BA ZAI WUCE YAWAN KUDADE BA, IDAN WATA, CEWA KA BIYA GASKIYA GA GADON.
Amfani da na'urorin Microchip a cikin tallafin rayuwa da/ko aikace-aikacen aminci gabaɗaya yana cikin haɗarin mai siye, kuma mai siye ya yarda ya kare, ramuwa da riƙe Microchip mara lahani daga kowane lalacewa, lamuni, kwat da wando, ko kashe kuɗaɗen da aka samu daga irin wannan amfani. Ba a isar da lasisi, a fakaice ko akasin haka, ƙarƙashin kowane haƙƙin mallaka na Microchip sai dai in an faɗi haka.
Alamomin kasuwanci
Sunan Microchip da tambari, tambarin Microchip, Adaptec, AVR, tambarin AVR, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus MediaLB, megaAVR, Microsemi, tambarin Microsemi, MAFI YAWAN tambari, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, tambarin PIC32, PolarFire, Prochip Designer, QTouch, SAM-BA, Sengenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetric , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, da XMEGA alamun kasuwanci ne masu rijista na Microchip Technology Incorporated a cikin Amurka da sauran ƙasashe.
AgileSwitch, ClockWorks, Kamfanin Haɓaka Sarrafa Sarrafa, EtherSynch, Flashtec, Sarrafa Saurin Saurin, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Daidaitaccen Edge, ProASIC, ProASIC Plus, Tambarin ProASIC Plus, Shuru-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, da ZL alamun kasuwanci ne masu rijista na Microchip Technology Incorporated a cikin Amurka
Maɓallin Maɓalli na kusa, AKS, Analog-for-da-Digital Age, Duk wani Capacitor, AnyIn, AnyOut, Ƙaƙwalwar Sauyawa, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM Matsakaicin Matsakaicin Matsala. , DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGAT, In-Circuit Serial Programming, ICSP, INICnet, Daidaitawar hankali, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, MarginryLink maxView, memBrain, Mindi, MiWi, MPASM, MPF, Tambarin Tambarin MPLAB, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Ƙwararren Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, MOS IV, Powerarfin MOS 7, PowerSmart, PureSilicon , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Jimlar Jimiri , Amintaccen Lokaci, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, da ZENA alamun kasuwanci ne na Microchip Technology Incorporated a cikin Amurka da sauran ƙasashe.
SQTP alamar sabis ce ta Microchip Technology Incorporated a cikin Amurka
Alamar Adaptec, Mitar Buƙatu, Fasahar Adana Silicon, da Symmcom alamun kasuwanci ne masu rijista na Microchip Technology Inc. a wasu ƙasashe.
GestIC alamar kasuwanci ce mai rijista ta Microchip Technology Germany II GmbH & Co. KG, reshen Microchip Technology Inc., a wasu ƙasashe.
Duk sauran alamun kasuwanci da aka ambata a nan mallakin kamfanoninsu ne.
2024, Microchip Technology Incorporated da rassanta. Duka Hakkoki.
ISBN: 978-1-6683-0183-8
Tsarin Gudanar da inganci
Don bayani game da Tsarin Gudanar da Ingancin Microchip, da fatan za a ziyarci www.microchip.com/quality.
Kasuwanci da Sabis na Duniya

AMURKA	ASIA/PACIFIC	ASIA/PACIFIC	TURAI
Ofishin Kamfanin 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Goyon bayan sana'a: www.microchip.com/support Web Adireshi: www.microchip.com Atlanta Dulut, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itace, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Ofishin Jakadancin Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Kanada - Toronto Tel: 905-695-1980 Fax: 905-695-2078	Ostiraliya - Sydney Lambar waya: 61-2-9868-6733 China - Beijing Lambar waya: 86-10-8569-7000 China - Chengdu Lambar waya: 86-28-8665-5511 China - Chongqing Lambar waya: 86-23-8980-9588 China - Dongguan Lambar waya: 86-769-8702-9880 China - Guangzhou Lambar waya: 86-20-8755-8029 China - Hangzhou Lambar waya: 86-571-8792-8115 China - Hong Kong SAR Lambar waya: 852-2943-5100 China - Nanjing Lambar waya: 86-25-8473-2460 China - Qingdao Lambar waya: 86-532-8502-7355 China - Shanghai Lambar waya: 86-21-3326-8000 China - Shenyang Lambar waya: 86-24-2334-2829 China - Shenzhen Lambar waya: 86-755-8864-2200 China - Suzhou Lambar waya: 86-186-6233-1526 China - Wuhan Lambar waya: 86-27-5980-5300 China - Xian Lambar waya: 86-29-8833-7252 China - Xiamen Lambar waya: 86-592-2388138 China - Zhuhai Lambar waya: 86-756-3210040	Indiya - Bangalore Lambar waya: 91-80-3090-4444 Indiya - New Delhi Lambar waya: 91-11-4160-8631 Indiya - Pune Lambar waya: 91-20-4121-0141 Japan - Osaka Lambar waya: 81-6-6152-7160 Japan - Tokyo Lambar waya: 81-3-6880-3770 Koriya - Daegu Lambar waya: 82-53-744-4301 Koriya - Seoul Lambar waya: 82-2-554-7200 Malaysia - Kuala Lumpur Lambar waya: 60-3-7651-7906 Malaysia - Penang Lambar waya: 60-4-227-8870 Philippines - Manila Lambar waya: 63-2-634-9065 Singapore Lambar waya: 65-6334-8870 Taiwan - Hsin Chu Lambar waya: 886-3-577-8366 Taiwan - Kaohsiung Lambar waya: 886-7-213-7830 Taiwan - Taipei Lambar waya: 886-2-2508-8600 Thailand - Bangkok Lambar waya: 66-2-694-1351 Vietnam - Ho Chi Minh Lambar waya: 84-28-5448-2100	Ostiriya - Wels Lambar waya: 43-7242-2244-39 Saukewa: 43-7242-2244-393 Denmark - Copenhagen Lambar waya: 45-4485-5910 Fax: 45-4485-2829 Finland - Espoo Lambar waya: 358-9-4520-820 Faransa - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Jamus - Garching Lambar waya: 49-8931-9700 Jamus - Han Lambar waya: 49-2129-3766400 Jamus - Heilbronn Lambar waya: 49-7131-72400 Jamus - Karlsruhe Lambar waya: 49-721-625370 Jamus - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Jamus - Rosenheim Lambar waya: 49-8031-354-560 Isra'ila - Hod Hasharon Lambar waya: 972-9-775-5100 Italiya - Milan Lambar waya: 39-0331-742611 Fax: 39-0331-466781 Italiya - Padova Lambar waya: 39-049-7625286 Netherlands - Drunen Lambar waya: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Lambar waya: 47-72884388 Poland - Warsaw Lambar waya: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Lambar waya: 46-8-5090-4654 UK - Wokingham Lambar waya: 44-118-921-5800 Saukewa: 44-118-921-5820

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