PolarFire Family FPGA Custom Flow User Guide
Libero SoC v2024.2

Chiyambi (Funsani Funso)

Pulogalamu ya Libero System-on-Chip (SoC) imapereka malo ophatikizika a Field Programmable Gate Array (FPGA). Komabe, ogwiritsa ntchito ochepa angafune kugwiritsa ntchito kaphatikizidwe ka chipani chachitatu ndi zida zoyerekeza kunja kwa chilengedwe cha Libero SoC. Libero tsopano ikhoza kuphatikizidwa m'malo opangira FPGA. Ndikofunikira kugwiritsa ntchito Libero SoC kuyang'anira mawonekedwe onse a FPGA.
Bukuli limafotokoza za Custom Flow ya zida za PolarFire ndi PolarFire SoC Family, njira yophatikizira Libero ngati gawo lalikulu la mapangidwe a FPGA. Supported Device Families® Gome lotsatirali limatchula mabanja omwe Libero SoC amathandizira. Komabe, zina zomwe zili mu bukhuli zitha kugwira ntchito pazida zinazake zokha. Pankhaniyi, chidziwitso choterocho chimadziwika bwino.
Table 1. Chipangizo Mabanja Othandizidwa ndi Libero SoC

Chipangizo Banja	Kufotokozera
PolarFire®	PolarFire FPGAs imapereka mphamvu zotsika kwambiri pamsika pakachulukidwe kapakati ndi chitetezo chapadera komanso kudalirika.
PolarFire SoC	PolarFire SoC ndiye SoC FPGA yoyamba yokhala ndi gulu lodziwikiratu, logwirizana la RISC-V CPU, komanso makina okumbukira a L2 omwe amathandizira Linux® ndi kugwiritsa ntchito nthawi yeniyeni.

Zathaview (Funsani Funso)

Ngakhale Libero SoC imapereka malo ophatikizika akumapeto-kumapeto kuti apange mapangidwe a SoC ndi FPGA, imaperekanso kusinthika koyendetsa kaphatikizidwe ndikuyerekeza ndi zida za chipani chachitatu kunja kwa chilengedwe cha Libero SoC. Komabe, njira zina zopangira ziyenera kukhalabe mkati mwa malo a Libero SoC.
Gome lotsatirali likulemba masitepe akuluakulu pamapangidwe a FPGA ndikuwonetsa masitepe omwe Libero SoC iyenera kugwiritsidwa ntchito.
Gulu 1-1. FPGA Design Flow

Design Flow Step	Muyenera Kugwiritsa Ntchito Libero	Kufotokozera
Zolemba Zopanga: HDL	Ayi	Gwiritsani ntchito chida chachitatu cha HDL chowongolera / choyang'anira kunja kwa Libero® SoC ngati mukufuna.
Kulowa kwa Design: Configurators	Inde	Pangani pulojekiti yoyamba ya Libero yopangira magawo amtundu wa IP.
Kupanga zoletsa za PDC/SDC zokha	Ayi	Zolepheretsa zotengedwa zimafunikira HDL yonse files ndi derive_constraints zofunikira zikachitidwa kunja kwa Libero SoC, monga momwe zafotokozedwera mu Zowonjezera C-Derive Constraints.
Kuyerekezera	Ayi	Gwiritsani ntchito chida chachitatu kunja kwa Libero SoC, ngati mukufuna. Pamafunika kutsitsa malaibulale oyerekeza omwe adasanjidwa kale pazida zomwe mukufuna, choyimira chandamale, ndi mtundu wa Libero womwe umagwiritsidwa ntchito pokhazikitsa kumbuyo.
Kaphatikizidwe	Ayi	Gwiritsani ntchito chida chachitatu kunja kwa Libero SoC ngati mukufuna.
Kukhazikitsa Mapangidwe: Sinthani Zolepheretsa, Lembani Netlist, Malo ndi Njira (onani Kupitiliraview)	Inde	Pangani pulojekiti yachiwiri ya Libero kuti mugwiritse ntchito backend.
Nthawi ndi Kutsimikizira Mphamvu	Inde	Khalani mu projekiti yachiwiri ya Libero.
Konzani Deta Yoyambira Yoyambira ndi Zokumbukira	Inde	Gwiritsani ntchito chida ichi kuti muyang'anire mitundu yosiyanasiyana ya kukumbukira ndikuyambitsa mapangidwe mu chipangizocho. Khalani mu projekiti yachiwiri.
Kupanga mapulogalamu File M'badwo	Inde	Khalani mu projekiti yachiwiri.

Chofunika: Inu ayenera kukopera precompiled malaibulale kupezeka pa PreCompiled Simulation Library tsamba kuti mugwiritse ntchito choyimira chipani chachitatu.
Mukuyenda koyera kwa Nsalu FPGA, lowetsani kapangidwe kanu pogwiritsa ntchito HDL kapena schematics ndikudutsa mwachindunji
ku zida za synthesis. Kuthamanga kumathandizidwabe. PolarFire ndi PolarFire SoC FPGAs ali ndi zofunikira
midadada yolimba ya IP yomwe imafuna kugwiritsa ntchito ma cores (SgCores) kuchokera ku Libero SoC IP
ndandanda. Kusamalira mwapadera kumafunika pazitsulo zilizonse zomwe zimakhala ndi ntchito za SoC:

• PolarFire
  – PF_UPROM
  - PF_SYSTEM_SERVICES
  - PF_CCC
  - PF CLK DIV
  – PF_CRIPTO
  – PF_DRI
  - PF_INIT_MONITOR
  – PF_NGMUX
  - PF_OSC
  - Ma RAM (TPSRAM, DPSRAM, URAM)
  - PF_SRAM_AHBL_AXI
  - PF_XCVR_ERM
  - PF_XCVR_REF_CLK
  - PF_TX_PLL
  – PF_PCIE
  – PF_IO
  - PF_IOD_CDR
  - PF_IOD_CDR_CCC
  - PF_IOD_GENERIC_RX
  - PF_IOD_GENERIC_TX
  - PF_IOD_GENERIC_TX_CCC
  - PF_RGMII_TO_GMII
  - PF_IOD_OCTAL_DDR
  - PF_DDR3
  - PF_DDR4
  - PF_LPDDR3
  – PF_QDR
  - PF_CORSMARTBERT
  – PF_TAMPER
  - PF_TVS, ndi zina zotero.

Kuphatikiza pa SgCores zomwe zatchulidwa kale, pali ma IP ambiri ofewa a DirectCore omwe amapezeka kwa mabanja a zida za PolarFire ndi PolarFire SoC mu Libero SoC Catalog yomwe imagwiritsa ntchito zida za nsalu za FPGA.
Kuti mulowe m'mapangidwe, ngati mugwiritsa ntchito chimodzi mwazinthu zomwe zapitazi, muyenera kugwiritsa ntchito Libero SoC ngati gawo lazolowera (Component Configuration), koma mutha kupitiliza zotsala za Design Entry yanu (HDL kulowa, ndi zina zotero) kunja kwa Libero. Kuti muwongolere kayendedwe ka FPGA kunja kwa Libero, tsatirani njira zomwe zaperekedwa mu bukhuli.
1.1 Gawo la Moyo Wozungulira (Funsani Funso)
Masitepe otsatirawa akufotokoza za moyo wa gawo la SoC ndikupereka malangizo amomwe angagwiritsire ntchito deta.

1. Pangani chigawocho pogwiritsa ntchito kasinthidwe kake mu Libero SoC. Izi zimapanga mitundu iyi ya data:
   - HDL files
   - Memory files
   - Kulimbikitsa ndi Kuyerekezera files
   - Gawo la SDC file
2. Za HDL files, yambitsani ndikuwaphatikiza muzotsalira zonse za HDL pogwiritsa ntchito chida chakunja cholowera / njira.
3. Perekani kukumbukira files ndi zolimbikitsa files ku chida chanu choyerekeza.
4. Gawo la SDC file kuti mupeze chida cha Constraint cha Constraint Generation. Onani Zowonjezera C—Derive Constraints kuti mumve zambiri.
5. Muyenera kupanga pulojekiti yachiwiri ya Libero, komwe mumalowetsa mndandanda wa post-Synthesis ndi metadata yanu, motero mumamaliza kugwirizana pakati pa zomwe mudapanga ndi zomwe mumakonza.

1.2 Libero SoC Project Creation (Funsani Funso)
Njira zina zamapangidwe ziyenera kuyendetsedwa mkati mwa chilengedwe cha Libero SoC (Table 1-1). Kuti izi zitheke, muyenera kupanga ma projekiti awiri a Libero SoC. Pulojekiti yoyamba imagwiritsidwa ntchito pokonzekera chigawo chokonzekera ndi kupanga, ndipo polojekiti yachiwiri ndiyo kukhazikitsa mwakuthupi kapangidwe kapamwamba.
1.3 Kuyenda Mwamakonda (Funsani Funso)
Chithunzi chotsatira chikuwonetsa:

• Libero SoC ikhoza kuphatikizidwa ngati gawo lalikulu la mapangidwe a FPGA oyenda ndi kaphatikizidwe ka chipani chachitatu ndi zida zoyeserera kunja kwa chilengedwe cha Libero SoC.
• Masitepe osiyanasiyana omwe amakhudzidwa ndikuyenda, kuyambira pakupanga mapangidwe ndi kusokera mpaka kupanga pulogalamu.
• Kusinthana kwa data (zolowera ndi zotuluka) zomwe ziyenera kuchitika pagawo lililonse lamayendedwe.

Langizo:

1. SNVM.cfg, UROMM.cfg
2. *.mu file m'badwo wa Kuyerekeza: pa4rtupromgen.exe imatenga UPROM.cfg monga cholowera ndikupanga UPROM.mem.

Nawa masitepe mumayendedwe okhazikika:

1. Kapangidwe kagawo ndi kupanga:
   a. Pangani pulojekiti yoyamba ya Libero (kuti ikhale Project Reference).
   b. Sankhani Core ku Catalog. Dinani kawiri pachimake kuti mupatse dzina lachigawo ndikusintha gawolo.
   Izi zimatumiza deta yamagulu ndi files. Ma Component Manifest amapangidwanso. Onani Zowonetsera Zachigawo kuti mumve zambiri. Kuti mudziwe zambiri, onani Kukonzekera Kwachigawo.
2. Malizitsani mapangidwe anu a RTL kunja kwa Libero:
   a. Yambitsani chigawo cha HDL files.
   b. Malo a HDL files yalembedwa mu Component Manifests files.
3. Pangani zolepheretsa za SDC za zigawozo. Gwiritsani ntchito zida za Derive Constraints kuti mupange zoletsa nthawi file(SDC) kutengera:
   a. Chigawo cha HDL files
   b. Chithunzi cha SDC files
   c. Wogwiritsa HDL files
   Kuti mumve zambiri, onani Zowonjezera C—Derive Constraints.
4. Chida chophatikizira/chida choyerekeza:
   a. Pezani HDL files, zolimbikitsa files, ndi zidziwitso za zigawo zochokera kumalo enieni monga momwe zasonyezedwera mu Component Manifests.
   b. Gwirizanitsani ndikuyerekeza kapangidwe kake ndi zida za chipani chachitatu kunja kwa Libero SoC.
5. Pangani Libero Project yanu yachiwiri (Implementation).
6. Chotsani kaphatikizidwe kuchokera pamakina opangira zida zamapangidwe (Pulojekiti> Zokonda Pulojekiti> Kuyenda Kwamapangidwe> chotsani bokosi la Yambitsani Synthesis).
7. Tengani gwero la mapangidwe files (post-synthesis *.vm netlist kuchokera ku chida chophatikizira):
   - Lowetsani post-synthesis *.vm netlist (File> Import> Synthesized Verilog Netlist (VM)).
   - Zigawo za metadata * .cfg files za uPROM ndi/kapena sNVM.
8. Lowetsani gawo lililonse la Libero SoC block files. Mpanda files ayenera kukhala mu *.cxz file mtundu.
   Kuti mudziwe zambiri za momwe mungapangire chipika, onani PolarFire Block Flow User Guide.
9. Lowetsani zopinga zamapangidwe:
   - Lowetsani I/O zoletsa files (Constraints Manager> I/OAttributes> Import).
   – Lowetsani kupanga pansi *.pdc files (Constraints Manager> Floor Planner> Import).
   - Lowetsani *.sdc choletsa nthawi files (Constraints Manager> Nthawi> Kulowetsa). Tengani SDC file zopangidwa kudzera mu chida cha Derive Constraint.
   – Lowetsani *.ndc zoletsa files (Constraints Manager> NetlistAttributes> Import), ngati zilipo.
10. Kukakamiza file ndi mgwirizano wa zida
    - Mu Constraint Manager, gwirizanitsani ndi *.pdc files kuyika ndi njira, *.sdc files kuyika ndi njira ndi zitsimikizo za nthawi, ndi *.ndc files kuti Pangani Netlist.
11. Kukonzekera komaliza
    - Malo ndi njira, tsimikizirani nthawi ndi mphamvu, sinthani deta yoyambira ndi zokumbukira, ndi mapulogalamu file m'badwo.
12. Tsimikizirani kapangidwe kake
    - Tsimikizirani kapangidwe kake pa FPGA ndikuwongolera ngati kuli kofunikira pogwiritsa ntchito zida zopangira zoperekedwa ndi Libero SoC design suite.

Kusintha kwagawo (Funsani Funso)

Gawo loyamba pamayendedwe oyenda ndikukonza zida zanu pogwiritsa ntchito projekiti ya Libero (yomwe imatchedwanso pulojekiti yoyamba ya Libero mu Table 1-1). Mumasitepe otsatirawa, mumagwiritsa ntchito deta kuchokera ku polojekitiyi.
Ngati mukugwiritsa ntchito zigawo zilizonse zomwe zatchulidwa kale, pansi pa Overview m'mapangidwe anu, chitani njira zomwe zafotokozedwa m'gawoli.
Ngati simukugwiritsa ntchito chilichonse mwazinthu zomwe zili pamwambapa, mutha kulemba RTL yanu kunja kwa Libero ndikuyilowetsa mwachindunji ku zida zanu za Synthesis ndi Simulation. Kenako mutha kupita ku gawo la kaphatikizidwe ndikungolowetsani positi-kaphatikizidwe *.vm netlist mu projekiti yanu yomaliza ya Libero (yomwe imatchedwanso pulojekiti yachiwiri ya Libero mu Table 1-1).
2.1 Kukonzekera Kwachigawo Pogwiritsa Ntchito Libero (Funsani Funso)
Mukasankha zigawo zomwe ziyenera kugwiritsidwa ntchito pamndandanda wapitawu, chitani izi:

1. Pangani pulojekiti yatsopano ya Libero (Core Configuration and Generation): Sankhani Chipangizo ndi Banja zomwe mukufuna kutsata mapangidwe anu omaliza.
2. Gwiritsani ntchito imodzi kapena zingapo zomwe zatchulidwa mu Custom Flow.
   a. Pangani SmartDesign ndikusintha maziko omwe mukufuna ndikukhazikitsa mu gawo la SmartDesign.
   b. Limbikitsani mapini onse kuti akhale apamwamba.
   c. Pangani SmartDesign.
   d. Dinani kawiri chida cha Simulate (chilichonse mwa Pre-Synthesis kapena Post-Synthesis kapena Post-Layout) kuti mupemphe choyimira. Mutha kutuluka mu simulator mutayitanidwa. Sitepe iyi imapanga kayeseleledwe filendizofunikira pa polojekiti yanu.

Tip: Inu muyenera kuchita izi ngati mukufuna kutengera kapangidwe kanu kunja kwa Libero.
Kuti mudziwe zambiri, onani Simulating Your Design.
e. Sungani polojekiti yanu-iyi ndi pulojekiti yanu yowonetsera.
2.2 Ziwonetsero zamagulu (Funsani Funso)
Mukapanga zigawo zanu, seti ya files imapangidwa pagawo lililonse. Lipoti la Component Manifest limafotokoza za files amapangidwa ndikugwiritsidwa ntchito mu sitepe iliyonse yotsatira (Kaphatikizidwe, Simulation, Firmware Generation, ndi zina zotero). Lipotili limakupatsani malo azinthu zonse zopangidwa files zofunika kuti mupitirize ndi Custom Flow. Mutha kupeza mawonekedwe agawo m'dera la Malipoti: Dinani Kupanga> Malipoti kuti mutsegule tabu ya Malipoti. Patsamba la Malipoti, mukuwona gulu la manifest.txt files (Paview), imodzi pagawo lililonse lomwe mwapanga.
Langizo: Muyenera kukhazikitsa gawo kapena gawo ngati '"root"' kuti muwone chiwonetsero chachigawocho file zomwe zili pagawo la Reports.
Kapenanso, mutha kupeza lipoti lamunthu payekha files pagawo lililonse lopangidwa kapena SmartDesign gawo kuchokera /gawo/ntchito/ / / _manifest.txt kapena /gawo/ntchito/ / _manifest.txt. Mukhozanso kupeza chiwonetsero chazithunzi file Zomwe zili mugawo lililonse lopangidwa kuchokera ku tabu yatsopano ya Components ku Libero, komwe file malo amatchulidwa ponena za chikwatu cha polojekiti.Yang'anani pa malipoti otsatirawa a Component Manifest:

• Ngati mudayika ma cores mu SmartDesign, werengani file _manifest.txt.
• Ngati mudapanga zigawo za ma cores, werengani _manifest.txt.

Muyenera kugwiritsa ntchito malipoti onse a Component Manifest omwe amagwira ntchito pamapangidwe anu. Za example, ngati polojekiti yanu ili ndi SmartDesign yokhala ndi gawo limodzi kapena zingapo zoyambira momwemo ndipo mukufuna kuzigwiritsa ntchito pomaliza, muyenera kusankha. files zotchulidwa mu Malipoti a Component Manifests a zigawo zonsezo kuti mugwiritse ntchito popanga mapangidwe anu.
2.3 Kutanthauzira Mawonekedwe Files (Funsani Funso)
Mukatsegula chiwonetsero chachigawo file, mukuwona njira zopita files mu projekiti yanu ya Libero ndi zolozera za komwe mumapangidwira kuti muzigwiritsa ntchito. Mutha kuwona mitundu yotsatirayi files mu chiwonetsero file:

• Chithunzi cha HDL files pa zida zonse za Synthesis ndi Simulation
• Zolimbikitsa files pazida zonse za Simulation
• Kukakamiza files

Chotsatira ndi Chiwonetsero Chachigawo cha PolarFire core chigawo.Mtundu uliwonse wa file ndizofunika kutsika mumayendedwe anu opangira. Magawo otsatirawa akufotokoza kusakanikirana kwa files kuchokera pachiwonetsero kupita kumapangidwe anu.

Constraint Generation (Funsani Funso)

Mukamapanga masinthidwe ndi kupanga, onetsetsani kuti mwalemba / kupanga zoletsa za SDC/PDC/NDC files kuti mapangidwewo awaperekeze ku Synthesis, Place-and-Route, ndi Verify Time zida.
Gwiritsani ntchito zida za Derive Constraints kunja kwa malo a Libero kuti mupange zopinga m'malo mozilemba pamanja. Kuti mugwiritse ntchito chida cha Derive Constraint kunja kwa malo a Libero, muyenera:

• Perekani osuta HDL, chigawo cha HDL, ndi zoletsa za SDC files
• Tchulani gawo lapamwamba kwambiri
• Tchulani malo oti mupangire zopinga zomwe zatengedwa files

Zoletsa za gawo la SDC zilipo pansi /gawo/ntchito/ / / chikwatu pambuyo pa kasinthidwe kagawo ndi kupanga.
Kuti mumve zambiri za momwe mungapangire zolepheretsa pakupanga kwanu, onani Zowonjezera C—Derive Constraints.

Kupanga Mapangidwe Anu (Funsani Funso)

Chimodzi mwazinthu zazikulu za Custom Flow ndikukulolani kuti mugwiritse ntchito kaphatikizidwe ka chipani chachitatu
chida kunja kwa Libero. Kuthamanga kwachizolowezi kumathandizira kugwiritsa ntchito Synopsys SynplifyPro. Kuti synthesize wanu
Pulogalamuyi, gwiritsani ntchito njira zotsatirazi:

1. Pangani pulojekiti yatsopano mu chida chanu cha Synthesis, kulunjika ku banja lazida zomwezo, kufa, ndi phukusi monga pulojekiti ya Libero yomwe mudapanga.
   a. Tengani RTL yanuyanu filemonga momwe mumachitira.
   b. Khazikitsani zotsatira za Synthesis kukhala Structural Verilog (.vm).
   Langizo: Zomangamanga Verilog (.vm) ndiye mtundu wokhawo wothandizidwa ndi kaphatikizidwe mu PolarFire.
2. Lowetsani Chigawo cha HDL files mu projekiti yanu ya Synthesis:
   a. Pa Chigawo chilichonse Lipoti la Manifests: Pa chilichonse file pansi pa HDL source files pa zida zonse za Synthesis ndi Simulation, lowetsani file mu Synthesis Project yanu.
3. Tengani katundu wa file polarfire_syn_comps.v (ngati mukugwiritsa ntchito Synopsys Synplify) kuchokera
   Malo oyika>/data/aPA5M ku projekiti yanu ya Synthesis.
4. Tengani SDC yopangidwa kale file kudzera mu chida cha Derived Constraint (onani Zowonjezera
   A—Sample SDC Constraints) mu chida cha Synthesis. Choletsa ichi file Imalepheretsa chida chophatikizira kuti chitheke kutseka nthawi ndikuchita khama komanso kubwereza kocheperako.

Zofunika: 

• Ngati mukufuna kugwiritsa ntchito *.sdc file kukakamiza Malo-ndi-Njira panthawi yokonza mapangidwe, muyenera kulowetsa izi *.sdc mu pulojekiti ya kaphatikizidwe. Izi ndikuwonetsetsa kuti palibe dzina lachinthu losafananira pamndandanda wopangidwa komanso zopinga za Malo-ndi-Njira panthawi yokhazikitsa dongosolo. Ngati simuphatikiza izi *.sdc file mu sitepe ya Synthesis, netlist yopangidwa kuchokera ku Synthesis ikhoza kulephera sitepe ya Malo ndi Njira chifukwa cha kusagwirizana kwa dzina lachinthu.
  a. Lowetsani Netlist Attributes *.ndc, ngati alipo, mu chida cha Synthesis.
  b. Thamanga Synthesis.
• Malo omwe chida chanu cha Synthesis chidatulutsa chili ndi *.vm netlist file zopangidwa positi Synthesis. Muyenera kulowetsa mndandanda mu Libero Implementation Project kuti mupitilize kupanga.

Kutengera Mapangidwe Anu (Funsani Funso)

Kuti muyesere kapangidwe kanu kunja kwa Libero (ndiko kuti, kugwiritsa ntchito malo anu oyerekeza ndi oyeserera), chitani izi:

1. Kupanga Files:
   a. Pre-Synthesis kayeseleledwe:
   • Lowetsani RTL yanu mu projekiti yanu yoyerekeza.
   • Pa Chigawo chilichonse cha Lipoti la Manifests.
   - Lowetsani chilichonse file pansi pa HDL source files pa zida zonse za Synthesis ndi Simulation mu projekiti yanu yoyeserera.
   • Lembani izi files monga mwa malangizo a simulator yanu.
   b. Kayeseleledwe ka pambuyo kaphatikizidwe:
   • Lowetsani post-synthesis *.vm netlist yanu (yopangidwa mu Synthesizing Your Design) mu projekiti yanu yofananira ndikuipanga.
   c. Kayeseleledwe kazithunzi:
   • Choyamba, malizitsani kugwiritsa ntchito mapangidwe anu (onani Kukhazikitsa Mapangidwe Anu). Onetsetsani kuti pulojekiti yanu yomaliza ya Libero ili m'malo osinthidwa.
   • Dinani kawiri Pangani BackAnnotated Files pawindo la Libero Design Flow. Zimapanga ziwiri files:
   / wopanga/ / _ba.v/vhd / wopanga/
   / _ba.sdf
   • Tengani zonse ziwirizi files mu chida chanu choyerekeza.
2. Kulimbikitsa ndi Kukonzekera files:
   a. Pa Lipoti la Chigawo chilichonse cha Manifests:
   • Lembani zonse files pansi pa Stimulus Files m'magawo onse a Zida Zoyeserera kugawo lachikwatu cha polojekiti yanu Yoyeserera.
   b. Onetsetsani kuti Tcl iliyonse files m'mindandanda yapitayi (mu gawo 2.a) amachitidwa poyamba, asanayambe kuyerekezera.
   c. UPROM.mem: Ngati mugwiritsa ntchito UPROM pachimake pakupanga kwanu ndi mwayi Gwiritsani ntchito zomwe zili zofananira zomwe zimathandizidwa ndi kasitomala mmodzi kapena angapo omwe mukufuna kutengera, muyenera kugwiritsa ntchito pa4rtupromgen (pa4rtupromgen.exe pa windows) kuti mupange UPROM.mem file. The pa4rtupromgen executable amatenga UPROM.cfg file monga zolowetsa kudzera mu Tcl script file ndi kutulutsa UROMM.mem file chofunika poyerekezera. Izi UROMM.mem file ziyenera kukopera ku chikwatu kayeseleledwe isanayambe kayeseleledwe kuthamanga. Example kusonyeza pa4rtupromgen ntchito executable waperekedwa mu njira zotsatirazi. The UROM.cfg file likupezeka m'ndandanda /gawo/ntchito/ / mu projekiti ya Libero yomwe mudagwiritsa ntchito popanga gawo la UPROM.
   d. snvm.mem: Ngati mumagwiritsa ntchito System Services pachimake pakupanga kwanu ndikukonza tabu ya sNVM pachimake ndi kusankha Gwiritsani ntchito zomwe zili zofananira zomwe zathandizira kasitomala m'modzi kapena angapo omwe mukufuna kutengera, snvm.mem file imapangidwa zokha kuti
   ndandanda /gawo/ntchito/ / mu projekiti ya Libero yomwe mudagwiritsa ntchito kupanga gawo la System Services. Izi snvm.mem file ziyenera kukopera ku chikwatu kayeseleledwe isanayambe kayeseleledwe kuthamanga.
3. Pangani chikwatu chogwira ntchito ndi chikwatu chaching'ono chotchedwa kuyerekezera pansi pa chikwatu chogwira ntchito.
   The pa4rtupromgen executable kuyembekezera kukhalapo kwa kayeseleledwe kakang'ono chikwatu mu chikwatu ntchito ndi * .tcl script anaika mu kayeseleledwe kagawo kagawo.
4. Koperani UROMM.cfg file kuchokera ku pulojekiti yoyamba ya Libero yomwe idapangidwa kuti ipange gawo mufoda yogwira ntchito.
5. Matani malamulo otsatirawa mu *.tcl script ndikuyiyika mufoda yoyeserera yopangidwa mu gawo 3.
   Sample *.tcl ya zida za PolarFire ndi PolarFire Soc Family kuti mupange URPOM.mem file
   kuchokera ku UROM.cfg
   set_device -fam -kufa -pkg
   set_input_cfg -njira
   set_sim_mem -njiraFile/UPROM.mem>
   gen_sim -use_init zabodza
   Kuti mugwiritse ntchito dzina lamkati loyenera, onani *.prjx file ya projekiti yoyamba ya Libero (yomwe imagwiritsidwa ntchito popanga chigawo).
   Mtsutso use_init uyenera kusinthidwa kukhala zabodza.
   Gwiritsani ntchito lamulo la set_sim_mem kuti mufotokoze njira yopitira file UPROM.mem ndiye
   zidapangidwa pakukhazikitsa script file ndi pa4rtupromgen executable.
6. Pa command prompt kapena cygwin terminal, pitani ku bukhu logwira ntchito lomwe lapangidwa mu gawo 3.
   Perekani lamulo la pa4rtupromgen ndi-script njira ndipo perekani kwa izo *.tcl script yopangidwa mu sitepe yapitayi.
   Za Windows
   /designer/bin/pa4rtupromgen.exe \
   -script./simulation/ .tcl
   Za Linux:
   /bin/pa4rtupromgen
   -script./simulation/ .tcl
7. Pambuyo pochita bwino pa4rtupromgen executable, onetsetsani kuti UPROM.mem file imapangidwa pamalo otchulidwa mu lamulo la set_sim_mem mu *.tcl script.
8. Kuti muyesere sNVM, lembani fayilo ya snvm.mem file kuchokera ku pulojekiti yanu yoyamba ya Libero (yomwe imagwiritsidwa ntchito pokonza chigawo) kupita ku chikwatu chapamwamba choyerekeza cha pulojekiti yanu yoyeserera kuti muyesere (kunja kwa Libero SoC). Kuti muyese zomwe zili mu UROMM, koperani UROMM.mem file mu chikwatu chapamwamba choyerekeza cha projekiti yanu yoyeserera kuti muyendetse kayeseleledwe (kunja kwa Libero SoC).

Chofunika: Ku tsanzirani magwiridwe antchito a SoC Components, tsitsani malaibulale oyeserera a PolarFire ndikulowetsa m'malo oyeserera monga momwe tafotokozera apa. Kuti mumve zambiri, onani Zakumapeto B—Importing Simulation Libraries into Simulation Environment.

Kukhazikitsa Mapangidwe Anu (Funsani Funso)

Mukamaliza kayeseleledwe ka Synthesis ndi Post-Synthesis m'dera lanu, muyenera kugwiritsa ntchito Libero kachiwiri kuti mugwiritse ntchito mapangidwe anu, kuyendetsa nthawi ndi kusanthula mphamvu, ndikupanga mapulogalamu anu. file.

1. Pangani pulojekiti yatsopano ya Libero kuti mukhazikitse mwakuthupi ndikusintha kapangidwe kake. Onetsetsani kuti mwalunjika pa chipangizo chomwe chili mu pulojekiti yomwe mudapanga mu Component Configuration.
2. Pambuyo popanga pulojekiti, chotsani kaphatikizidwe kuchokera pazida pawindo la Design Flow (Pulojekiti> Zokonda za Pulojekiti> Kuyenda kwa Mapangidwe> Osayang'ana Yambitsani Synthesis).
3.  Lowetsani kaphatikizidwe kanu *.vm file mu polojekiti iyi, (File > Tengani > Synthesized Verilog Netlist (VM)).
   Langizo: Ndibwino kuti mupange ulalo wa izi file, kotero kuti ngati mukonzanso mapangidwe anu, Libero nthawi zonse amagwiritsa ntchito mndandanda waposachedwa wa post-synthesis.
   a. Muwindo la Design Hierarchy, onani dzina la gawo la mizu.
4. Lowetsani zopinga mu polojekiti ya Libero. Gwiritsani ntchito Constraint Manager kuti mulowetse *.pdc/*.sdc/*.ndc contraints.
   a. Lowetsani I/O *.pdc zoletsa files (Constraints Manager> Makhalidwe a I/O> Import).
   b. Tengani Floorplanning *.pdc constraint files (Constraints Manager> Floor Planner> Import).
   c. Lowetsani *.sdc kuletsa nthawi files (Constraints Manager> Nthawi> Lowani). Ngati mapangidwe anu ali ndi ma cores omwe alembedwa mu Overview, onetsetsani kuti mukulowetsa SDC file zopangidwa ndi dereive contraindication.
   d. Lowetsani *.ndc zoletsa files (Constraints Manager> Netlist Attributes> Import).
5. Zoletsa Zogwirizana Files kupanga zida.
   a. Tsegulani Constraint Manager (Sinthani Zoletsa> Tsegulani Zoletsa View).
   Chongani bokosi la Malo-ndi-Njira ndi Kutsimikizira Nthawi pafupi ndi cholepheretsa file kukhazikitsa zopinga file ndi mgwirizano wa zida. Gwirizanitsani *.pdc kuletsa kwa Place-andRoute ndi *.sdc ku Zonse-ndi-Njira ndi Kutsimikizira Nthawi. Gwirizanitsani ndi *.ndc file kuti Pangani Netlist.
   Langizo: Ngati Malo ndi Njira zikulephera ndi *.sdc contraindication file, kenako lowetsani zomwezi *.sdc file kuti kaphatikizidwe ndi kuyambitsanso kaphatikizidwe.
6. Dinani Pangani Netlist ndiyeno Place and Route kuti mumalize masanjidwewo.
7. Chida cha Configure Design Initialization Data and Memories chimakupatsani mwayi woyambitsa midadada yamapangidwe, monga LSRAM, µSRAM, XCVR (transceivers), ndi PCIe pogwiritsa ntchito data yosungidwa mu µPROM, sNVM, kapena SPI Flash memory memory. Chidachi chili ndi ma tabu otsatirawa pofotokozera ndondomeko ya ndondomeko yoyambira mapangidwe, ndondomeko ya makasitomala oyambira, makasitomala ogwiritsira ntchito deta.
   - Design Initialization tabu
   - µPROM tabu
   - sNVM tabu
   - SPI Flash tabu
   - Zida za RAMs tabu
   Gwiritsani ntchito ma tabu omwe ali pachidacho kuti mukonze zoyambira zoyambira ndi kukumbukira.Mukamaliza kasinthidwe, chitani zotsatirazi kuti mukonze zoyambira:
   • Pangani makasitomala oyambitsa
   • Pangani kapena katundu bitstream
   • Lembani chipangizocho
   Kuti mumve zambiri zamomwe mungagwiritsire ntchito chida ichi, onani Libero SoC Design Flow User Guide. Kuti mumve zambiri pamalamulo a Tcl omwe amagwiritsidwa ntchito pokonza ma tabo osiyanasiyana mu chida ndikufotokozera kasinthidwe ka kukumbukira files (*.cfg), onani Tcl Commands Reference Guide.
8. Pangani Pulogalamu File kuchokera ku polojekitiyi ndikugwiritsa ntchito kukonza FPGA yanu.

Zakumapeto A—SampZoletsa za SDC (Funsani Funso

Libero SoC imapanga zoletsa za SDC zamtundu wina wa IP, monga CCC, OSC, Transceiver ndi zina zotero. Kudutsa zopinga za SDC popanga zida kumawonjezera mwayi wotseka nthawi ndikuchita khama komanso kubwereza kocheperako. Njira yathunthu yotsatizana kuchokera pamlingo wapamwamba imaperekedwa pazinthu zonse zamapangidwe zomwe zafotokozedwa muzoletsa.
7.1 Zolepheretsa Nthawi ya SDC (Funsani Funso)
Mu Libero IP core reference projekiti, chopinga chapamwamba cha SDC ichi file imapezeka kuchokera kwa Constraint Manager (Design Flow> Open Manage Constraint View > Nthawi > Pezani Zolepheretsa).
Zofunika: Onani izi file kukhazikitsa zoletsa za SDC ngati mapangidwe anu ali ndi CCC, OSC, Transceiver, ndi zina. Sinthani njira zonse zotsogola, ngati kuli kofunikira, kuti zigwirizane ndi kapangidwe kanu kapena gwiritsani ntchito Derive_Constraints ndi masitepe mu Zowonjezera C—Derive Constraints pagawo la SDC file.
Sungani the file ku dzina lina ndikulowetsa SDC file ku chida chophatikizira, Chida cha Malo-ndi-Njira, ndi Kutsimikizira Nthawi, monga zopinga zilizonse za SDC files.
7.1.1 Derived SDC File (Funsani Funso)
#Izi file adapangidwa kutengera gwero lotsatira la SDC files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
TRANSMIT_PLL/TRANSMIT_PLL_0/TRANSMIT_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PCIE_INITIATOR/PCIE_INITIATOR_0/PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** Zosintha zilizonse pa izi file zidzatayika ngati zopinga zomwe zatengedwa zikuyendetsedwanso. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} -nthawi 6.25
[ pezani_mapini {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } ] create_clock -name {REF_CLK_PAD_P} -nthawi 10 [ get_ports { REF_CLK_PAD_P } ] create_clock -name {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_ist_PLL
DIV_CLK} -nthawi 8
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CCC_CLK_CLL_0_PF_0
OUT0} -chulukitsa_ndi 25 -gawikana_ndi 32 -gwero
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -gawo 0
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CCC_Cll_0CLL_Cll_0CLL_CLL_
OUT1} -chulukitsa_ndi 25 -gawikana_ndi 32 -gwero
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -gawo 0
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CCC_Cll_0CLL_Cll_0CLL_CLL_
OUT2} -chulukitsa_ndi 25 -gawikana_ndi 32 -gwero
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -gawo 0
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CCC_Cll_0CLL_Cll_0CLL_CLL_
OUT3} -chulukitsa_ndi 25 -gawikana_ndi 64 -gwero
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -gawo 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_80MHz/CLK_CD_0_CD_XNUMX
Y_DIV} -gawika_ndi 2 -gwero
[ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CLK_DIV_0/I_CD/A } ] [ pezani_mapini { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz_DIV_CD_CD_CD_CD_CD_CD_CD_ set_false_path -through [ get_nets { DMA_INITIATOR_inst_0/ARESETN* } ] set_false_path -from [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray* } ] -ku [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1* } ] set_false_path -from [ get_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray* } ] -ku [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1* } ] set_false_path -through [ get_nets { FIC0_INITIATOR_inst_0/ARESETN* } ] set_false_path -to [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[0] PCIE/0PF_PF_0
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/PCIE_1/MPERST_N } ] set_false_path -from [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/TL_CLK } ] set_false_path -through [ get_NIstNTIATOR] Zakumapeto B—Kulowetsa Ma Library Oyerekeza Kumalo Oyerekeza (Funsani Funso)
Choyimira chosasinthika cha RTL choyerekeza ndi Libero SoC ndi ModelSim ME Pro.
Ma library omwe adapangidwa kale a simulator yokhazikika akupezeka ndi kukhazikitsa kwa Libero pa chikwatu /Designer/lib/modelsimpro/precompiled/vlog for® mabanja othandizidwa. Libero SoC imathandiziranso zolemba zina zachitatu za ModelSim, Questasim, VCS, Xcelium.
, Active HDL, ndi Riviera Pro. Tsitsani malaibulale omwe adasanjidwa kale kuchokera Libero SoC v12.0 ndipo kenako kutengera simulator ndi mtundu wake.
Zofanana ndi chilengedwe cha Libero, run.do file ziyenera kupangidwa kuti zizitha kuyendetsa kunja kwa Libero.
Pangani njira yosavuta ya run.do file yomwe ili ndi malamulo okhazikitsa laibulale kuti ikhale ndi zotsatira zophatikiza, kupanga mapu a library, kuphatikiza, ndi kuyerekezera. Tsatirani masitepe kuti mupange zoyambira run.do file.

1. Pangani laibulale yomveka kuti musunge zotsatira zophatikiza pogwiritsa ntchito vlib command vlib presynth.
2. Lembani dzina laibulale yomveka ku chikwatu cha laibulale yopangidwa kale pogwiritsa ntchito vmap command vmap .
3. Konzani gwero files-gwiritsani ntchito malamulo ophatikizira azilankhulo kuti muphatikize mapangidwe files mu bukhu logwira ntchito.
   – vlog ya .v/.sv
   - vcom ya .vhd
4. Kwezani mapangidwe oyerekeza pogwiritsa ntchito vsim command potchula dzina la gawo lililonse lapamwamba.
5. Tsanzirani kapangidwe kake pogwiritsa ntchito run command.
   Mukatsitsa mapangidwewo, nthawi yofananira imayikidwa paziro, ndipo mutha kulowa lamulo loyendetsa kuti muyambe kuyerekezera.
   Pazenera la simulator, yambitsani run.do file monga run.do yendetsani kuyerekezera. Sampndi run.do file motere.

khazikitsani mwakachetechete ACTELLIBNAME PolarFire ikani PROJECT_DIR "W:/Test/basic_test" ngati
{[file lilipo presynth/_info]} { echo “INFO: Silation library presynth ilipo” } china
{ file delete -force presynth vlib presynth } vmap presynth vmap PolarFire
"X:/Libero/Designer/lib/modelsimpro/precompiled/vlog/PolarFire" vlog -sv -work presynth
“${PROJECT_DIR}/hdl/top.v” vlog “+incdir+${PROJECT_DIR}/stimulus” -sv -work presynth “$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb add wave /tb/*
thamangani 1000ns log /tb/* kutuluka

Zowonjezera C—Kupeza Zoletsa (Funsani Funso)

Zowonjezera izi zikufotokozera malamulo a Derive Constraints Tcl.
9.1 Pezani Malamulo a Tcl (Funsani Funso)
Dongosolo la derive_constraints limakuthandizani kuti mupeze zopinga kuchokera ku RTL kapena kasinthidwe kunja kwa chilengedwe cha Libero SoC. Kuti mupange zolepheretsa pakupanga kwanu, mufunika Wogwiritsa HDL, Component HDL, ndi Component Constraints. files. Zoletsa za gawo la SDC files zilipo pansi /gawo/ntchito/ / / chikwatu pambuyo pa kasinthidwe kagawo ndi kupanga.
Chigawo chilichonse choletsa file ili ndi lamulo la set_component tcl (limafotokoza dzina lachigawo) ndi mndandanda wa zopinga zomwe zimapangidwa pambuyo pokonzekera. Zoletsa zimapangidwira kutengera kasinthidwe ndipo ndizokhazikika pagawo lililonse.
Exampndi 9-1. Chigawo Choletsa File za PF_CCC Core
Nayi exampndi chopinga cha chigawo file za PF_CCC pachimake:
set_component PF_CCC_C0_PF_CCC_C0_0_PF_CCC
#Microchip Corp.
#Tsiku: 2021-Oct-26 04:36:00
# Wotchi yoyambira ya PLL #0
create_clock -period 10 [ get_pins {pll_inst_0/REF_CLK_0 } ] create_generated_clock -divide_by 1 -source [ get_pins {pll_inst_0/
REF_CLK_0 } ] -phase 0 [ get_pins {pll_inst_0/OUT0 }] Apa, create_clock and create_generated_clock ndizo zoletsa zowunikira komanso zotulutsa mawotchi motsatana, zomwe zimapangidwa potengera kasinthidwe.
9.1.1 Kugwira ntchito ndi derive_constraints Utility (Funsani Funso)
Zopinga zimadutsa pamapangidwewo ndikugawa zopinga zatsopano pagawo lililonse lachigawo kutengera zomwe zidaperekedwa kale SDC. files. Kwa mawotchi owonetsera a CCC, imafalikira mmbuyo kudzera mu kapangidwe kake kuti mupeze gwero la wotchiyo. Ngati gwero ndi I/O, choletsa cha wotchiyo chidzakhazikitsidwa pa I/O. Ngati ndi CCC yotulutsa kapena gwero lina la wotchi (mwachitsanzoample, Transceiver, oscillator), imagwiritsa ntchito wotchi kuchokera kuchigawo china ndikupereka chenjezo ngati nthawizo sizikugwirizana. Kuletsa zoletsa kudzaperekanso zoletsa kwa ma macros ena monga on-chip oscillator ngati muli nawo mu RTL yanu.
Kuti mugwiritse ntchito derive_constraints, muyenera kupereka .tcl file mtsutso wa mzere wa lamulo ndi chidziwitso chotsatira mu dongosolo lomwe latchulidwa.

1. Tchulani zambiri za chipangizocho pogwiritsa ntchito zomwe zili mugawo set_device.
2. Sankhani njira yopita ku RTL filepogwiritsa ntchito zomwe zili mugawo read_verilog kapena read_vhdl.
3. Khazikitsani gawo lapamwamba pogwiritsa ntchito zomwe zili mugawo set_top_level.
4. Tchulani njira yopita ku gawo la SDC filepogwiritsa ntchito zomwe zili mugawo read_sdc kapena read_ndc.
5. Yesani filepogwiritsa ntchito zomwe zili mu gawo deive_constraints.
6.  Tchulani njira yopita ku zovuta zomwe zimachokera ku SDC file pogwiritsa ntchito zomwe zili mugawo lolemba_sdc kapena lembani_pdc kapena lembani_ndc.

Exampndi 9-2. Kuchita ndi Zomwe zili mu derive.tcl File
Chotsatira ndi example mkangano wa mzere wolamula kuti mugwiritse ntchito derive_constraints.
$ /bin{64}/derive_constraints derive.tcl
Zomwe zili mu derive.tcl file:
# Zambiri pazida
set_device -family PolarFire -die MPF100T -speed -1
#RTL files
read_verilog -mode system_verilog project/component/work/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
read_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
read_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd}
#Chigawo cha SDC files
set_top_level {xcvr1}
werengani_sdc -gawo {project/component/work/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
werengani_sdc -gawo {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
# Gwiritsani ntchito derive_constraint command
derive_constraints
Zotsatira za #SDC/PDC/NDC files
write_sdc {project/constraint/xcvr1_derived_constraints.sdc}
write_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 set_device (Funsani Funso)
Kufotokozera
Tchulani dzina labanja, dzina lakufa, ndi kalasi yothamanga.
set_device -family -kufa -liwiro
Zokangana

Parameter	Mtundu	Kufotokozera
-banja	Chingwe	Tchulani dzina labanja. Zomwe zingatheke ndi PolarFire®, PolarFire SoC.
-kufa	Chingwe	Tchulani dzina lakufa.
-liwiro	Chingwe	Tchulani liwiro la chipangizocho. Zomwe zingatheke ndi STD kapena -1.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Gawo lofunikira - kufa kulibe	Njira ya kufa ndiyofunikira ndipo iyenera kufotokozedwa.
ZOKHUDZA	kufa 'MPF30' yosadziwika	Mtengo wa -die mwina siwolondola. Onani mndandanda wazinthu zomwe zingatheke muzofotokozera za zosankha.
ZOKHUDZA	Parameter - kufa kulibe mtengo	Njira ya kufa imatchulidwa popanda mtengo.
ZOKHUDZA	Zofunikira - banja likusowa	Zosankha zabanja ndizovomerezeka ndipo ziyenera kufotokozedwa.
ZOKHUDZA	Banja losadziwika 'PolarFire®'	Zosankha zabanja sizolondola. Onani mndandanda wazinthu zomwe zingatheke muzofotokozera za zosankha.

………… anapitiriza
Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Parameter—banja likusowa mtengo	Chosankha chabanja chimatchulidwa popanda mtengo.
ZOKHUDZA	Zofunikira - liwiro lilibe	Njira yothamanga ndiyofunikira ndipo iyenera kufotokozedwa.
ZOKHUDZA	Liwiro losadziwika ' '	Kuthamanga kwachangu sikulondola. Onani mndandanda wazinthu zomwe zingatheke muzofotokozera za zosankha.
ZOKHUDZA	Parameter—liwiro likusowa mtengo	Kuthamanga kwachangu kumatchulidwa popanda mtengo.

Example
set_device -family {PolarFire} -fa {MPF300T_ES} -liwiro -1
set_device -family SmartFusion 2 -fa M2S090T -speed -1
9.1.3 werengani_verilog (Funsani Funso)
Kufotokozera
Werengani Verilog file pogwiritsa ntchito Verific.
werengani_verilog [-lib ] [-mode ]filedzina>
Zokangana

Parameter	Mtundu	Kufotokozera
-lib	Chingwe	Tchulani laibulale yomwe ili ndi ma modules kuti awonjezedwe mulaibulale.
- mode	Chingwe	Tchulani muyezo wa Verilog. Zomwe zingatheke ndi verilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. Makhalidwe samakhudzidwa ndi nkhani. Zofikira zonse ndi verilog_2k.
filedzina	Chingwe	Verilog file dzina.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Parameter-lib ikusowa mtengo	Njira ya lib imatchulidwa popanda mtengo.
ZOKHUDZA	Parameter-mode ilibe mtengo	Njira yosankha imatchulidwa popanda mtengo.
ZOKHUDZA	Njira yosadziwika ' '	Mtundu wa verilog womwe watchulidwa sudziwika. Onani mndandanda wamawonekedwe amtundu wa verilog mu-mafotokozedwe anjira.
ZOKHUDZA	Zofunikira parameter file dzina palibe	Palibe verilog file njira imaperekedwa.
ZOKHUDZA	Zalephereka chifukwa chofotokozera Verific	Vuto la Syntax mu verilog file. Verific's parser imatha kuwonedwa mu console yomwe ili pamwamba pa uthenga wolakwika.
ZOKHUDZA	set_device sichimatchedwa	Zambiri za chipangizocho sizinatchulidwe. Gwiritsani ntchito lamulo la set_device pofotokozera chipangizocho.

Example
read_verilog -mode system_verilog {component/work/top/top.v}
read_verilog -mode system_verilog_mfcu design.v
9.1.4 werengani_vhdl (Funsani Funso)
Kufotokozera
Onjezani VHDL file mu mndandanda wa VHDL files.
werengani_vhdl [-lib ] [-mode ]filedzina>
Zokangana

Parameter	Mtundu	Kufotokozera
-lib	—	Tchulani laibulale momwe ziyenera kuwonjezeredwa.
- mode	—	Imatchula muyezo wa VHDL. Zofikira zonse ndi VHDL_93. Zomwe zingatheke ndi vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. Makhalidwe samakhudzidwa ndi nkhani.
filedzina	—	Chithunzi cha VHDL file dzina.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Parameter-lib ikusowa mtengo	Njira ya lib imatchulidwa popanda mtengo.
ZOKHUDZA	Parameter-mode ilibe mtengo	Njira yosankha imatchulidwa popanda mtengo.
ZOKHUDZA	Njira yosadziwika ' '	Mtundu wa VHDL womwe watchulidwa sudziwika. Onani mndandanda wamawonekedwe a VHDL mu-mafotokozedwe a njira.
ZOKHUDZA	Zofunikira parameter file dzina palibe	Palibe VHDL file njira imaperekedwa.
ZOKHUDZA	Takanika kulembetsa invalid_path.v file	VHDL yotchulidwa file kulibe kapena kulibe chilolezo chowerenga.
ZOKHUDZA	set_device sichimatchedwa	Zambiri za chipangizocho sizinatchulidwe. Gwiritsani ntchito lamulo la set_device pofotokozera chipangizocho.

Example
read_vhdl -mode vhdl_2008 osc2dfn.vhd
read_vhdl {hdl/top.vhd}
9.1.5 set_top_level (Funsani Funso)
Kufotokozera
Tchulani dzina la gawo lapamwamba kwambiri mu RTL.
set_top_level [-lib ]
Zokangana

Parameter	Mtundu	Kufotokozera
-lib	Chingwe	Laibulale yoti mufufuze gawo lapamwamba kwambiri kapena gulu (Mwasankha).
dzina	Chingwe	Module yapamwamba kapena dzina lachinthu.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Mulingo wapamwamba wofunikira ulibe	Njira yapamwamba ndiyofunikira ndipo iyenera kufotokozedwa.
ZOKHUDZA	Parameter-lib ikusowa mtengo	Njira ya lib imatchulidwa popanda zikhalidwe.
ZOKHUDZA	Sitinathe kupeza mulingo wapamwamba mu library	Gawo lapamwamba lomwe latchulidwa silinafotokozedwe mulaibulale yoperekedwa. Kuti mukonze cholakwikachi, gawo lapamwamba kapena dzina la library liyenera kukonzedwa.
ZOKHUDZA	Kufotokozera zalephera	Zolakwika pakusintha kwa RTL. Uthenga wolakwika ukhoza kuwonedwa kuchokera ku console.

Example
set_top_level {pamwamba}
set_top_level -lib HDl pamwamba
9.1.6 read_sdc (Funsani Funso)
Kufotokozera
Werengani a SDC file mu gawo la database.
werengani_sdc -gawofiledzina>
Zokangana

Parameter	Mtundu	Kufotokozera
- gawo	—	Uwu ndi mbendera yovomerezeka ya read_sdc command tikapeza zopinga.
filedzina	Chingwe	Njira yopita ku SDC file.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Zofunikira parameter file dzina palibe.	Njira yovomerezeka file dzina silinatchulidwe.
ZOKHUDZA	SDC file <file_path> sichiwerengeka.	SDC yosankhidwa file alibe zilolezo zowerenga.
ZOKHUDZA	Takanika kutsegulafile_njira> file.	Chithunzi cha SDC file kulibe. Njirayo iyenera kukonzedwa.
ZOKHUDZA	Lamulo losowa set_component mufile_njira> file	Mtengo wapatali wa magawo SDC file sichimatchula chigawocho.

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	<List of errors from sdc file>	Chithunzi cha SDC file ili ndi malamulo olakwika a sdc. Za example, pakakhala cholakwika mu set_multicycle_path constraint: Zolakwika mukuchita lamulo read_sdc: mufile_njira> file: Zolakwika mu lamulo set_multicycle_path: Zosadziwika [get_cells {reg_a}].

Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 read_ndc (Funsani Funso)
Kufotokozera
Werengani NDC file mu gawo la database.
werengani_ndc -gawofiledzina>
Zokangana

Parameter	Mtundu	Kufotokozera
- gawo	—	Ichi ndi mbendera yovomerezeka ya read_ndc command tikapeza zopinga.
filedzina	Chingwe	Njira yopita ku NDC file.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Takanika kutsegulafile_njira> file	NDC pa file kulibe. Njirayo iyenera kukonzedwa.
ZOKHUDZA	Zofunikira - AtclParamO_ ikusowa.	Njira yovomerezeka filedzina silinatchulidwe.
ZOKHUDZA	Zofunikira - gawo lilibe.	Chosankha cha gawo ndichofunikira ndipo chiyenera kufotokozedwa.
ZOKHUDZA	NDC file 'file_path>' sichiwerengeka.	NDC yodziwika file alibe zilolezo zowerenga.

Example
read_ndc -component {chigawo/work/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 deive_constraints (Funsani Funso)
Kufotokozera
Yambitsani gawo la SDC files mumndandanda wazinthu zamapangidwe.
derive_constraints
Zokangana

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Mlingo wapamwamba sunatchulidwe	Izi zikutanthauza kuti gawo lapamwamba kapena gulu silinatchulidwe. Kuti mukonze kuyimba uku, perekani set_top_level lamulo pamaso pa derive_constraints lamulo.

Example
derive_constraints
9.1.9 write_sdc (Funsani Funso)
Kufotokozera
Amalemba choletsa file mu mawonekedwe a SDC.
kulemba_sdcfiledzina>
Zokangana

Parameter	Mtundu	Kufotokozera
<filedzina>	Chingwe	Njira yopita ku SDC file zidzapangidwa. Iyi ndi njira yovomerezeka. Ngati ndi file alipo, adzalembedwa.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Takanika kutsegulafile njira> file.	File njira si yolondola. Onani ngati maulalo a makolo alipo.
ZOKHUDZA	SDC file 'file path>' sichimalembedwa.	SDC yosankhidwa file alibe chilolezo cholemba.
ZOKHUDZA	Zofunikira parameter file dzina palibe.	Chithunzi cha SDC file njira ndi njira yovomerezeka ndipo iyenera kufotokozedwa.

Example
write_sdc "derived.sdc"
9.1.10 write_pdc (Funsani Funso)
Kufotokozera
Amalemba zopinga zakuthupi (Derive Constraints kokha).
kulemba_pdcfiledzina>
Zokangana

Parameter	Mtundu	Kufotokozera
<filedzina>	Chingwe	Njira yopita ku PDC file zidzapangidwa. Iyi ndi njira yovomerezeka. Ngati ndi file njira ilipo, idzalembedwa.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Mauthenga Olakwika	Kufotokozera
ZOKHUDZA	Takanika kutsegulafile njira> file	The file njira si yolondola. Onani ngati maulalo a makolo alipo.
ZOKHUDZA	PDC file 'file path>' sichikhoza kulembedwa.	PDC yosankhidwa file alibe chilolezo cholemba.
ZOKHUDZA	Zofunikira parameter file dzina palibe	Chithunzi cha PDC file njira ndi njira yovomerezeka ndipo iyenera kufotokozedwa.

Example
write_pdc "derived.pdc"
9.1.11 write_ndc (Funsani Funso)
Kufotokozera
Imalemba zovuta za NDC kukhala a file.
kulemba_ndcfiledzina>
Zokangana

Parameter	Mtundu	Kufotokozera
filedzina	Chingwe	Njira yopita ku NDC file zidzapangidwa. Iyi ndi njira yovomerezeka. Ngati ndi file alipo, adzalembedwa.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Mauthenga Olakwika	Kufotokozera
ZOKHUDZA	Takanika kutsegulafile_njira> file.	File njira si yolondola. Maulalo a makolo kulibe.
ZOKHUDZA	NDC file 'file_path>' sichimalembedwa.	NDC yodziwika file alibe chilolezo cholemba.
ZOKHUDZA	Zofunikira _AtclParamO_ ikusowa.	NDC pa file njira ndi njira yovomerezeka ndipo iyenera kufotokozedwa.

Example
write_ndc "derved.ndc"
9.1.12 add_include_path (Funsani Funso)
Kufotokozera
Imatchula njira yosaka kuphatikiza files powerenga RTL files.
add_include_path
Zokangana

Parameter	Mtundu	Kufotokozera
directory	Chingwe	Imatchula njira yosaka kuphatikiza files powerenga RTL files. Njira iyi ndi yovomerezeka.

Mtundu Wobwerera	Kufotokozera
0	Lamulo linapambana.

Mtundu Wobwerera	Kufotokozera
1	Lamulo lalephera. Pali cholakwika. Mutha kuwona uthenga wolakwika mu console.

Mndandanda wa Zolakwa

Khodi Yolakwika	Uthenga Wolakwika	Kufotokozera
ZOKHUDZA	Zofunikira pakuphatikiza njira ikusowa.	Njira yachikwatu ndiyofunikira ndipo iyenera kuperekedwa.

Zindikirani: Ngati njira yachikwatu si yolondola, ndiye add_include_path idzadutsa popanda cholakwika.
Komabe, malamulo a read_verilog/read_vhd adzalephera chifukwa cha Verific's parser.
Example
add_include_path component/work/CORABC0/CORABC0_0/rtl/vlog/core

Mbiri Yowunikiranso (Funsani Funso)

Mbiri yokonzanso ikufotokoza zosintha zomwe zidakhazikitsidwa muzolemba. Zosinthazo zandandalikidwa ndi kubwereza, kuyambira ndi zofalitsa zamakono.

Kubwereza	Tsiku	Kufotokozera
F	08/2024	Zosintha zotsatirazi zasinthidwa mukusinthaku: • Chigawo chosinthidwa Chakumapeto B—Kulowetsa Malaibulale Oyerekeza Kumalo Oyerekeza.
E	08/2024	Zosintha zotsatirazi zasinthidwa mukusinthaku: • Gawo losinthidwa Kuthaview. • Gawo losinthidwa Derived SDC File. • Chigawo chosinthidwa Chakumapeto B—Kulowetsa Malaibulale Oyerekeza Kumalo Oyerekeza.
D	02/2024	Chikalatachi chimatulutsidwa ndi Libero 2024.1 SoC Design Suite popanda kusintha kuchokera ku v2023.2. Gawo losinthidwa Kugwira ntchito ndi derive_constraints Utility
C	08/2023	Chikalatachi chimatulutsidwa ndi Libero 2023.2 SoC Design Suite popanda kusintha kuchokera ku v2023.1.
B	04/2023	Chikalatachi chimatulutsidwa ndi Libero 2023.1 SoC Design Suite popanda kusintha kuchokera ku v2022.3.
A	12/2022	Kubwereza Koyamba.

Thandizo la Microchip FPGA
Gulu lazinthu za Microchip FPGA limathandizira zogulitsa zake ndi ntchito zosiyanasiyana zothandizira, kuphatikiza Makasitomala, Customer Technical Support Center, a webmalo, ndi maofesi ogulitsa padziko lonse lapansi.
Makasitomala akulangizidwa kuti aziyendera zapaintaneti za Microchip asanakumane ndi chithandizo chifukwa ndizotheka kuti mafunso awo ayankhidwa kale.
Lumikizanani ndi Technical Support Center kudzera pa website pa www.microchip.com/support. Tchulani nambala ya Gawo la Chipangizo cha FPGA, sankhani gulu loyenera, ndikuyika mapangidwe files popanga chithandizo chaukadaulo.
Lumikizanani ndi Makasitomala kuti muthandizidwe ndi zinthu zomwe si zaukadaulo, monga mitengo yazinthu, kukweza kwazinthu, zambiri zosintha, mawonekedwe oyitanitsa, ndi chilolezo.

• Kuchokera ku North America, imbani 800.262.1060
• Kuchokera kudziko lonse lapansi, imbani 650.318.4460
• Fax, kuchokera kulikonse padziko lapansi, 650.318.8044

Zambiri za Microchip
The Microchip Webmalo
Microchip imapereka chithandizo cha intaneti kudzera pa athu website pa www.microchip.com/. Izi webtsamba limagwiritsidwa ntchito kupanga files ndi zambiri kupezeka mosavuta kwa makasitomala. Zina mwazinthu zomwe zilipo ndi izi:

• Thandizo lazinthu - Mapepala a deta ndi zolakwika, zolemba za ntchito ndi sampmapulogalamu, zida zamapangidwe, maupangiri a ogwiritsa ntchito ndi zikalata zothandizira pa Hardware, kutulutsa kwaposachedwa kwa mapulogalamu ndi mapulogalamu osungidwa zakale
• General Technical Support - Mafunso Ofunsidwa Kawirikawiri (FAQs), zopempha zothandizira luso, magulu okambirana pa intaneti, mndandanda wa mamembala a pulogalamu ya Microchip
• Business of Microchip - Zosankha katundu ndi maupangiri oyitanitsa, zofalitsa zaposachedwa za Microchip, mindandanda yamasemina ndi zochitika, mndandanda wamaofesi ogulitsa a Microchip, ogawa ndi oyimira mafakitale.

Ntchito Yodziwitsa Kusintha Kwazinthu
Ntchito yodziwitsa zakusintha kwazinthu za Microchip imathandizira makasitomala kuti azitha kudziwa zinthu za Microchip. Olembetsa adzalandira zidziwitso za imelo nthawi iliyonse pakakhala zosintha, zosintha, zosintha kapena zolakwika zokhudzana ndi banja linalake kapena chida chachitukuko. Kuti mulembetse, pitani ku www.microchip.com/pcn ndikutsatira malangizo olembetsera.

Thandizo la Makasitomala
Ogwiritsa ntchito Microchip atha kulandira thandizo kudzera munjira zingapo:

• Wogawa kapena Woimira
• Local Sales Office
• Embedded Solutions Engineer (ESE)
• Othandizira ukadaulo

Makasitomala akuyenera kulumikizana ndi omwe amawagawa, oyimilira kapena ESE kuti awathandize. Maofesi ogulitsa am'deralo amapezekanso kuti athandize makasitomala. Mndandanda wamaofesi ogulitsa ndi malo uli m'chikalatachi. Thandizo laukadaulo likupezeka kudzera mu webtsamba pa: www.microchip.com/support
Chitetezo cha Microchip Devices Code
Zindikirani tsatanetsatane wotsatira wa chitetezo cha code pazinthu za Microchip:

• Zogulitsa za Microchip zimakwaniritsa zomwe zili mu Microchip Data Sheet yawo.
• Microchip imakhulupirira kuti katundu wake ndi wotetezeka akagwiritsidwa ntchito m'njira yomwe akufuna, malinga ndi momwe amagwirira ntchito, komanso m'mikhalidwe yabwinobwino.
• Ma Microchip amawakonda ndikuteteza mwamphamvu ufulu wake wazinthu zamaluso. Kuyesa kuphwanya malamulo otetezedwa ndi zinthu za Microchip ndikoletsedwa ndipo zitha kuphwanya Digital Millennium Copyright Act.
• Ngakhale Microchip kapena wopanga semiconductor wina aliyense sangatsimikizire chitetezo cha code yake. Kutetezedwa kwa ma code sikutanthauza kuti tikutsimikizira kuti chinthucho ndi "chosasweka". Chitetezo cha code chikusintha nthawi zonse. Microchip yadzipereka mosalekeza kuwongolera mawonekedwe achitetezo azinthu zathu.

Chidziwitso chazamalamulo
Bukuli ndi zambiri zomwe zili pano zitha kugwiritsidwa ntchito ndi zinthu za Microchip zokha, kuphatikiza kupanga, kuyesa, ndi kuphatikiza zinthu za Microchip ndi pulogalamu yanu. Kugwiritsa ntchito chidziwitsochi mwanjira ina iliyonse kumaphwanya mawuwa. Zambiri zokhudzana ndi kugwiritsa ntchito zida zimaperekedwa kuti zitheke ndipo zitha kulowedwa m'malo ndi zosintha. Ndi udindo wanu kuwonetsetsa kuti pulogalamu yanu ikugwirizana ndi zomwe mukufuna. Lumikizanani ndi ofesi yogulitsa za Microchip kwanuko kuti muthandizidwe zina kapena, pezani thandizo lina pa www.microchip.com/en-us/support/design-help/client-support-services.
ZIMENEZI AMAPEREKA NDI MICROCHIP "MONGA ILI". MICROCHIP SIKUYAMBIRA KAPENA ZIZINDIKIRO ZA MTIMA ULIWONSE KAYA KUTANTHAUZIRA KAPENA ZOTHANDIZA, ZOlembedwa KAPENA MWAMWAMBA, ZOYENERA KAPENA ZINTHU ZINA, ZOKHUDZANA NDI CHIZINDIKIRO KUPHATIKIZAPO KOMA ZOSAKHALA NDI CHIPEMBEDZO CHILICHONSE, NTCHITO, NTCHITO, NTCHITO, NTCHITO, NTCHITO, NTCHITO. ZOLINGA ZABWINO, KAPENA ZOTSATIRA ZIMAGWIRITSA NTCHITO KAKHALIDWE, UKHALIDWE, KAPENA NTCHITO ZAKE. PAMENE MICROCHIP IDZAKHALA NDI NTCHITO PA CHIZINDIKIRO CHILICHONSE, CHAPADERA, CHILANGO, ZOCHITIKA, KAPENA ZOTSATIRA ZOTSATIRA, KUonongeka, mtengo, KAPENA NTCHITO ZONSE ZOMWE ZILI ZOKHUDZA CHIdziwitso KAPENA NTCHITO YAKE, KOMA CHIFUKWA CHIFUKWA CHOCHITIKA, ZOCHITIKA KAPENA ZOWONONGWA NDI ZOONERA. KUBWERA KWABWINO KWAMBIRI ZOLOLEZEDWA NDI MALAMULO, NDONDOMEKO YONSE YA MICROCHIP PA ZINSINSI ZONSE MU NJIRA ILIYONSE YOKHUDZANA NDI CHIdziwitso KAPENA KUKGWIRITSA NTCHITO CHOSAPYOTSA KUCHULUKA KWA ZOLIMBIKITSA, NGATI KULIPO, ZIMENE MULIPITSA CHIFUKWA CHIFUKWA CHIFUKWA CHIYANI.
Kugwiritsa ntchito zipangizo za Microchip pa chithandizo cha moyo ndi/kapena ntchito za chitetezo zili pachiopsezo cha wogula, ndipo wogula akuvomera kuteteza, kubwezera ndi kusunga Microchip yopanda vuto lililonse ndi kuwonongeka kulikonse, ndalama, masuti, kapena ndalama zomwe zimadza chifukwa cha ntchito yotereyi. Palibe zilolezo zomwe zimaperekedwa, mobisa kapena mwanjira ina, pansi pa ufulu wazinthu zaukadaulo za Microchip pokhapokha zitanenedwa.
Zizindikiro
Dzina la Microchip ndi logo, logo ya Microchip, Adaptec, AVR, logo ya AVR, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ndi XMEGA ndi zizindikiro zolembetsedwa za Microchip Technology Incorporated ku USA ndi mayiko ena.
AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​​​Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, ndi ZL ndi zizindikilo zolembetsedwa za Microchip Technology Incorporated ku USA.
Kuponderezedwa Kwachinsinsi, AKS, Analog-for-the-Digital Age, AnyCapacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM Average. . maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PureSimart , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance , Nthawi Yodalirika, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ndi ZENA ndi zizindikiro za Microchip Technology Incorporated ku USA ndi mayiko ena.
SQTP ndi chizindikiro cha ntchito cha Microchip Technology Incorporated ku USA
Chizindikiro cha Adaptec, Frequency on Demand, Silicon Storage Technology, ndi Symmcom ndi zizindikilo zolembetsedwa za Microchip Technology Inc. m'maiko ena.
GestIC ndi chizindikiro cholembetsedwa cha Microchip Technology Germany II GmbH & Co. KG, kampani ya Microchip Technology Inc., m'maiko ena.
Zizindikiro zina zonse zomwe zatchulidwa pano ndi zamakampani awo.
2024, Microchip Technology Incorporated ndi mabungwe ake. Maumwini onse ndi otetezedwa.
ISBN: 978-1-6683-0183-8
Quality Management System
Kuti mudziwe zambiri za Microchip's Quality Management Systems, chonde pitani www.microchip.com/quality.
Zogulitsa Padziko Lonse ndi Ntchito

AMERICAS	ASIA/PACIFIC	ASIA/PACIFIC	ULAYA
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