Ezinụlọ PolarFire FPGA Ntuziaka onye ọrụ ịgba ọsọ
Libero SoC v2024.2

Okwu mmalite (Jụọ ajụjụ)

Ngwa ngwa Libero System-on-Chip (SoC) na-enye gburugburu imewe Field Programmable Gate Array (FPGA). Agbanyeghị, ndị ọrụ ole na ole nwere ike ịchọ iji njikọ nke ndị ọzọ na ngwa ịme anwansị na mpụga ebe Libero SoC. Enwere ike itinye Libero ugbu a na gburugburu imewe FPGA. A na-atụ aro ka iji Libero SoC jikwaa usoro nhazi FPGA niile.
Ntuziaka onye ọrụ a na-akọwa Flow omenala maka PolarFire na PolarFire SoC ngwaọrụ ezinụlọ, usoro iji jikọta Libero dịka akụkụ nke nnukwu nhazi FPGA. Ezinụlọ Ngwaọrụ akwadoro Tebụlụ na-esote depụtara ezinụlọ ngwaọrụ ndị Libero SoC na-akwado. Agbanyeghị, ụfọdụ ozi dị na ntuziaka a nwere ike emetụta naanị otu ezinụlọ nke ngwaọrụ. N'okwu a, a na-achọpụta ozi dị otú ahụ nke ọma.
Tebụl 1. Ezinụlọ ngwaọrụ nke Libero SoC na-akwado

Ezinụlọ ngwaọrụ	Nkọwa
PolarFire®	PolarFire FPGA na-ebunye ike ụlọ ọrụ kacha ala na njupụta dị n'etiti yana nchekwa na ntụkwasị obi pụrụ iche.
PolarFire SoC	PolarFire SoC bụ SoC FPGA nke mbụ nwere ụyọkọ RISC-V CPU na-ekpebi, yana sistemụ nchekwa L2 na-ekpebi Linux® na ngwa ozugbo.

gafereview (Jụọ ajụjụ)

Ọ bụ ezie na Libero SoC na-enye gburugburu njedebe njedebe njedebe zuru oke iji mepụta atụmatụ SoC na FPGA, ọ na-enyekwa mgbanwe iji mee njikọ na ịme anwansị na ngwaọrụ ndị ọzọ na-abụghị ebe Libero SoC. Agbanyeghị, ụfọdụ usoro imewe ga-adịrịrị n'ime mpaghara Libero SoC.
Tebụlụ na-esonụ na-edepụta usoro ndị bụ isi na usoro nhazi FPGA ma gosi usoro nke a ga-eji Libero SoC mee ihe.
Isiokwu 1-1. Usoro nhazi FPGA

Nzọpụta Usoro Nhazi	Ga-eji Libero	Nkọwa
Ntinye imewe: HDL	Mba	Jiri ngwa editọ/nyocha HDL ndị ọzọ na mpụga Libero® SoC ma ọ bụrụ na achọrọ.
Ntinye imewe: Configurators	Ee	Mepụta ọrụ mbụ Libero maka ọgbọ akụrụngwa akụrụngwa IP katalọgụ.
Ọgbọ mgbochi PDC/SDC akpaaka	Mba	Ihe mgbochi ewepụtara chọrọ HDL niile files na akụrụngwa derive_constraints mgbe a na-eme ya na mpụga nke Libero SoC, dịka akọwara na Mgbakwunye C—Mkpagide Na-enweta.
ịme anwansị	Mba	Jiri ngwa ndị ọzọ na-abụghị Libero SoC, ma ọ bụrụ na achọrọ. Na-achọ nbudata ọba akwụkwọ simulation ekpokọtara tupu oge eruo maka ngwaọrụ ebumnuche, simulator lekwasịrị anya, na ụdị Libero ebumnuche ejiri maka mmejuputa azụ azụ.
Synthesis	Mba	Jiri ngwá ọrụ ndị ọzọ na-abụghị Libero SoC ma ọ bụrụ na ịchọrọ.
Mmezu imewe: Jikwaa ihe mgbochi, chịkọta netlist, ebe-na ụzọ (lee n'eluview)	Ee	Mepụta ọrụ Libero nke abụọ maka mmejuputa azụ azụ.
Oge na nkwenye ike	Ee	Nọgide na ọrụ Libero nke abụọ.
Hazie data mmalite mmalite imewe na ncheta	Ee	Jiri ngwá ọrụ a jikwaa ụdị ncheta dị iche iche na nhazi mmalite na ngwaọrụ ahụ. Nọgide na ọrụ nke abụọ.
Mmemme File Ọgbọ	Ee	Nọgide na ọrụ nke abụọ.

Ihe dị mkpa: Ị ga-ebudata ọba akwụkwọ achịkọtaburu dị na ya Ọbá akwụkwọ ịme anwansị achịkọtaburu ibe iji jiri simulator ndị ọzọ.
N'ime akwa FPGA dị ọcha, tinye nhazi gị site na iji HDL ma ọ bụ ntinye atụmatụ wee gafee nke ahụ ozugbo
ka synthesis ngwaọrụ. A ka na-akwado eruba. PolarFire na PolarFire SoC FPGA nwere nnukwu ihe
Ihe mgbochi IP siri ike nke na-achọ iji nhazi cores (SgCores) sitere na Libero SoC IP.
katalọgụ. Achọrọ njikwa pụrụ iche maka ngọngọ ọ bụla nwere ọrụ SoC:

• PolarFire
  - PF_UPROM
  - PF_SYSTEM_SERVICES
  - PF_CCC
  - PF CLK DIV
  - PF_CRYPTO
  - PF_DRI
  - PF_INIT_MONITOR
  - PF_NGMUX
  - PF_OSC
  - RAM (TPSRAM, DPSRAM, URAM)
  - PF_SRAM_AHBL_AXI
  - PF_XCVR_ERM
  - PF_XCVR_REF_CLK
  - PF_TX_PLL
  - PF_PCIE
  - PF_IO
  - PF_IOD_CDR
  - PF_IOD_CDR_CCC
  - PF_IOD_GENERIC_RX
  - PF_IOD_GENERIC_TX
  - PF_IOD_GENERIC_TX_CCC
  - PF_RGII_TO_GMII
  - PF_IOD_OCTAL_DDR
  - PF_DDR3
  - PF_DDR4
  - PF_LPDDR3
  - PF_QDR
  - PF_CORESMARTBERT
  - PF_TAMPER
  - PF_TVS, na ndị ọzọ.

Na mgbakwunye na SgCores edepụtara nke bu ụzọ, enwere ọtụtụ DirectCore soft IP dị maka ezinụlọ PolarFire na PolarFire SoC na Libero SoC Catalog na-eji akụrụngwa akwa FPGA.
Maka ntinye imewe, ọ bụrụ na ị na-eji nke ọ bụla n'ime ihe ndị bu ụzọ, ị ga-eji Libero SoC maka akụkụ nke ntinye ntinye (Component Configuration), ma ị nwere ike ịga n'ihu na ntinye ihe ntinye gị (ntinye HDL, na ihe ndị ọzọ) n'èzí Libero. Iji jikwaa usoro nhazi FPGA na mpụga Libero, soro usoro ndị enyere na ntuziaka ndị ọzọ.
1.1 Usoro ndụ akụkụ (Jụọ ajụjụ)
Usoro ndị a na-akọwa usoro ndụ nke akụrụngwa SoC wee nye ntuziaka maka otu esi ejikwa data ahụ.

1. Mepụta akụrụngwa site na iji nhazi ya na Libero SoC. Nke a na-emepụta ụdị data ndị a:
   - HDL files
   – Ebe nchekwa files
   - Ihe mkpali na ịme anwansị files
   - Akụkụ SDC file
2. Maka HDL files, mee ngwa ngwa ma jikọta ha na nhazi HDL ndị ọzọ site na iji ngwa ntinye/usoro ntinye nke mpụga.
3. Ebe nchekwa ọkọnọ files na mkpali files na ngwá ọrụ ịme anwansị gị.
4. Ngwa akụrụngwa SDC file iji nweta ihe mgbochi maka ọgbọ mgbochi. Lee Ihe Odide Ntụkwasị C — Nweta mmachi maka nkọwa ndị ọzọ.
5. Ị ga-emepụta ọrụ Libero nke abụọ, ebe ị na-ebubata netlist post-Synthesis na metadata akụrụngwa gị, si otú a na-emecha njikọ n'etiti ihe ị mepụtara na ihe ị na-eme.

1.2 Libero SoC Project Creation (Jụọ ajụjụ)
Ụfọdụ usoro nhazi ga-emerịrị n'ime gburugburu ebe obibi Libero SoC (Table 1-1). Ka usoro ndị a wee na-agba ọsọ, ị ga-emerịrị ọrụ abụọ nke Libero SoC. A na-eji ọrụ mbụ eme ihe maka nhazi akụkụ nhazi na ọgbọ, ọrụ nke abụọ bụ maka mmejuputa anụ ahụ nke nhazi ọkwa elu.
1.3 Usoro omenala (Jụọ ajụjụ)
Ọnụ ọgụgụ a na-egosi:

• Enwere ike ijikọ Libero SoC dị ka akụkụ nke nnukwu mmebe FPGA nwere njikọ nke ndị ọzọ na ngwa ịme anwansị na mpụga ebe Libero SoC.
• Usoro dị iche iche na-etinye aka na ọsọ ahụ, na-amalite site na imepụta imewe na ịdụkọta ruo n'usoro nhazi ngwaọrụ.
• Mgbanwe data (ntinye na ntinye) nke ga-emerịrị na usoro nhazi ọ bụla.

Ndụmọdụ:

1. SNVM.cfg, UPROM.cfg
2. *.mem file ọgbọ maka ịme anwansị: pa4rtupromgen.exe na-ewe UPROM.cfg dị ka ntinye wee mepụta UPROM.mem.

Ihe ndị a bụ usoro n'ime usoro nhazi omenala:

1. Nhazi akụrụngwa na ọgbọ:
   a. Mepụta ọrụ mbụ Libero (iji jee ozi dị ka ọrụ ntụaka).
   b. Họrọ isi na katalọgụ. Pịa isi ugboro abụọ iji nye ya aha akụrụngwa wee hazie akụrụngwa.
   Nke a na-ebupụ data akụrụngwa na-akpaghị aka na files. A na-emepụtakwa ihe ngosipụta akụkụ. Lee nkọwapụta akụkụ maka nkọwa. Maka nkọwa ndị ọzọ, hụ Nhazi akụrụngwa.
2. Mezue nhazi RTL gị na mpụga Libero:
   a. Mepụta akụrụngwa HDL ozugbo files.
   b. Ọnọdụ nke HDL files ka edepụtara na ngosipụta akụrụngwa files.
3. Mepụta ihe mgbochi SDC maka akụrụngwa. Jiri akụrụngwa ihe mgbochi iji mepụta mmachi oge file(SDC) dabere na:
   a. Akụkụ HDL files
   b. Akụkụ SDC files
   c. HDL onye ọrụ files
   Maka nkọwa ndị ọzọ, lee Ihe Odide C—Mkpagide Na-akpata.
4. Ngwá ọrụ synthesis/ihe simulation:
   a. Nweta HDL files, mkpali files, na data akụrụngwa sitere na ebe akọwapụtara dị ka ekwuru na ngosipụta akụrụngwa.
   b. Mekọrịta ma were ngwaọrụ ndị ọzọ megharịa ihe ahụ na mpụga Libero SoC.
5. Mepụta ọrụ Libero gị nke abụọ (mmejuputa).
6. Wepu njikọ sitere na yinye eruba imewe (Project> Settings Project> Flow Design> Kpochapụ igbe nlele Kwado Synthesis).
7. Bubata isi mmalite imewe files (post-synthesis * .vm netlist sitere na ngwa njikọ):
   - Bubata post-synthesis * .vm netlist (File> Bubata> Verilog Netlist synthesized (VM)).
   - metadata akụrụngwa * .cfg files maka uPROM na/ma ọ bụ sNVM.
8. Bubata akụrụngwa mgbochi Libero SoC ọ bụla files. Ihe mgbochi files ga-adị na * .cxz file usoro.
   Maka ozi ndị ọzọ gbasara otu esi emepụta ngọngọ, hụ Ntuziaka onye ọrụ PolarFire Block.
9. Bubata mmachi imewe:
   – Bubata mmachi I/O files (Onye njikwa ihe mgbochi> I/OAttributes> Bubata).
   – Bubata atụmatụ ala * .pdc files (Onye njikwa ihe mgbochi> Onye nhazi ala> Bubata).
   – Bubata * .sdc mmachi oge files (Onye njikwa ihe mgbochi> Oge> Bubata). Bubata SDC file emepụtara site na ngwá ọrụ Derive Constraint.
   – Mbubata * .ndc mgbochi files (Onye njikwa ihe mgbochi> NetlistAttributes> Bubata), ọ bụrụ na ọ dị.
10. Mmachi file na njikọ ngwá ọrụ
    – Na Constraint Manager, na-akpakọrịta * .pdc files ebe na ụzọ, * .sdc files idobe na ụzọ na nkwenye oge, yana * .ndc files iji chịkọta Netlist.
11. Mmejuputa nhazi zuru oke
    - Ebe na ụzọ, nyochaa oge na ike, hazie data mmalite na ncheta, yana mmemme file ọgbọ.
12. Kwado imewe ahụ
    - Kwado imewe ahụ na FPGA wee mebie dị ka ọ dị mkpa site na iji ngwaọrụ eji emebe nke Libero SoC design suite.

Nhazi akụrụngwa (Jụọ ajụjụ)

Nzọụkwụ mbụ n'ime usoro omenala bụ ịhazi ihe gị site na iji ọrụ ntụaka Libero (nke a na-akpọkwa ọrụ mbụ Libero na Tebụl 1-1). Na usoro ndị ọzọ, ị na-eji data sitere na ọrụ ntụnye aka a.
Ọ bụrụ na ị na-eji akụrụngwa ọ bụla edepụtara na mbụ, n'okpuru Overview N'ime imewe gị, mee usoro ndị akọwapụtara na ngalaba a.
Ọ bụrụ na ị naghị eji nke ọ bụla n'ime ihe ndị a dị n'elu, ị nwere ike ide RTL gị na mpụga Libero wee bubata ya ozugbo na ngwa Synthesis na Simulation gị. Ị nwere ike ịga n'ihu na ngalaba post-synthesis na naanị ibubata post-synthesis * .vm netlist gị n'ime ọrụ mmejuputa Libero ikpeazụ gị (nke a na-akpọkwa ọrụ Libero nke abụọ na Tebụl 1-1).
2.1 Nhazi akụrụngwa site na iji Libero (Jụọ ajụjụ)
Mgbe ịhọrọchara ihe ndị a ga-ejirịrị na listi bu ụzọ, mee usoro ndị a:

1. Mepụta oru ngo Libero ọhụrụ (Nhazi isi na ọgbọ): Họrọ ngwaọrụ na ezinaụlọ nke ị lekwasịrị anya imewe ikpeazụ gị.
2. Jiri otu ma ọ bụ karịa nke cores ndị a kpọtụrụ aha na Omenala Flow.
   a. Mepụta SmartDesign wee hazie isi ihe achọrọ wee mee ya ozugbo na ngwa SmartDesign.
   b. Kwalite ntụtụ niile n'ọkwa dị elu.
   c. Mepụta SmartDesign.
   d. Pịa ngwa ngwa Simulate ugboro abụọ (nke ọ bụla n'ime Pre-Synthesis ma ọ bụ Post-Synthesis ma ọ bụ nhọrọ nhazi nhazi) ka ịkpọku simulator. Ị nwere ike ịpụ na simulator mgbe akpọchara ya. Nzọụkwụ a na-emepụta simulation filedị mkpa maka ọrụ gị.

Ndụmọdụ: Ị ga-emerịrị usoro a ma ọ bụrụ na ịchọrọ ịmegharị atụmatụ gị na mpụga Libero.
Maka ozi ọzọ, ịhụ Simulating Your Design.
e. Chekwaa oru ngo gi - nke a bu oru nrụtụ aka gị.
2.2 Ngosipụta akụkụ (Jụọ ajụjụ)
Mgbe ị na-emepụta components gị, a set nke files na-eme maka mpaghara ọ bụla. Akuko nke akụrụngwa na-akọwapụta nhazi nke files emepụtara ma jiri ya mee ihe na usoro ọ bụla sochirinụ (Synthesis, Simulation, Firmware Generation, na ndị ọzọ). Akụkọ a na-enye gị ebe niile emepụtara files mkpa iji gaa n'ihu na Usoro Omenala. Ị nwere ike ịnweta akụrụngwa gosipụtara na mpaghara Akụkọ: Pịa Imepụta> Akụkọ iji mepee taabụ Akụkọ. Na taabụ akụkọ, ị na-ahụ setịpụ nke manifest.txt files (Ofeview), otu maka akụrụngwa ọ bụla ị mepụtara.
NDỤMỌDỤ: Ị ga-edozi akụrụngwa ma ọ bụ modul dị ka "mgbọrọgwụ"' iji hụ akụkụ ahụ pụtara file ọdịnaya dị na taabụ Akụkọ.
N'aka nke ọzọ, ị nwere ike ịnweta mkpesa ngosi nke onye ọ bụla files maka isi akụrụngwa ọ bụla emepụtara ma ọ bụ akụrụngwa SmartDesign sitere na / akụkụ / ọrụ / / / _manifest.txt ma ọ bụ / akụkụ / ọrụ / / _manifest.txt. Ị nwekwara ike ịnweta ihe ngosi file ọdịnaya nke mpaghara ọ bụla ewepụtara site na taabụ akụrụngwa ọhụrụ dị na Libero, ebe ndị file A na-akpọ ebe ndị a gbasara akwụkwọ ndekọ aha.Lekwasị anya na akụkọ ihe ngosi akụrụngwa ndị a:

• Ọ bụrụ na ị na-etinye cores ozugbo n'ime SmartDesign, gụọ ya file _manifest.txt.
• Ọ bụrụ na ị mepụtara components maka cores, gụọ ya _manifest.txt.

Ị ga-ejiri akụkọ ngosipụta akụkụ akụkụ niile na-emetụta imewe gị. Maka exampYa mere, ọ bụrụ na gị oru ngo nwere a SmartDesign na otu ma ọ bụ karịa isi components instantiated na ya na ị bu n'obi iji ha niile na gị ikpeazụ imewe, mgbe ahụ ị ga-ahọrọ. files nke edepụtara na nkọwapụta akụrụngwa nke akụrụngwa ndị ahụ niile maka ojiji n'usoro nhazi gị.
2.3 Ngosipụta nkọwa Files (Jụọ ajụjụ)
Mgbe imepee ihe ngosipụta akụrụngwa file, ị na-ahụ ụzọ ka files n'ime ọrụ Libero gị yana ntụnye aka ebe n'usoro nhazi iji jiri ha mee ihe. Ị nwere ike ịhụ ụdị ndị a files na ngosipụta file:

• HDL isi mmalite files maka niile Synthesis na Simulation ngwaọrụ
• Ihe mkpali files maka ngwa ịme anwansị niile
• Mmachi files

Ihe na-esote bụ ngosipụta akụkụ nke akụrụngwa PolarFire.Ụdị nke ọ bụla file dị mkpa downstream na gị imewe eruba. Akụkụ ndị na-esonụ na-akọwa ntinye nke files si na-egosi n'ime gị imewe eruba.

Ọgbọ mgbochi (Jụọ ajụjụ)

Mgbe ị na-eme nhazi na ọgbọ, hụ na ị ga-ede / mepụta ihe mgbochi SDC / PDC / NDC files maka imewe ibufe ha na Synthesis, Ebe-na ụzọ, na nyochaa ngwa ọrụ oge.
Jiri akụrụngwa ihe mgbochi na-abụghị nke Libero iji mepụta ihe mgbochi kama iji aka dee ha. Iji jiri ihe mgbochi mgbochi na mpụga gburugburu Libero, ị ga-emerịrị:

• Onye ọrụ na-eweta HDL, akụrụngwa HDL, yana mmachi SDC akụrụngwa files
• Ezipụta modul ọkwa dị elu
• Kọwaa ebe a ga-ewepụta mmachi ewepụtara files

Ihe mgbochi akụrụngwa SDC dị n'okpuru / akụkụ / ọrụ / / / ndekọ mgbe akụrụngwa nhazi na ọgbọ.
Maka nkọwa ndị ọzọ gbasara otu ị ga-esi wepụta ihe mgbochi maka imewe gị, lee Ihe Odide C—Mkpagide Na-akpata.

Ịmepụta atụmatụ gị (Jụọ ajụjụ)

Otu n'ime njirimara bụ isi nke Flow omenala bụ inye gị ohere iji njikọ nke ndị ọzọ
ngwá ọrụ n'èzí Libero. Usoro omenala na-akwado iji Synopsys SynplifyPro. Ka synthesize gị
oru ngo, jiri usoro a:

1. Mepụta ọrụ ọhụrụ n'ime ngwa Synthesis gị, na-ezubere otu ezinụlọ ngwaọrụ, nwụọ na ngwugwu dị ka ọrụ Libero ị mepụtara.
   a. Bubata RTL nke gị filedị ka ị na-emekarị.
   b. Tọọ mmepụta Synthesis ka ọ bụrụ Structural Verilog (.vm).
   Ndụmọdụ: Nhazi Verilog (.vm) bụ naanị usoro mmepụta njikọ akwadoro na PolarFire.
2. Bubata akụrụngwa HDL filebanye n'ọrụ Synthesis gị:
   a. Maka akụkụ ọ bụla na-egosipụta akụkọ: Maka nke ọ bụla file n'okpuru isi iyi HDL files maka ngwa Synthesis na Simulation niile, bubata ihe file banye Project Synthesis gị.
3. Bubata ihe file polarfire_syn_comps.v (ma ọ bụrụ na ị na-eji Synopsys Synplify) site na
   Ebe nwụnye>/data/aPA5M na ọrụ Synthesis gị.
4. Bubata SDC ewepụtara na mbụ file site na ngwa ihe mgbochi ewepụtara (lee Ihe Odide
   A—Sample SDC Constraints) n'ime Synthesis ngwá ọrụ. Nke a mmachi file na-amachibido ngwa ngwa njikọ iji nweta mmechi oge site na obere mbọ yana obere nhazi nhazi.

Ihe dị mkpa: 

• Ọ bụrụ na ị na-eme atụmatụ iji otu * .sdc file iji gbochie ebe-na ụzọ n'oge mmebe mmejuputa iwu, ị ga-ebubata * .sdc a n'ime ọrụ njikọ. Nke a bụ iji hụ na enweghị aha njirimara aha ihe na-adaba adaba na netlist synthesized na ebe-na-ụzọ mgbochi n'oge mmejuputa usoro nke nhazi usoro. Ọ bụrụ na itinyeghị nke a * .sdc file na usoro Synthesis, netlist ewepụtara site na Synthesis nwere ike daa nzọụkwụ ebe na ụzọ n'ihi na ahaghị ihe ahaziri ahaziri.
  a. Bubata njirimara Netlist * .ndc, ọ bụrụ na ọ bụla, n'ime ngwa Synthesis.
  b. Gbaa Synthesis.
• Ebe mmepụta ngwá ọrụ Synthesis gị nwere * .vm netlist file emepụtara post Synthesis. Ị ga-ebubata netlist n'ime ọrụ mmejuputa Libero iji gaa n'ihu na usoro nhazi.

Ịmepụta atụmatụ gị (Jụọ ajụjụ)

Iji mee ka imewe gị na mpụga Libero (ya bụ, iji gburugburu ịme anwansị gị na simulator), mee usoro ndị a:

1. Nhazi Files:
   a. Simulation tupu synthesis:
   • Bubata RTL gị n'ime ọrụ ịme anwansị gị.
   • Maka akụkụ ọ bụla na-egosipụta mkpesa.
   – Bubata nke ọ bụla file n'okpuru isi iyi HDL files maka ngwa Synthesis na Simulation niile n'ime ọrụ ịme anwansị gị.
   • Chịkọta ihe ndị a filedị ka ntuziaka simulator gị si dị.
   b. Simulation post-synthesis:
   • Bubata gị post-synthesis *.vm netlist (nke emebere na Synthesizing Your Design) n'ime ọrụ ịme anwansị gị wee chịkọta ya.
   c. Simulation post-layout:
   • Nke mbụ, mezuo mmejuputa atumatu gị (lee imezu atụmatụ gị). Gbaa mbọ hụ na ọrụ Libero ikpeazụ gị dị na steeti nhazi ọkwa.
   • Pịa ugboro abụọ n'ịwa BackAnnotated Files na mpio Ntụpụta nke Libero Design. Ọ na-emepụta abụọ files:
   /onye mmebe/ / _ba.v/vhd /onye mmebe/
   / _ba.sdf
   • Bubata ha abụọ a files n'ime ngwa ịme anwansị gị.
2. Ihe mkpali na nhazi files:
   a. Maka akụkụ ọ bụla gosipụtara mkpesa:
   • Detuo ihe niile files n'okpuru ihe mkpali Files maka akụkụ Ngwa ngwa Simulation niile gaa na ndekọ ndekọ nke ọrụ ịme anwansị gị.
   b. Gbaa mbọ hụ na Tcl ọ bụla files na ndepụta ndị bu ụzọ (na nzọụkwụ 2.a) na-ebu ụzọ gbuo, tupu mmalite nke ịme anwansị.
   c. UPROM.mem: Ọ bụrụ na ị na-eji isi UPROM n'ime imewe gị yana nhọrọ Jiri ọdịnaya maka ịme anwansị enyere maka otu ma ọ bụ karịa ndị ahịa nchekwa data ịchọrọ ịme, ị ga-eji pa4rtupromgen executable (pa4rtupromgen.exe na windo) mepụta UPROM.mem. file. The pa4rtupromgen executable na-ewe UPROM.cfg file dị ka ntinye site na edemede Tcl file wee wepụta UPROM.mem file achọrọ maka ịme anwansị. Nke a UPROM.mem file a ga-e copyomi ya na nchekwa simulation tupu ịgba ọsọ simulation. Otu exampna-egosi pa4rtupromgen executable ojiji na-nyere na ndị a nzọụkwụ. Ihe UPROM.cfg file dị na ndekọ / akụkụ / ọrụ / / n'ime oru ngo nke Libero nke i jiri weputa akụrụngwa UPROM.
   d. snvm.mem: Ọ bụrụ na ị na-eji isi ọrụ sistemu na imewe gị wee hazie taabụ sNVM dị na isi yana nhọrọ Jiri ọdịnaya maka ịme anwansị enyere maka otu ndị ahịa ma ọ bụ karịa nke ịchọrọ ịme, snvm.mem file na-akpaghị aka eme ka
   ndekọ / akụkụ / ọrụ / / n'ime oru ngo nke Libero nke i jiri weputa akụrụngwa Ọrụ Sistemu. Nke a snvm.mem file a ga-e copyomi ya na nchekwa simulation tupu ịgba ọsọ simulation.
3. Mepụta folda na-arụ ọrụ na obere nchekwa aha ya bụ simulation n'okpuru folda na-arụ ọrụ.
   The pa4rtupromgen executable na-atụ anya ọnụnọ nke simulation sub nchekwa na-arụ ọrụ nchekwa na * .tcl script etinye na simulation sub nchekwa.
4. Detuo UPROM.cfg file site na mbụ Libero oru ngo e kere maka akụrụngwa akụrụngwa n'ime na-arụ ọrụ nchekwa.
5. Tapawa iwu ndị a na edemede * .tcl wee tinye ya na nchekwa simulation emepụtara na nzọụkwụ 3.
   Sample * .tcl maka PolarFire na PolarFire Soc ngwaọrụ ezinụlọ iji mepụta URPOM.mem file
   sitere na UPROM.cfg
   set_ngwaọrụ -fam -anwụ -pkg
   set_input_cfg - ụzọ
   set_sim_mem - ụzọFile/UPROM.mem>
   gen_sim -use_init ụgha
   Maka aha ime kwesịrị ekwesị iji mee ihe maka anwụ na ngwugwu, lee * .prjx file nke mbụ Libero oru ngo (eji maka akụrụngwa akụrụngwa).
   A ghaghị ịtọ arụmụka use_init ka ọ bụrụ ụgha.
   Jiri set_sim_mem iwu ezipụta ụzọ na-aga na mmepụta file UPROM.mem ya bụ
   emepụtara n'elu ogbugbu nke edemede ahụ file na pa4rtupromgen executable.
6. Na ngwa ngwa ma ọ bụ cygwin Terminal, gaa na ndekọ ọrụ emepụtara na nzọụkwụ 3.
   Mezue iwu pa4rtupromgen na nhọrọ-script wee nyefee ya ederede *.tcl nke emepụtara na nzọụkwụ gara aga.
   Maka Windows
   /Designer/bin/pa4rtupromgen.exe \
   -script./simulation/ .tcl
   Maka Linux:
   /bin/pa4rtupromgen
   -script./simulation/ .tcl
7. Mgbe ịga nke ọma ogbugbu nke pa4rtupromgen executable, lelee na UPROM.mem. file emepụtara na ebe akọwapụtara n'iwu set_sim_mem na edemede * .tcl.
8. Iji mee ka sNVM mee, detuo snvm.mem file site na mbụ Libero oru ngo (eji maka nhazi akụrụngwa) banye n'ime nchekwa simulation dị elu nke ọrụ ịme anwansị gị iji mee simulation (n'èzí Libero SoC). Iji megharịa ọdịnaya UPROM, detuo UPROM.mem emepụtara file n'ime folda ịme anwansị dị elu nke ọrụ ịme anwansị gị iji mee ịme anwansị (na mpụga Libero SoC).

Ihe dị mkpa: Iji mee ka arụrụ ọrụ nke Ngwa SoC, budata ọba akwụkwọ simulation PolarFire achịkọtagoro wee bubata ha na gburugburu ịme anwansị gị dịka akọwara ebe a. Maka nkọwa ndị ọzọ, lee Ihe Odide B—Ibubata ọba akwụkwọ simulation n'ime Environment Simulation.

Na-eme atụmatụ gị (Jụọ ajụjụ)

Mgbe ịmechara simulation Synthesis na Post-Synthesis na gburugburu gị, ị ga-eji Libero ọzọ mejuputa atụmatụ gị n'ụzọ anụ ahụ, na-agba ọsọ oge na nyocha ike, wee mepụta mmemme gị. file.

1. Mepụta ọrụ Libero ọhụrụ maka mmejuputa anụ ahụ na nhazi nke imewe. Gbaa mbọ hụ na ị lekwasịrị anya otu ngwaọrụ dị na ọrụ ntụnye aka ị mepụtara na nhazi akụrụngwa.
2. Mgbe emechara ọrụ ngo, wepụ Synthesis site na yinye ngwá ọrụ dị na windo Flow Design (Project> Settings Settings> Design Flow> Uncheck Enable Synthesis).
3.  Bubata njikọ nbipute gị * .vm file banye n'ọrụ a, (File > Bubata > Verilog Netlist synthesized (VM)).
   Ndụmọdụ: A na-atụ aro ka ịmepụta njikọ na nke a file, nke mere na ọ bụrụ na ị resynthesize gị imewe, Libero mgbe niile na-eji ọhụrụ post-synthesis netlist.
   a. Na mpio imewe nhazi, rịba ama aha modul mgbọrọgwụ.
4. Bubata ihe mgbochi na ọrụ Libero. Jiri njikwa mgbochi ibubata *.pdc/*.sdc/*.ndc mgbochi.
   a. Bubata I/O * .pdc mmachi files (Onye njikwa ihe mgbochi> Àgwà m/O> Bubata).
   b. Bubata atụmatụ ala * .pdc mmachi files (Onye njikwa ihe mgbochi> Onye nhazi ụlọ> Bubata).
   c. Bubata * .sdc mmachi oge files (Onye njikwa ihe mgbochi> Oge> Bubata). Ọ bụrụ na imewe gị nwere nke ọ bụla n'ime cores edepụtara na Overview, hụ na ibubata SDC file emepụtara site na ngwa mgbochi mgbochi.
   d. Bubata * .ndc mmachi files (Onye njikwa ihe mgbochi> Njirimara Netlist> Bubata).
5. Mmachi mmekọ Files chepụta ngwaọrụ.
   a. Mepee njikwa ihe mgbochi (Jikwaa mmachi> Mepee njikwa mmachi View).
   Lelee igbe nlele ebe-na-ụzọ na nkwenye oge n'akụkụ mmachi file iji guzobe mmachi file na njikọ ngwá ọrụ. Jikọọ mmachi * .pdc na Ebe-na Ụzọ yana * .sdc na ma Ebe-na ụzọ yana nkwenye oge. Jikọọ * .ndc file iji chịkọta Netlist.
   Ndụmọdụ: Ọ bụrụ Ebe na ụzọ na-ada na nke a * .sdc mmachi file, wee bubata otu * .sdc a file ka synthesis na re-agba ọsọ njikọ.
6. Pịa Compile Netlist wee tinye ebe na ụzọ iji mezue usoro nhazi.
7. Ngwa Hazie Nhazi mmalite data na ihe ncheta na-enye gị ohere ibido ihe mgbochi imewe, dị ka LSRAM, µSRAM, XCVR (transceivers), na PCIe site na iji data echekwara na µPROM na-adịghị agbanwe agbanwe, sNVM, ma ọ bụ ebe nchekwa Flash SPI mpụga. Ngwá ọrụ ahụ nwere taabụ ndị a maka ịkọwapụta nkọwapụta nke usoro mmalite mmalite, nkọwapụta nke ndị ahịa mmalite, ndị ahịa data onye ọrụ.
   – Taabụ mmalite imewe
   - taabụ µPROM
   - sNVM tab
   – SPI Flash tab
   - Taabụ akwa RAM
   Jiri taabụ dị n'ime ngwa ahụ hazie data mmalite na ncheta imewe.Mgbe ịmechara nhazi ahụ, mee usoro ndị a iji hazie data mmalite:
   • Mepụta ndị ahịa mbido
   • Mepụta ma ọ bụ bupụ bitstream
   • Hazie ngwaọrụ
   Maka ozi zuru ezu maka otu esi eji ngwá ọrụ a, lee Libero SoC Design Flow User Guide. Maka ozi ndị ọzọ gbasara iwu Tcl ejiri hazie taabụ dị iche iche na ngwaọrụ wee kọwaa nhazi ebe nchekwa files (*.cfg), hụ Ntuziaka ntụaka iwu Tcl.
8. Mepụta mmemme File site na oru a ma jiri ya hazie FPGA gị.

Ihe odide ntụkwasị A—SampMgbochi SDC (Jụọ ajụjụ

Libero SoC na-ebute mmachi oge SDC maka ụfọdụ cores IP, dị ka CCC, OSC, Transceiver na ndị ọzọ. Ịfefe mmachi SDC iji chepụta ngwaọrụ na-abawanye ohere nke izute mmechi oge na obere mbọ yana obere nhazi nhazi. A na-enye ụzọ nhazi ọkwa zuru oke site na ihe atụ dị elu maka ihe niile eji eme ihe atụnyere na mmachi.
7.1 SDC oge mmachi (Jụọ ajụjụ)
N'ime ọrụ ntụaka isi nke Libero IP, mmachi SDC a dị elu file dị site na Constraint Manager (Flow Design> Mepee njikwa mmachi View > Ogologo oge > Ihe mgbochi).
Ihe dị mkpa: Lee nke a file iji tọọ mmachi SDC ma ọ bụrụ na imewe gị nwere CCC, OSC, Transceiver, na ihe ndị ọzọ. Gbanwee ụzọ nhazi ọkwa zuru oke, ọ bụrụ na ọ dị mkpa, ka ị kwekọọ n'usoro nhazi gị ma ọ bụ jiri ọrụ Derive_Constraints na nzọụkwụ dị na Mgbakwunye C - Nweta ihe mgbochi na ọkwa mpaghara SDC. file.
Chekwaa file gaa na aha dị iche wee bubata SDC file gaa na ngwa njikọ, Ngwá Ọrụ Ebe-na Ụzọ, na Nkwenye oge, dị ka mmachi SDC ọ bụla ọzọ. files.
7.1.1 SDC ewepụtara File (Jụọ ajụjụ)
# Nke a file emepụtara dabere na isi iyi SDC na-esote files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
TRANSMIT_PLL/TRANSMIT_PLL_0/transmit_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PCIE_INITIATOR/ PCIE_INITIATOR_0/ PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** Mgbanwe ọ bụla na nke a file ga-efunahụ ma ọ bụrụ na emegharịrị ihe mgbochi ndị ewepụtara. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} - oge 6.25
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } ] create_clock -name {REF_CLK_PAD_P} -period 10 [ nweta_ports {REF_CLK_PAD_P} ] create_clock - aha {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/tx
DIV_CLK} - oge 8
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK} ] mepụta_generated_clock - aha {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_P_CC0/inst_CC
OUT0} -amụba_site na 25 -nkewa_site na 32 -isi iyi
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -nha 0
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0} ] create_generated_clock - aha {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT1} -amụba_site na 25 -nkewa_site na 32 -isi iyi
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -nha 0
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1} ] create_generated_clock - aha {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT2} -amụba_site na 25 -nkewa_site na 32 -isi iyi
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -nha 0
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2} ] create_generated_clock - aha {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/inst_CC_C
OUT3} -amụba_site na 25 -nkewa_site na 64 -isi iyi
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0} ] -nha 0
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3} ] mepụta_generated_clock - aha {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_DIMZ
Y_DIV} -nkewa_site na 2 -isi iyi
[ nweta_pins {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CLK_DIV_0/I_CD/A} ] set_false_path -through [ get_nets { DMA_INITIATOR_inst_0/ARESETN*} ] set_false_path -site na [ get_cells { DMA_INITIATOR_inst_160/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray*} ] -na [ nweta_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1*} ] set_false_path -site na [ nweta_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray*} ] -na [ nweta_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1*} ] set_false_path -through [ nweta_nets {FIC0_INITIATOR_inst_0/ARESETN*} ] set_false_ụzọ -na [ nweta_pins { PCIE/PF_PCIE_C0_0/ PCIE_1/INTERRUPT[0] PCIE/PF_0/PCIE_C0
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/ PCIE_1/MPERST_N} ] set_false_path -site na [ get_pins { PCIE/PF_PCIE_C0_0/ PCIE_1/TL_CLK} ] set_false_path -through [get_nets {PCIE_NITIA] Ihe Mgbakwunye B—Na-ebubata ọba akwụkwọ simulation n'ime gburugburu emume ngosi (Jụọ ajụjụ)
Simulator ndabara maka simulation RTL na Libero SoC bụ ModelSim ME Pro.
Ọbá akwụkwọ achịkọtara tupu oge eruo maka simulator ndabara dị na ntinye Libero na ndekọ /Designer/lib/modelsimpro/precompiled/vlog for® ezinụlọ akwadoro. Libero SoC na-akwado mbipụta simulators ndị ọzọ nke ModelSim, Questasim, VCS, Xcelium.
, HDL na-arụ ọrụ na Riviera Pro. Budata ọba akwụkwọ achịkọtara tupu oge eruo Libero SoC v12.0 na mgbe e mesịrị dabere na simulator na ụdị ya.
Yiri gburugburu Libero, run.do file ga-emerịrị ka ịme simulation n'èzí Libero.
Mepụta ọsọ ọsọ.do file nke nwere iwu iji guzobe ọba akwụkwọ maka nsonaazụ mkpokọta, eserese ọbá akwụkwọ, mkpokọta, na ịme anwansị. Soro usoro ndị a ka ịmepụta isi run.do file.

1. Mepụta ọba akwụkwọ ezi uche dị na ya iji chekwaa nsonaazụ nchịkọta site na iji vlib iwu vlib presynth.
2. Jiri vmap iwu vmap depụta aha ọba akwụkwọ ezi uche dị na ndekọ ndekọ aha ọbá akwụkwọ achịkọtaburu .
3. Mepụta isi iyi files — jiri iwu mkpokọta asụsụ akọwapụtara maka ikpokọta imewe files n'ime ndekọ ọrụ.
   - vlog maka .v/.sv
   - vcom maka .vhd
4. Bujuo imewe maka ịme anwansị site na iji vsim iwu site na ịkọwa aha modul ọ bụla dị elu.
5. Jiri iwu ọsọ mee ka imewe dị.
   Mgbe ịmechara nhazi ahụ, a na-edozi oge ịme anwansị ka ọ bụrụ efu, ma ị nwere ike tinye iwu ọsọ iji malite ịme simulation.
   Na mpio ihe odide simulator, mee run.do file ka run.do na-agba simulation. Sample ọsọ.do file dị ka ndị a.

ji nwayọọ tọọ ACTELLIBNAME PolarFire ji nwayọọ tọọ PROJECT_DIR "W:/Test/Basic_test" ma ọ bụrụ
{[file adị presynth/_info]} {na-ekwu "INFO: presynth Library nke Simulation dị"} ọzọ
{ file delete -force presynth vlib presynth } vmap presynth presynth vmap PolarFire
"X:/Libero/Designer/lib/modelsimpro/precompiled/vlog/PolarFire" vlog -sv -work presynth
"${PROJECT_DIR}/hdl/top.v" vlog "+incdir+${PROJECT_DIR}/stimulus" -sv -work presynth "$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb tinye ife /tb/*
na-agba ọsọ 1000ns log /tb/* pụọ

Ihe Odide C — Nweta Mmachi (Jụọ ajụjụ)

Ihe mgbakwunye a na-akọwa iwu Derive Constraints Tcl.
9.1 Nweta mmachibido iwu Tcl (Jụọ ajụjụ)
Utility derive_constraints na-enyere gị aka inweta ihe mgbochi site na RTL ma ọ bụ onye nhazi na mpụga ebe imewe Libero SoC. Iji wepụta ihe mgbochi maka imewe gị, ị ga-achọ HDL onye ọrụ, akụkụ HDL na ihe mgbochi akụrụngwa. files. Akụkụ SDC na-egbochi files dị n'okpuru / akụkụ / ọrụ / / / ndekọ mgbe akụrụngwa nhazi na ọgbọ.
Ihe mgbochi akụrụngwa ọ bụla file nwere iwu set_component tcl (na-akọwapụta aha akụrụngwa) yana ndepụta ihe mgbochi ewepụtara mgbe nhazichara ya. A na-emepụta ihe mgbochi na-adabere na nhazi ahụ ma bụrụ kpọmkwem maka akụkụ ọ bụla.
Example 9-1. Mmachi akụrụngwa File maka PF_CCC Core
Nke a bụ example nke ihe mgbochi akụrụngwa file maka isi PF_CCC:
set_component PF_CCC_C0_PF_CCC_C0_0_PF_CCC
# Microchip Corp.
# Ụbọchị: 2021-Ọkt-26 04:36:00
# Elekere ntọala maka PLL #0
create_clock -period 10 [ nweta_pins {pll_inst_0/REF_CLK_0} ] create_generated_clock -divide_by 1 -source [ nweta_pins {pll_inst_0/
REF_CLK_0 } ] -phase 0 [ get_pins {pll_inst_0/OUT0} ] N'ebe a, create_clock na create_generated_clock bụ ntụaka na mmepụta elekere n'otu n'otu, nke a na-esite na nhazi ahụ.
9.1.1 Na-arụ ọrụ na derive_constraints Utility (Jụọ ajụjụ)
Ihe mgbochi na-agafe site na nhazi ahụ wee kenye mmachi ọhụrụ maka ihe atụ ọ bụla nke akụrụngwa dabere na akụrụngwa SDC enyere na mbụ. files. Maka clocks ntụaka CCC, ọ na-agbasa azụ site na imewe iji chọta isi iyi nke elekere ntụaka. Ọ bụrụ na isi mmalite bụ I/O, a ga-edobe mmachi elekere na I/O. Ọ bụrụ na ọ bụ mmepụta CCC ma ọ bụ ebe elekere ọzọ (maka example, Transceiver, oscillator), ọ na-eji elekere si n'akụkụ nke ọzọ na-akọ ịdọ aka ná ntị ma ọ bụrụ na etiti oge adabaghị. Ihe mgbochi ga-ekenye ihe mgbochi maka ụfọdụ macros dị ka on-chip oscillators ma ọ bụrụ na ị nwere ha na RTL gị.
Iji rụọ ọrụ derive_constraints, ị ga-eburịrị .tcl file arụmụka ahịrị iwu yana ozi ndị a n'usoro akọwapụtara.

1. Ezipụta ozi ngwaọrụ site na iji ozi dị na ngalaba set_device.
2. Kpebie ụzọ na RTL files iji ozi dị na ngalaba read_verilog ma ọ bụ read_vhdl.
3. Tọọ modul dị elu site na iji ozi dị na ngalaba set_top_level.
4. Ezipụta ụzọ gaa na mpaghara SDC files iji ozi dị na ngalaba read_sdc ma ọ bụ read_ndc.
5. Mee ihe ahụ filena-eji ozi dị na ngalaba derive_constraints.
6.  Kọwaa ụzọ gaa na mmachi ndị SDC ewepụtara file iji ozi dị na ngalaba write_sdc ma ọ bụ write_pdc ma ọ bụ write_ndc.

Example 9-2. Mmezu na ọdịnaya nke ewepụtara.tcl File
Ihe na-esonụ bụ example iwu-akara arụmụka ime ihe derive_constraints utility.
$ /bin{64}/deriv_constraints derive.tcl
Ọdịnaya nke ewepụtara.tcl file:
# Ozi ngwaọrụ
set_device -ezinụlọ PolarFire - anwụ MPF100T -speed -1
# RTL files
read_verilog -mode system_verilog project/component/work/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
read_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
read_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd}
# Ngwa SDC files
set_top_level {xcvr1}
read_sdc -akụrụngwa {project/component/work/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
read_sdc - akụrụngwa {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
# Jiri iwu derive_constraint
eweputa_mgbochi
# SDC/PDC/NDC nsonaazụ files
write_sdc {project/constraint/xcvr1_derived_constraints.sdc}
write_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 set_ngwaọrụ (Jụọ ajụjụ)
Nkọwa
Ezipụta aha ezinụlọ, aha anwụ na ọkwa ọsọ.
set_ngwaọrụ - ezinụlọ -anwụ -ọsọ
Arụmụka

Oke	Ụdị	Nkọwa
-ezinụlọ	Ụdọ	Ezipụta aha ezinụlọ. Ụkpụrụ enwere ike bụ PolarFire®, PolarFire SoC.
-anwụ	Ụdọ	Ezipụta aha anwụ.
-ọsọ	Ụdọ	Ezipụta ọkwa ọsọ ngwaọrụ. Ụkpụrụ nwere ike ịbụ STD ma ọ bụ -1.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Oke achọrọ — anwụ adịghị	Nhọrọ anwụ bụ iwu na a ga-akọwarịrị ya.
NJR	Amaghị anwụ 'MPF30'	Uru nke -die nhọrọ ezighi ezi. Hụ ndepụta ụkpụrụ enwere ike na nkọwa nhọrọ.
NJR	Parameter — die na-efu efu uru	A na-akọwapụta nhọrọ anwụ anwụ na-enweghị uru.
NJR	Oke achọrọ — ezinaụlọ na-efu	Nhọrọ ezinụlọ bụ iwu na a ga-akọwarịrị ya.
NJR	Ezinụlọ amaghi ama 'PolarFire®'	Nhọrọ ezinụlọ adịghị mma. Hụ ndepụta ụkpụrụ enwere ike na nkọwa nhọrọ.

………… gara n'ihu
Koodu mperi	Ozi mperi	Nkọwa
NJR	Parameter — uru ezinụlọ na-efu	A na-akọwapụta nhọrọ ezinụlọ na-enweghị uru.
NJR	Oke achọrọ—ọsọ adịghị	Nhọrọ ọsọ ọsọ bụ iwu na a ga-akọwarịrị ya.
NJR	Ọsọ amaghị ama' '	Nhọrọ ọsọ ọsọ adịghị mma. Hụ ndepụta ụkpụrụ enwere ike na nkọwa nhọrọ.
NJR	Parameter-ọsọ na-efu uru	A na-akọwapụta nhọrọ ọsọ ọsọ na-enweghị uru.

Example
set_device -family {PolarFire} -die {MPF300T_ES} -speed -1
set_ngwaọrụ -ezinụlọ SmartFusion 2 -die M2S090T -speed -1
9.1.3 ọgụgụ_verilog (Jụọ ajụjụ)
Nkọwa
Gụọ otu Verilog file iji Verific.
read_verilog [-lib ] [-ụdị ]fileaha>
Arụmụka

Oke	Ụdị	Nkọwa
-lib	Ụdọ	Ezipụta ọbá akwụkwọ nke nwere modul ndị a ga-agbakwunye n'ọbá akwụkwọ ahụ.
-ụdị	Ụdọ	Ezipụta ọkọlọtọ Verilog. Ụkpụrụ nwere ike ịbụ verilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. Ụkpụrụ enweghị mmetụta. Ihe ndabara bụ verilog_2k.
fileaha	Ụdọ	Verilog file aha.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Parameter — lib na-efu uru	A na-akọwapụta nhọrọ lib na-enweghị uru.
NJR	Parameter — ụkpụrụ efu efu	A na-akọwapụta nhọrọ ọnọdụ na-enweghị uru.
NJR	Ụdị amaghi ama ' '	Amaghị ụdị verilog akọwapụtara. Hụ ndepụta nke ụdị verilog nwere ike ime na nkọwa nhọrọ ọnọdụ.
NJR	Oke achọrọ file aha efu	Enweghị verilog file a na-enye ụzọ.
NJR	Ọ dara n'ihi nzacha Verific	Njehie syntax na verilog file. Enwere ike ịhụ nzacha Verific na njikwa n'elu ozi njehie.
NJR	set_ngwaọrụ anaghị akpọ	akọwapụtaghị ozi ngwaọrụ. Jiri iwu set_device kọwaa ngwaọrụ ahụ.

Example
read_verilog -mode system_verilog {component/work/top/top.v}
read_verilog -mode system_verilog_mfcu design.v
9.1.4 gụọ_vhdl (Jụọ ajụjụ)
Nkọwa
Tinye VHDL file banye na listi VHDL files.
gụọ_vhdl [-lib ] [-ụdị ]fileaha>
Arụmụka

Oke	Ụdị	Nkọwa
-lib	—	Ezipụta ọbá akwụkwọ ebe a ga-agbakwunye ọdịnaya ya.
-ụdị	—	Na-akọwapụta ọkọlọtọ VHDL. Ihe ndabara bụ VHDL_93. Ụkpụrụ enwere ike bụ vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. Ụkpụrụ enweghị mmetụta.
fileaha	—	VHDL file aha.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Parameter — lib na-efu uru	A na-akọwapụta nhọrọ lib na-enweghị uru.
NJR	Parameter — ụkpụrụ efu efu	A na-akọwapụta nhọrọ ọnọdụ na-enweghị uru.
NJR	Ụdị amaghi ama ' '	Amaghị ụdị VHDL akọwapụtara. Hụ ndepụta nke ụdị VHDL enwere ike na nkọwa nhọrọ ọnọdụ.
NJR	Oke achọrọ file aha efu	Enweghị VHDL file a na-enye ụzọ.
NJR	Enweghị ike ịdebanye aha invalid_path.v file	VHDL akọwapụtara file adịghị adị ma ọ bụ enweghị ikike ịgụ ihe.
NJR	set_ngwaọrụ anaghị akpọ	akọwapụtaghị ozi ngwaọrụ. Jiri iwu set_device kọwaa ngwaọrụ ahụ.

Example
gụọ_vhdl -mode vhdl_2008 osc2dfn.vhd
gụọ_vhdl {hdl/top.vhd}
9.1.5 set_top_level (Jụọ ajụjụ)
Nkọwa
Ezipụta aha modul ọkwa dị elu na RTL.
set_top_level [-lib ]
Arụmụka

Oke	Ụdị	Nkọwa
-lib	Ụdọ	Ọbá akwụkwọ ka ịchọọ modul ma ọ bụ ihe dị n'ọkwa dị elu (Nhọrọ).
aha	Ụdọ	Modul dị elu ma ọ bụ aha ụlọ ọrụ.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Ọkwa dị elu achọrọ na-efu	Nhọrọ ọkwa dị elu bụ iwu na a ga-akọwarịrị ya.
NJR	Parameter — lib na-efu uru	A na-akọwapụta nhọrọ lib na-enweghị ụkpụrụ.
NJR	Enweghị ike ịchọta ọkwa dị elu n'ọbá akwụkwọ	A kọwapụtaghị modul elu-elu n'ọbá akwụkwọ enyere. Iji dozie njehie a, a ga-edozirịrị modul ma ọ bụ aha ọba akwụkwọ kacha elu.
NJR	Nkewa nke ọma dara	Njehie na usoro nkọwa RTL. Enwere ike ịhụ ozi njehie site na njikwa.

Example
set_top_level {n'elu}
set_top_level -lib hdl n'elu
9.1.6 read_sdc (Jụọ ajụjụ)
Nkọwa
Gụọ otu SDC file banye nchekwa data akụrụngwa.
read_sdc - akụrụngwafileaha>
Arụmụka

Oke	Ụdị	Nkọwa
- akụkụ	—	Nke a bụ ọkọlọtọ amanyere iwu maka read_sdc iwu mgbe anyị nwetara ihe mgbochi.
fileaha	Ụdọ	Ụzọ na SDC file.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Oke achọrọ file aha efu.	Nhọrọ nke amanyere iwu file akpọpụtaghị aha.
NJR	SDC file <file_ụzọ> enweghị ike ịgụ ya.	SDC akọwapụtara file enweghị ikike ịgụ akwụkwọ.
NJR	Enweghị ike imepefile_ụzọ> file.	Ndị SDC file adịghị adị. A ga-edozirịrị ụzọ ahụ.
NJR	Iwu set_component na-efufile_ụzọ> file	Akụkụ akọwapụtara nke SDC file anaghị akọwapụta akụrụngwa.

Koodu mperi	Ozi mperi	Nkọwa
NJR	<List of errors from sdc file>	Ndị SDC file nwere iwu sdc ezighi ezi. Maka example, mgbe enwere mperi na mgbochi set_multicycle_path: Njehie mgbe ị na-eme iwu read_sdc: infile_ụzọ> file: Erro na iwu set_multicycle_path: Amaghi ama oke [get_cells {reg_a}].

Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 read_ndc (Jụọ ajụjụ)
Nkọwa
Gụọ otu NDC file banye nchekwa data akụrụngwa.
read_ndc - akụkụfileaha>
Arụmụka

Oke	Ụdị	Nkọwa
- akụkụ	—	Nke a bụ ọkọlọtọ amanyere iwu maka read_ndc iwu mgbe anyị nwetara ihe mgbochi.
fileaha	Ụdọ	Ụzọ na NDC file.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Enweghị ike imepefile_ụzọ> file	NDC file adịghị adị. A ga-edozirịrị ụzọ ahụ.
NJR	Oke achọrọ—AtclParamO_ na-efu.	Nhọrọ nke amanyere iwu fileakpọpụtaghị aha.
NJR	Oke achọrọ — akụrụngwa na-efu.	Nhọrọ akụrụngwa bụ iwu na a ga-akọwarịrị ya.
NJR	NDC file 'file_path>' enweghị ike ịgụ.	NDC akọwapụtara file enweghị ikike ịgụ akwụkwọ.

Example
read_ndc -akụrụngwa {component/work/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 na-ebute ihe mgbochi (Jụọ ajụjụ)
Nkọwa
Ngwa ngwa ngwa SDC files n'ime nchekwa data ọkwa-ichepụta.
eweputa_mgbochi
Arụmụka

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	A kọwaghị ọkwa dị elu	Nke a pụtara na akọwapụtaghị modul ma ọ bụ ihe dị n'elu. Iji dozie oku a, wepụta ya set_top_level iwu tupu derive_constraints iwu.

Example
eweputa_mgbochi
9.1.9 write_sdc (Jụọ ajụjụ)
Nkọwa
Na-ede mmachi file na usoro SDC.
dee_sdcfileaha>
Arụmụka

Oke	Ụdị	Nkọwa
<fileaha>	Ụdọ	Ụzọ na SDC file a ga-emepụta. Nke a bụ nhọrọ amanyere iwu. Ọ bụrụ na file dị, a ga-edegharị ya.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Enweghị ike imepefile ụzọ> file.	File ụzọ adịghị mma. Lelee ma akwụkwọ ndekọ aha nne na nna dị.
NJR	SDC file 'file ụzọ >' adịghị ede.	SDC akọwapụtara file enweghị ikike ide.
NJR	Oke achọrọ file aha efu.	Ndị SDC file ụzọ bụ nhọrọ amanyere ma a ga-akọwarịrị ya.

Example
dee_sdc "derived.sdc"
9.1.10 write_pdc (Jụọ ajụjụ)
Nkọwa
Na-ede ihe mgbochi anụ ahụ (naanị ihe mgbochi).
dee_pdcfileaha>
Arụmụka

Oke	Ụdị	Nkọwa
<fileaha>	Ụdọ	Ụzọ na PDC file a ga-emepụta. Nke a bụ nhọrọ amanyere iwu. Ọ bụrụ na file ụzọ dị, a ga-edegharị ya.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Enweghị ike imepefile ụzọ> file	Nke file ụzọ adịghị mma. Lelee ma akwụkwọ ndekọ aha nne na nna dị.
NJR	PDC file 'file ụzọ >' enweghị ike ide.	PDC akọwapụtara file enweghị ikike ide.
NJR	Oke achọrọ file aha efu	Ọnụ ego nke PDC file ụzọ bụ nhọrọ amanyere ma a ga-akọwarịrị ya.

Example
write_pdc "derived.pdc"
9.1.11 write_ndc (Jụọ ajụjụ)
Nkọwa
Na-ede ihe mgbochi NDC n'ime a file.
dee_ndcfileaha>
Arụmụka

Oke	Ụdị	Nkọwa
fileaha	Ụdọ	Ụzọ na NDC file a ga-emepụta. Nke a bụ nhọrọ amanyere iwu. Ọ bụrụ na file dị, a ga-edegharị ya.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Enweghị ike imepefile_ụzọ> file.	File ụzọ adịghị mma. Akwụkwọ ndekọ aha nne na nna adịghị.
NJR	NDC file 'file_path>' anaghị ede ede.	NDC akọwapụtara file enweghị ikike ide.
NJR	Oke achọrọ _AtclParamO_ na-efu.	NDC file ụzọ bụ nhọrọ amanyere ma a ga-akọwarịrị ya.

Example
write_ndc "derived.ndc"
9.1.12 add_include_path (Jụọ ajụjụ)
Nkọwa
Na-akọwapụta ụzọ ịchọọ gụnyere files mgbe ị na-agụ RTL files.
ụzọ tinye_include_ụzọ
Arụmụka

Oke	Ụdị	Nkọwa
ndekọ	Ụdọ	Na-akọwapụta ụzọ ịchọọ gụnyere files mgbe ị na-agụ RTL files. Nhọrọ a bụ iwu.

Ụdị nloghachi	Nkọwa
0	Iwu gara nke ọma.

Ụdị nloghachi	Nkọwa
1	Iwu dara. Enwere mperi. Ị nwere ike ịhụ ozi njehie na njikwa.

Ndepụta mmejọ

Koodu mperi	Ozi mperi	Nkọwa
NJR	Oke achọrọ gụnyere ụzọ efu.	Nhọrọ ndekọ aha bụ iwu na a ga-enyerịrị ya.

Mara: Ọ bụrụ Ụzọ ndekọ aha adịghị mma, mgbe ahụ add_include_path ga-agafe na-enweghị njehie.
Otú ọ dị, read_verilog/read_vhd iwu ga-ada n'ihi Verific's parser.
Example
add_include_path akụrụngwa/ọrụ/COREABC0/COREABC0_0/rtl/vlog/isi

Akụkọ ngbanwe (Jụọ ajụjụ)

Akụkọ ngbanwe ahụ na-akọwa mgbanwe ndị etinyere na akwụkwọ ahụ. Edepụtara mgbanwe ndị a site na ntughari, malite na mbipụta kachasị ugbu a.

Ndozigharị	Ụbọchị	Nkọwa
F	08/2024	A na-eme mgbanwe ndị a na ngbanwe a: • Nkebi emelitere Ihe Okike B — Na-ebubata ọba akwụkwọ simulation na gburugburu Simulation.
E	08/2024	A na-eme mgbanwe ndị a na ngbanwe a: • ngalaba emelitere gafereview. • Ngalaba emelitere SDC ewepụtara File. • Nkebi emelitere Ihe Okike B — Na-ebubata ọba akwụkwọ simulation na gburugburu Simulation.
D	02/2024	Ewepụtara akwụkwọ a na Libero 2024.1 SoC Design Suite na-enweghị mgbanwe site na v2023.2. Ngalaba emelitere na-arụ ọrụ na derive_constraints Utility
C	08/2023	Ewepụtara akwụkwọ a na Libero 2023.2 SoC Design Suite na-enweghị mgbanwe site na v2023.1.
B	04/2023	Ewepụtara akwụkwọ a na Libero 2023.1 SoC Design Suite na-enweghị mgbanwe site na v2022.3.
A	12/2022	Ndozigharị izizi.

Nkwado FPGA Microchip
Otu ngwaahịa Microchip FPGA na-eji ọrụ nkwado dị iche iche kwado ngwaahịa ya, gụnyere Ọrụ Ndị Ahịa, Ụlọ Ọrụ Nkwado nka na ụzụ Ndị Ahịa, a websaịtị, na ụlọ ahịa ahịa zuru ụwa ọnụ.
A na-atụ aro ka ndị ahịa gaa leta akụrụngwa Microchip n'ịntanetị tupu ha akpọtụrụ nkwado n'ihi na o yikarịrị ka azalarị ajụjụ ha.
Kpọtụrụ Ụlọ Ọrụ Nkwado nka na ụzụ site na websaịtị na www.microchip.com/support. Kwuo nọmba akụkụ ngwaọrụ FPGA, họrọ udi ikpe dabara adaba, wee bulite imewe files mgbe ị na-ekepụta ikpe nkwado teknụzụ.
Kpọtụrụ ọrụ ndị ahịa maka nkwado ngwaahịa na-abụghị teknụzụ, dị ka ọnụahịa ngwaahịa, nkwalite ngwaahịa, mmelite ozi, ọkwa ịtụ na ikike.

• Site na North America, kpọọ 800.262.1060
• Site na ụwa ndị ọzọ, kpọọ 650.318.4460
• Fax, si n'ebe ọ bụla n'ụwa, 650.318.8044

Ozi Microchip
Microchip Websaịtị
Microchip na-enye nkwado ntanetị site na anyị websaịtị na www.microchip.com/. Nke a weba na-eji saịtị eme ihe files na ozi dị mfe maka ndị ahịa. Ụfọdụ ọdịnaya dị gụnyere:

• Nkwado ngwaahịa – Ibé akwụkwọ data na errata, ndetu ngwa na sampmmemme, akụrụngwa imewe, ntuziaka onye ọrụ na akwụkwọ nkwado ngwaike, ewepụtara sọftụwia kacha ọhụrụ yana sọftụwia echekwara
• Nkwado nka na ụzụ izugbe - Ajuju a na-ajụkarị (FAQ), arịrịọ nkwado teknụzụ, otu mkparịta ụka n'ịntanetị, ndepụta ndị otu mmemme mmebe Microchip
• Azụmahịa nke Microchip – ntuziaka onye na-ahọpụta ngwaahịa na ịtụ iwu, mbipụta akwụkwọ akụkọ Microchip kacha ọhụrụ, ndepụta nke nzukọ ọmụmụ na mmemme, ndepụta nke ụlọ ahịa Microchip, ndị nkesa na ndị nnọchi anya ụlọ ọrụ mmepụta ihe.

Ọrụ ngosi mgbanwe ngwaahịa
Ọrụ ngosi mgbanwe ngwaahịa Microchip na-enyere ndị ahịa aka ugbu a na ngwaahịa Microchip. Ndị debanyere aha ga-enweta ọkwa email mgbe ọ bụla enwere mgbanwe, mmelite, nlegharị anya ma ọ bụ errata metụtara ezinụlọ ngwaahịa akọwapụtara ma ọ bụ ngwa mmepe nke mmasị. Iji debanye aha, gaa na www.microchip.com/pcn ma soro ntuziaka ndebanye aha.

Nkwado ndị ahịa
Ndị na-eji ngwaahịa Microchip nwere ike ịnweta enyemaka site na ọtụtụ ọwa:

• Onye nkesa ma ọ bụ onye nnọchi anya
• Ụlọ ọrụ ire ahịa mpaghara
• Injinia Ngwọta agbakwunyere (ESE)
• Nkwado ndị teknuzu

Ndị ahịa kwesịrị ịkpọtụrụ onye nkesa ha, onye nnọchi anya ma ọ bụ ESE maka nkwado. Ọfịs ahịa mpaghara dịkwa maka inyere ndị ahịa aka. Agụnyere ndepụta ụlọ ọrụ ahịa na ebe n'ime akwụkwọ a. Nkwado nka na ụzụ dị site na websaịtị na: www.microchip.com/support
Njirimara Nchekwa Koodu Ngwaọrụ Microchip
Rịba ama nkọwa ndị a nke njirimara nchedo koodu na ngwaahịa Microchip:

• Ngwaahịa Microchip na-ezute nkọwapụta dị na mpempe data Microchip ha.
• Microchip kwenyere na ezinaụlọ nke ngwaahịa ya nwere nchekwa mgbe ejiri ya n'ụzọ achọrọ, n'ime nkọwapụta ọrụ yana n'okpuru ọnọdụ nkịtị.
• Ụkpụrụ Microchip na-eji ike na-echebe ikike ikike ọgụgụ isi ya. Mgbalị imebi njirimara nchedo koodu nke ngwaahịa Microchip bụ nke amachibidoro nke ọma ma nwee ike imebi iwu nwebiisinka nke Millennium Digital.
• Ma Microchip ma ọ bụ ndị nrụpụta semiconductor ọ bụla enweghị ike ikwe nkwa nchekwa nke koodu ya. Nchedo koodu apụtaghị na anyị na-ekwe nkwa na ngwaahịa a "enweghị ike imebi". Nchekwa koodu na-agbanwe mgbe niile. Microchip agba mbọ na-aga n'ihu na-emeziwanye njirimara nchedo koodu nke ngwaahịa anyị.

Akwụkwọ Ozi Iwu
Enwere ike iji akwụkwọ a na ozi dị n'ime ya naanị site na ngwaahịa Microchip, gụnyere iji chepụta, nwalee ma jikọta ngwaahịa Microchip na ngwa gị. Iji ozi a n'ụzọ ọ bụla ọzọ mebiri usoro ndị a. A na-enye ozi gbasara ngwa ngwaọrụ naanị maka ịdị mma gị yana mmelite nwere ike dochie ya. Ọ bụ ọrụ gị ịhụ na ngwa gị dabara na nkọwapụta gị. Kpọtụrụ ụlọ ọrụ ịre ahịa Microchip mpaghara gị maka nkwado ọzọ ma ọ bụ nweta nkwado ọzọ na www.microchip.com/en-us/support/design-help/client-support-services.
Ozi a bụ MICROCHIP “DỊ KA Ọ BỤ”. MICROCHIP emeghị nnochite anya ma ọ bụ akwụkwọ ikike n'ụdị ọ bụla ma ọ bụ nkwupụta ma ọ bụ akọwapụta ya, edere ma ọ bụ n'ọnụ, iwu ma ọ bụ nke ọzọ, metụtara ozi ahụ gụnyere mana ọnweghị oke n'akwụkwọ ozi ọ bụla na-akwadoghị, iwu na-akwadoghị. Mgbakwunyere ọnọdụ ya, ogo ya, ma ọ bụ arụmọrụ ya. Ọ BỤGHỊ ỌMỤNỤ Ọ BỤGHỊ MICROCHIP GA-AKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỤKWỌ Ọ BỤLA N'ỤDỊ Ọ BỤLA OZI Ọ BỤLA NDỊ MMADỤ MA Ọ BỤ NDỊ MMADỤ. IHE IKE IKE MA ọ bụ mmebi iwu dị n'ihu. Ruo n'ụzọ zuru ezu iwu kwadoro, MICROCHIP'S TOTAL IBLIability na ebubo niile n'ụzọ ọ bụla metụtara ozi ma ọ bụ ya ojiji agaghị agafe ego nke ụgwọ, ma ọ bụrụ na ọ bụla, na ị kwụrụ ozugbo ka ọ gwa ya.
Iji ngwaọrụ Microchip na nkwado ndụ yana/ma ọ bụ ngwa nchekwa bụ kpamkpam n'ihe ize ndụ nke onye zụrụ ya, onye na-azụ ya kwenyere ịgbachitere, kwụọ ụgwọ ma jide Microchip na-adịghị emerụ ahụ site na mmebi ọ bụla, lams, suit, ma ọ bụ mmefu sitere na ụdị ojiji ahụ. Ọnweghị ikike ebugara, n'ezoghị ọnụ ma ọ bụ n'ụzọ ọzọ, n'okpuru ikike ikike ọgụgụ isi Microchip ọ gwụla ma ekwuputara ya.
Akara ụghalaahia
Aha Microchip na akara ngosi, akara Microchip, Adaptec, AVR, akara AVR, AVR Freaks, BestTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXXSty MediaLB, megaAVR, Microsemi, Microsemi logo, ọtụtụ, akara ngosi, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, akara PIC32, PolarFire, Prochip Designer, QTouch, SAM-BA, Seniity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, na XMEGA bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Incorporated na USA na obodo ndị ọzọ.
AgileSwitch, ClockWorks, The agbakwunyere Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, na ZL bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Incorporated na USA
Nkwụsị igodo dị n'akụkụ, AKS, Analog-maka-Digital Age, Capacitor ọ bụla, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM Average Net , DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGAT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Njikọta, JitterBlocker, Knob-on-Display, MarginryLink, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Asambodo akara, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Ike MOS IV, Ike MOS 7, PowerSmart, PureSilicon , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance , Oge ntụkwasị obi, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, na ZENA bụ ụghalaahịa nke Microchip Technology Incorporated na USA na obodo ndị ọzọ.
SQTP bụ akara ọrụ Microchip Technology Incorporated na USA
Akara Adaptec, Frequency on Demand, Silicon Storage Technology, na Symmcom bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Inc. na obodo ndị ọzọ.
GestIC bụ ụghalaahịa edenyere n'akwụkwọ ikikere nke Microchip Technology Germany II GmbH & Co.KG, onye enyemaka Microchip Technology Inc., na mba ndị ọzọ.
ụghalaahịa ndị ọzọ niile a kpọtụrụ aha n'ime ebe a bụ akụ nke ụlọ ọrụ ha.
2024, Microchip Technology Incorporated na ndị enyemaka ya. Ikike niile echekwabara.
ISBN: 978-1-6683-0183-8
Sistemụ Njikwa Ogo
Maka ozi gbasara Sistemụ Njikwa Ogo nke Microchip, biko gaa na www.microchip.com/quality.
Ahịa na Ọrụ zuru ụwa ọnụ

AMERIKA	ASIA/PACIFIC	ASIA/PACIFIC	EUROPE
Ụlọ ọrụ ụlọ ọrụ 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Nkwado ndị teknuzu: www.microchip.com/support Web adreesị: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078	Australia - Sydney Nọmba ekwentị: 61-2-9868-6733 China - Beijing Nọmba ekwentị: 86-10-8569-7000 China - Chengdu Nọmba ekwentị: 86-28-8665-5511 China - Chongqing Nọmba ekwentị: 86-23-8980-9588 China - Dongguan Nọmba ekwentị: 86-769-8702-9880 China - Guangzhou Nọmba ekwentị: 86-20-8755-8029 China - Hangzhou Nọmba ekwentị: 86-571-8792-8115 China - Hong Kong SAR Tel: 852-2943-5100 China - Nanjing Nọmba ekwentị: 86-25-8473-2460 China - Qingdao Nọmba ekwentị: 86-532-8502-7355 China - Shanghai Nọmba ekwentị: 86-21-3326-8000 China - Shenyang Nọmba ekwentị: 86-24-2334-2829 China - Shenzhen Nọmba ekwentị: 86-755-8864-2200 China - Suzhou Nọmba ekwentị: 86-186-6233-1526 China - Wuhan Nọmba ekwentị: 86-27-5980-5300 China - Xian Nọmba ekwentị: 86-29-8833-7252 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040	India - Bangalore Nọmba ekwentị: 91-80-3090-4444 India - New Delhi Nọmba ekwentị: 91-11-4160-8631 India - Pune Nọmba ekwentị: 91-20-4121-0141 Japan - Osaka Nọmba ekwentị: 81-6-6152-7160 Japan - Tokyo Nọmba ekwentị: 81-3-6880-3770 Korea - Daegu Nọmba ekwentị: 82-53-744-4301 Korea - Seoul Nọmba ekwentị: 82-2-554-7200 Malaysia - Kuala Lumpur Nọmba ekwentị: 60-3-7651-7906 Malaysia - Penang Nọmba ekwentị: 60-4-227-8870 Philippines - Manila Nọmba ekwentị: 63-2-634-9065 Singapore Tel: 65-6334-8870 Taiwan - Hsin Chu Nọmba ekwentị: 886-3-577-8366 Taiwan - Kaohsiung Nọmba ekwentị: 886-7-213-7830 Taiwan - Taipei Nọmba ekwentị: 886-2-2508-8600 Thailand - Bangkok Nọmba ekwentị: 66-2-694-1351 Vietnam - Ho Chi Minh Nọmba ekwentị: 84-28-5448-2100	Austria – Wels Nọmba ekwentị: 43-7242-2244-39 Faksị: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4485-5910 Faksị: 45-4485-2829 Finland - Espoo Nọmba ekwentị: 358-9-4520-820 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - na-agba ọsọ Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Nọmba ekwentị: 49-8031-354-560 Israel - Hod Hasharon Nọmba ekwentị: 972-9-775-5100 Ịtali - Milan Tel: 39-0331-742611 Faksị: 39-0331-466781 Ịtali - Padova Tel: 39-049-7625286 Netherlands - mmanya Tel: 31-416-690399 Faksị: 31-416-690340 Norway - Trondheim Nọmba ekwentị: 47-72884388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Nọmba ekwentị: 46-8-5090-4654 UK - Wokingham Nọmba ekwentị: 44-118-921-5800 Faksị: 44-118-921-5820

Akwụkwọ / akụrụngwa

MICROCHIP DS00004807F Omenala Ezinụlọ FPGA PolarFire [pdf] Ntuziaka onye ọrụ DS00004807F PolarFire Ezinụlọ FPGA Omenala Omenala, DS00004807F, Omenala Ezinụlọ FPGA PolarFire, Omenala FPGA Ezinụlọ, Ọsọ Omenala, Ọsọ

Ntụaka

• Akwụkwọ ntuziaka onye ọrụ