PolarFire Mhuri FPGA Tsika Inoyerera Mushandisi Yekushandisa
Libero SoC v2024.2
Nhanganyaya (Bvunza Mubvunzo)
Libero System-on-Chip (SoC) software inopa yakazara yakabatanidzwa Field Programmable Gate Array (FPGA) dhizaini nharaunda. Nekudaro, vashoma vashandisi vangangoda kushandisa yechitatu-bato synthesis uye simulation maturusi kunze kweLibero SoC nharaunda. Libero ikozvino inogona kubatanidzwa mune iyo FPGA dhizaini nharaunda. Zvinokurudzirwa kushandisa Libero SoC kubata iyo yese FPGA dhizaini inoyerera.
Gwaro iri remushandisi rinotsanangura Kuyerera Kwetsika kwePolarFire uye PolarFire SoC Mhuri zvishandiso, maitiro ekubatanidza Libero sechikamu cheiyo yakakura FPGA dhizaini inoyerera. Inotsigirwa Mudziyo Mhuri® Iri tafura rinotevera rinoratidza mhuri dzemidziyo inotsigira Libero SoC. Nekudaro, rumwe ruzivo mugwaro rino rinogona kungoshanda kune imwe mhuri yemidziyo. Muchiitiko ichi, ruzivo rwakadaro runonyatsozivikanwa.
Tafura 1. Mudziyo Mhuri Inotsigirwa neLibero SoC
| Mudziyo Mhuri | Tsanangudzo |
| PolarFire® | PolarFire FPGAs inopa iyo indasitiri simba rakaderera pane yepakati-renji densities ine chengetedzo yakasarudzika uye kuvimbika. |
| PolarFire SoC | PolarFire SoC ndiyo yekutanga SoC FPGA ine deterministic, yakabatana RISC-V CPU cluster, uye inogadzirisa L2 memory subsystem inogonesa Linux® uye chaiyo-nguva maapplication. |
Overview (Bvunza Mubvunzo)
Nepo Libero SoC ichipa yakanyatsobatanidzwa yekupedzisira-kusvika-kumagumo dhizaini dhizaini yekugadzira SoC uye FPGA dhizaini, inopa zvakare shanduko yekumhanyisa synthesis uye simulation neyechitatu-bato maturusi kunze kweLibero SoC nharaunda. Nekudaro, mamwe matanho ekugadzira anofanirwa kuramba ari mukati meLibero SoC nharaunda.
Tafura inotevera inonyora matanho makuru muFPGA dhizaini inoyerera uye inoratidza matanho ayo Libero SoC inofanira kushandiswa.
Tafura 1-1. FPGA Dhizaini Flow
| Dhizaini Inoyerera Danho | Unofanira Kushandisa Libero | Tsanangudzo |
| Dhizaini Kupinda: HDL | Aihwa | Shandisa wechitatu-bato HDL mupepeti/checker chishandiso kunze kweLibero® SoC kana uchida. |
| Dhizaini Kupinda: Configurators | Ehe | Gadzira yekutanga Libero purojekiti yeIP catalog yakakosha chikamu chizvarwa. |
| Otomatiki PDC/SDC inomanikidza chizvarwa | Aihwa | Zvisungo zvakatorwa zvinoda ese HDL files uye derive_constraints utility kana ikaitwa kunze kweLibero SoC, sezvakatsanangurwa muAppendix C-Dhivha Zvipingamupinyi. |
| Simulation | Aihwa | Shandisa chechitatu-bato chishandiso kunze kweLibero SoC, kana uchida. Inoda kudhawunirodherwa kwemaraibhurari ekuenzanisa ekare echishandiso chinonangwa, nhanho yekuenzanisira, uye yakananga Libero vhezheni inoshandiswa kuita backend. |
| Synthesis | Aihwa | Shandisa chechitatu-bato chishandiso kunze kweLibero SoC kana uchida. |
| Dhizaini Yekuita: Tonga Zvipingamupinyi, Nyora Netlist, Nzvimbo-uye-Nzira (ona Pamusoroview) | Ehe | Gadzira yechipiri Libero purojekiti yekudzosera kumashure. |
| Nguva uye Kusimbisa Simba | Ehe | Gara mune yechipiri Libero chirongwa. |
| Gadzirisa Dhizaini Yekutanga Dhata uye Memori | Ehe | Shandisa chishandiso ichi kubata akasiyana marudzi endangariro uye dhizaini yekutanga mumudziyo. Gara muchirongwa chechipiri. |
| Programming File Generation | Ehe | Gara muchirongwa chechipiri. |
Chakakosha: Iwe unofanirwa kudhawunirodha precompiled raibhurari iripo pa PreCompiled Simulation Libraries peji yekushandisa yechitatu-bato simulator.
Mune yakachena Fabric FPGA kuyerera, pinda dhizaini yako uchishandisa HDL kana schematic yekupinda uye pfuura iyo zvakananga
kune synthesis zvishandiso. Kuyerera kuchiri kutsigirwa. PolarFire uye PolarFire SoC FPGAs dzine zvakakosha
proprietary hard IP blocks inoda kushandiswa kweiyo configuration cores (SgCores) kubva kuLibero SoC IP.
catalog. Kubata kwakakosha kunodiwa kune chero zvivharo zvinosanganisira SoC mashandiro:
- PolarFire
– PF_UPROM
– PF_SYSTEM_SERVICES
– PF_CCC
– PF CLK DIV
– PF_CRYPTO
– PF_DRI
– PF_INIT_MONITOR
– PF_NGMUX
– PF_OSC
- RAMs (TPSRAM, DPSRAM, URAM)
– PF_SRAM_AHBL_AXI
– PF_XCVR_ERM
– PF_XCVR_REF_CLK
– PF_TX_PLL
– PF_PCIE
– PF_IO
– PF_IOD_CDR
– PF_IOD_CDR_CCC
– PF_IOD_GENERIC_RX
– PF_IOD_GENERIC_TX
– PF_IOD_GENERIC_TX_CCC
– PF_RGMII_TO_GMII
– PF_IOD_OCTAL_DDR
– PF_DDR3
– PF_DDR4
– PF_LPDDR3
– PF_QDR
– PF_CORESMARTBERT
– PF_TAMPER
– PF_TVS, zvichingodaro.
Pamusoro peiyo yapfuura yakanyorwa SgCores, kune akawanda DirectCore akapfava IPs anowanikwa ePolarFire uye PolarFire SoC mudziyo mhuri muLibero SoC Catalog inoshandisa iyo FPGA machira zviwanikwa.
Pakupinza dhizaini, kana iwe ukashandisa chero chimwe chezvinhu zvakapfuura, unofanirwa kushandisa Libero SoC yechikamu cheiyo dhizaini yekupinda (Component Configuration), asi iwe unogona kuenderera yakasara yako Dhizaini Entry (HDL yekupinda, zvichingodaro) kunze kweLibero. Kugadzirisa iyo FPGA dhizaini inoyerera kunze kweLibero, tevera matanho akapihwa mune yasara gwara.
1.1 Chikamu Chehupenyu Hupenyu (Bvunza Mubvunzo)
Matanho anotevera anotsanangura kutenderera kwehupenyu hweSoC chikamu uye kupa mirairo yemabatiro e data.
- Gadzira chikamu uchishandisa iyo configurator muLibero SoC. Izvi zvinogadzira marudzi anotevera e data:
- HDL files
– Memory files
-Kukurudzira uye Simulation files
- Chikamu cheSDC file - Pamusoro peHDL files, simbisa uye uvasanganise mune yakasara yeHDL dhizaini uchishandisa yekunze dhizaini yekupinda chishandiso / maitiro.
- Supply memory files uye kukurudzira files kune yako yekufananidza chishandiso.
- Supply Component SDC file kuDhivha Constraint chishandiso cheConstraint Generation. Ona Appendix C—Dzina Zvikumbiro kuti uwane mamwe mashoko.
- Iwe unofanirwa kugadzira yechipiri Libero purojekiti, kwaunopinza iyo post-Synthesis netlist uye chikamu chako metadata, nokudaro uchipedzisa hukama pakati pezvawakagadzira uye zvaunoronga.
1.2 Libero SoC Project Kusikwa (Bvunza Mubvunzo)
Mamwe matanho ekugadzira anofanirwa kumhanyiswa mukati meLibero SoC nharaunda (Tafura 1-1). Kuti aya matanho aite, iwe unofanirwa kugadzira maviri Libero SoC mapurojekiti. Yekutanga purojekiti inoshandiswa pakugadzira chikamu chekugadzirisa uye chizvarwa, uye yechipiri chirongwa ndechekuitwa kwemuviri kweiyo yepamusoro-yepamusoro dhizaini.
1.3 Kuyerera Kwetsika (Bvunza Mubvunzo)
Mufananidzo unotevera unoratidza:
- Libero SoC inogona kubatanidzwa sechikamu cheiyo yakakura FPGA dhizaini inoyerera neyechitatu-bato synthesis uye yekunyepedzera maturusi kunze kweLibero SoC nharaunda.
- Matanho akasiyana-siyana anosanganisirwa mukuyerera, kutanga kubva pakugadzira dhizaini uye kusona nzira yese kusvika pakuronga mudziyo.
- Kutsinhana kwedata (zvipimo uye zvinobuda) izvo zvinofanirwa kuitika pane imwe neimwe dhizaini yekuyerera nhanho.
Zano:
- SNVM.cfg, UROMM.cfg
- *.mem file chizvarwa cheSimulation: pa4rtupromgen.exe inotora UPROM.cfg sekuisa uye inoburitsa UPROM.mem.
Aya ndiwo matanho ekuyerera kwetsika:
- Kugadziriswa kwechikamu uye kugadzirwa:
a. Gadzira yekutanga Libero purojekiti (kushanda seReference Project).
b. Sarudza iyo Core kubva kuCatalog. Dzvanya kaviri pakati kuti upe zita rechikamu uye gadzirisa chikamu.
Izvi zvinotumira otomatiki chikamu data uye files. A Component Manifest inogadzirwa zvakare. Ona maComponent Manifest kuti uwane rumwe ruzivo. Kuti uwane rumwe ruzivo, ona Component Configuration. - Pedzisa dhizaini yako yeRTL kunze kweLibero:
a. Isa chikamu HDL files.
b. Nzvimbo yeHDL files yakanyorwa muComponent Manifests files. - Gadzira zvipingaidzo zveSDC zvezvikamu. Shandisa Derive Constraints utility kugadzira iyo nguva yekumanikidza file(SDC) yakavakirwa pa:
a. Chikamu HDL files
b. Chikamu cheSDC files
c. Mushandisi HDL files
Kuti uwane rumwe ruzivo, ona Appendix C—Dhivha Zvinetso. - Synthesis tool/ simulation tool:
a. Tora HDL files, kukurudzira files, uye data yechikamu kubva kunzvimbo chaidzo sezvakanyorwa muComponent Manifests.
b. Synthesize uye tevedzera dhizaini neyechitatu-bato maturusi kunze kweLibero SoC. - Gadzira yako yechipiri (Implementation) Libero Project.
- Bvisa synthesis kubva kudhizaini yekuyerera chishandiso cheni (Projekiti> Zvirongwa zveProjekiti> Dhizaini Inoyerera> bvisa iyo Inogonesa Synthesis cheki bhokisi).
- Ngenisa dhizaini sosi files (post-synthesis *.vm netlist kubva kune synthesis tool):
– Ngenisa post-synthesis *.vm netlist (File> Import> Synthesized Verilog Netlist (VM)).
– Chikamu metadata *.cfg files yePROM uye/kana sNVM. - Ngenisa chero Libero SoC block chikamu files. The block files inofanira kunge iri mu *.cxz file format.
Kuti uwane rumwe ruzivo nezve maitiro ekugadzira block, ona PolarFire Block Flow User Guide. - Pinza kunze kwezvisungo zvekugadzira:
-Kupinza I / O kumanikidza files (Constraints Manager> I/OAttributes> Import).
– Kuunza floorplanning *.pdc files (Constraints Manager> Floor Planner> Import).
– Ngenisa *.sdc nguva inomanikidzirwa files (Constraints Maneja> Nguva> Kupinza). Tumira kunze kweSDC file inogadzirwa kuburikidza neDerive Constraint chishandiso.
– Import * .ndc constraint files (Constraints Manager> NetlistAttributes> Import), kana iripo. - Constraint file uye mubatanidzwa wezvishandiso
– MuConstraint Manager, batanidza ne *.pdc files kuisa uye nzira, iyo *.sdc files kuisa uye nzira uye nguva yekuongorora, uye *.ndc files kuunganidza Netlist. - Kuzadza dhizaini kuita
-Nzvimbo uye nzira, simbisa nguva uye simba, gadzirisa dhizaini yekutanga data uye ndangariro, uye hurongwa file generation. - Simbisa dhizaini
-Simbisa dhizaini paFPGA uye debug sezvinodiwa uchishandisa maturusi ekugadzira akapihwa neLibero SoC dhizaini suite.
Kugadziriswa kwechikamu (Bvunza Mubvunzo)
Nhanho yekutanga mukuyerera kwetsika ndeyekugadzirisa zvikamu zvako uchishandisa Libero referensi purojekiti (inonziwo yekutanga Libero chirongwa muTafura 1-1). Mune matanho anotevera, iwe unoshandisa data kubva kune ino referenzi purojekiti.
Kana iwe uri kushandisa chero zvikamu zvakanyorwa kare, pasi peOverview mukugadzira kwako, ita matanho anotsanangurwa muchikamu chino.
Kana usiri kushandisa chimwe chezvipi zviri pamusoro apa, unogona kunyora RTL yako kunze kweLibero woipinza zvakananga mune yako Synthesis uye Simulation maturusi. Iwe unogona ipapo kuenderera kune post-synthesis chikamu uye chete pinza yako post-synthesis *.vm netlist mune yako yekupedzisira Libero purojekiti (inonziwo yechipiri Libero purojekiti muTafura 1-1).
2.1 Chikamu Kugadzirisa Uchishandisa Libero (Bvunza Mubvunzo)
Mushure mekusarudza izvo zvinofanirwa kushandiswa kubva pane yapfuura runyorwa, ita zvinotevera matanho:
- Gadzira chirongwa chitsva cheLibero (Core Configuration uye Generation): Sarudza Chishandiso uye Mhuri chaunonongedza dhizaini yako yekupedzisira.
- Shandisa imwe kana akawanda emacores akataurwa muCustom Flow.
a. Gadzira SmartDesign uye gadzirisa yaunoda musimboti uye simbisa iyo muSmartDesign chikamu.
b. Kurudzira mapini ese kusvika padanho repamusoro.
c. Gadzira iyo SmartDesign.
d. Dzvanya kaviri iyo Simulate chishandiso (chero chePre-Synthesis kana Post-Synthesis kana Post-Layout sarudzo) kudaidza iyo simulator. Unogona kubuda iyo simulator mushure mekunge yakumbirwa. Danho iri rinogadzira simulation filezvinodikanwa kuprojekiti yako.
Zano: Iwe unofanirwa kuita danho iri kana iwe uchida kutevedzera dhizaini yako kunze kweLibero.
Kuti uwane rumwe ruzivo, ona Simulating Yako Dhizaini.
e. Sevha purojekiti yako-iyi ndiyo purojekiti yako yereferensi.
2.2 ZvinoratidzaBvunza Mubvunzo)
Paunogadzira zvinhu zvako, seti ye files inogadzirwa kune chimwe nechimwe chikamu. Chirevo cheComponent Manifest chinotsanangura seti ye files inogadzirwa uye inoshandiswa mune imwe neimwe nhanho inotevera (Synthesis, Simulation, Firmware Generation, zvichingodaro). Chirevo ichi chinokupa iwe nzvimbo dzezvose zvakagadzirwa fileinodiwa kuti uenderere mberi neCustom Flow. Iwe unogona kuwana chikamu chekuratidzira munzvimbo yeReports: Dzvanya Dhizaini> Mishumo kuvhura iyo Mishumo tebhu. MuReports tab, unoona seti yemanifest.txt files (Kupfuuraview), chimwe chechimwe chikamu chawakagadzira.
Zano: Unofanira kuseta chikamu kana module se'”mudzi”' kuti uone chikamu chinobuda file zviri mukati meReports tab.
Neimwe nzira, iwe unogona kuwana iyo yega manifest report files yechimwe nechimwe chepakati chikamu chinogadzirwa kana SmartDesign chikamu kubva / chikamu/basa/ / / _manifest.txt kana / chikamu/basa/ / _manifest.txt. Iwe unogona zvakare kuwana iyo manifest file zviri mukati mechikamu chega chega chinogadzirwa kubva kune itsva Components tab muLibero, uko iyo file nzvimbo dzinotaurwa maererano nedhairekitori reprojekiti.
Tarisa pane zvinotevera Component Manifest mishumo:
- Kana iwe wakasimbisa macores muSmartDesign, verenga iyo file _manifest.txt.
- Kana iwe wakagadzira zvikamu zvemacores, verenga iyo _manifest.txt.
Iwe unofanirwa kushandisa ese maComponent Manifest mishumo inoshanda kune dhizaini yako. For exampuye, kana purojekiti yako iine SmartDesign ine chimwe kana zvimwe zvakakosha zvikamu zvakasimbiswa mairi uye iwe uchifunga kuishandisa ese mukugadzirwa kwako kwekupedzisira, saka unofanira kusarudza. files yakanyorwa muComponent Manifest mishumo yezvose izvo zvikamu zvekushandisa mukuyerera kwako kwekugadzira.
2.3 Kuturikira Ratidza Files (Bvunza Mubvunzo)
Paunovhura chikamu manifest file, unoona nzira dzekuenda files mune yako Libero purojekiti uye anonongedzera pane pari mudhizaini inoyerera kuti uzvishandise. Unogona kuona anotevera marudzi e files mune manifest file:
- HDL chinyorwa files yezvose Synthesis uye Simulation zvishandiso
- Stimulus files yezvishandiso zvese zvekutevedzera
- Constraint files
Chinotevera ndicho Chikamu Manifest chePolarFire musimboti chikamu.
Imwe neimwe mhando ye file inofanirwa kudzika pasi mukuyerera kwako kwekugadzira. Zvikamu zvinotevera zvinotsanangura kubatanidzwa kwe files kubva kumanifest kusvika padhizaini yako inoyerera.
Constraint Generation (Bvunza Mubvunzo)
Paunenge uchiita zvigadziriso uye chizvarwa, ita shuwa kunyora / kugadzira iyo SDC/PDC/NDC inomanikidza. files kuti dhizaini ivapfuure kuSynthesis, Nzvimbo-uye-Nzira, uye Verify Timing maturusi.
Shandisa iyo Derive Constraints utility kunze kwenzvimbo yeLibero kugadzira zvipingaidzo pane kuzvinyora nemawoko. Kuti ushandise iyo Derive Constraint utility kunze kwenzvimbo yeLibero, unofanirwa:
- Ipa mushandisi HDL, chikamu HDL, uye chikamu cheSDC chinomanikidza files
- Taura iyo yepamusoro level module
- Rondedzera nzvimbo yekugadzira iyo dhizaini yakatorwa files
Iyo SDC chikamu zvipingamupinyi zvinowanikwa pasi / chikamu/basa/ / / dhairekitori mushure mekugadziriswa kwechikamu uye chizvarwa.
Kuti uwane rumwe ruzivo nezve maitiro ekugadzira zvipingaidzo padhizaini yako, ona Appendix C—Derive Constraints.
Synthesizing Dhizaini Yako (Bvunza Mubvunzo)
Chimwe chezvinhu zvekutanga zveCustom Flow ndeyekubvumidza iwe kushandisa yechitatu-bato synthesis
chishandiso kunze kweLibero. Iyo tsika inoyerera inotsigira kushandiswa kweSynopsys SynplifyPro. Kuti synthesize yako
purojekiti, shandisa nzira inotevera:
- Gadzira purojekiti nyowani mune yako Synthesis chishandiso, yakananga kune imwechete mudziyo mhuri, kufa, uye pasuru seLibero chirongwa chawakagadzira.
a. Pinza yako wega RTL files sezvaunowanzoita.
b. Seta Synthesis inobuda kuti ive Structural Verilog (.vm).
Zano: Zvimiro Verilog (.vm) ndiyo yega inotsigirwa fomati yekubuda muPolarFire. - Ngenisa Chikamu HDL files mune yako Synthesis chirongwa:
a. Kune yega yega Component Manifest Report: Yega yega file pasi peHDL sosi files yezvese Synthesis uye Simulation zvishandiso, pinza iyo file mune yako Synthesis Project. - Import the file polarfire_syn_comps.v (kana uchishandisa Synopsys Synplify) kubva
Kuisa nzvimbo>/data/aPA5M kune yako Synthesis purojekiti. - Pinza iyo yakambogadzirwa SDC file kuburikidza neDerived Constraint tool (ona Appendix
A—Sample SDC Constraints) mune Synthesis chishandiso. Kumanikidza uku file inomanikidza chishandiso chekubatanidza kuwana nguva yekuvharwa nekuedza kushoma uye kushoma kwedhizaini.
Zvakakosha:
- Kana ukaronga kushandisa zvakafanana *.sdc file kumanikidza Nzvimbo-ne-Nzira panguva yekugadzira dhizaini chikamu, unofanira kuunza iyi *.sdc muchirongwa chekubatanidza. Izvi ndezvekuona kuti hapana dhizaini yezita risingaenderane mune yakasanganiswa netlist uye Nzvimbo-uye-Nzira zvipingamupinyi panguva yekuita chikamu chekugadzira maitiro. Kana ukasabatanidza iyi *.sdc file mudanho reSynthesis, iyo netlist inogadzirwa kubva kuSynthesis inogona kutadza nhanho yeNzvimbo neNzira nekuda kwedhizaini yezita rechinhu kusaenderana.
a. Ngenisa Netlist Attributes *.ndc, kana iripo, muChishandiso cheSynthesis.
b. Run Synthesis. - Nzvimbo yeSynthesis tool inobuda ine *.vm netlist file yakagadzirwa post Synthesis. Iwe unofanirwa kuendesa iyo netlist muLibero Implementation Project kuti uenderere mberi nemaitiro ekugadzira.
Kutevedzera Dhizaini Yako (Bvunza Mubvunzo)
Kutevedzera dhizaini yako kunze kweLibero (kureva, kushandisa yako wega nharaunda yekunyepedzera uye simulator), ita zvinotevera matanho:
- Design Files:
a. Pre-Synthesis simulation:
• Pinza RTL yako mupurojekiti yako yekufananidza.
• Pachikamu chega chega Manifest Report.
– Ngenisa imwe neimwe file pasi peHDL sosi files yezvose Synthesis uye Simulation maturusi mune yako simulation purojekiti.
• Nyora izvi files sekuenderana nemirairo yako simulator.
b. Post-synthesis simulation:
• Pinza yako post-synthesis * .vm netlist (yakagadzirwa muSynthesizing Yako Dhizaini) mupurojekiti yako yekufananidza uye kuiunganidza.
c. Post-layout simulation:
• Chekutanga, pedzisa kuita dhizaini yako (ona Kushandisa Dhizaini Yako). Ita shuwa kuti yako yekupedzisira Libero purojekiti iri mune post-yakarongedzwa mamiriro.
• Tinya kaviri Gadzira BackAnnotated Files muLibero Dhizaini Flow hwindo. Inogadzira maviri files:
/ mugadziri/ / _ba.v/vhd / mugadziri/
/ _ba.sdf
• Kupinza zvose izvi files muchishandiso chako chekufananidza. - Stimulus uye Configuration files:
a. Kune imwe neimwe Chikamu Manifest Report:
• Kopa zvese files pasi peStimulus Files yezvikamu zvese zveSimulation Tools kune mudzi dhairekitori yeSimulation purojekiti yako.
b. Ita shuwa kuti chero Tcl files mune dzapfuura (mudanho 2.a) dzinoitwa kutanga, kusati kwatanga kutevedzera.
c. UPROM.mem: Kana iwe ukashandisa iyo UPROM musimboti mudhizaini yako nesarudzo Shandisa zvirimo zvekuenzanisa zvinogoneswa kune imwe kana akawanda macustomer ekuchengetedza data aunoda kutevedzera, unofanirwa kushandisa iyo inogoneka pa4rtupromgen (pa4rtupromgen.exe pamahwindo) kugadzira iyo UPROM.mem. file. The pa4rtupromgen executable inotora UPROM.cfg file sekupinza kuburikidza neTcl script file uye inoburitsa iyo UROMM.mem file inodiwa pakuenzanisa. Iyi UROMM.mem file inofanirwa kukopwa kune yekufananidza folda isati yaitwa yekutevedzera. An example kuratidza iyo pa4rtupromgen inoshandiswa kushandiswa inopiwa mumatanho anotevera. The UROM.cfg file inowanikwa mudhairekitori / chikamu/basa/ / muLibero purojekiti yawakashandisa kugadzira iyo UPROM chikamu.
d. snvm.mem: Kana iwe ukashandisa iyo System Services musimboti mudhizaini yako uye nekugadzirisa iyo sNVM tebhu iri pakati neiyo sarudzo Shandisa zvirimo mukuenzanisa zvinogoneswa kune mumwe kana kupfuura mutengi waunoda kutevedzera, snvm.mem. file inogadzirwa otomatiki kuti
dhairekitori / chikamu/basa/ / muLibero purojekiti yawakashandisa kugadzira iyo System Services chikamu. Izvi snvm.mem file inofanirwa kukopwa kune yekufananidza folda isati yaitwa yekutevedzera. - Gadzira dhairekitori rekushanda uye diki-folder rakanzi simulation pasi pefaira rekushanda.
The pa4rtupromgen executable kutarisira kuvapo yokutevedzera sub forodha ari kushanda forodha uye * .tcl script anoiswa mu simulation sub folder. - Kopa iyo UROMM.cfg file kubva kune yekutanga Libero purojekiti yakagadzirirwa chizvarwa chechikamu mune inoshanda folda.
- Namira mirairo inotevera mune * .tcl script woiisa musimulation folda yakagadzirwa mudanho rechitatu.
Sample *.tcl yePolarFire uye PolarFire Soc Mhuri zvishandiso kugadzira URPOM.mem file
kubva kuUPROM.cfg
set_device -fam -fa -pkg
set_input_cfg -path
set_sim_mem -nziraFile/UPROM.mem>
gen_sim -use_init nhema
Kuti uwane zita remukati chairo rekushandisa kufa uye pasuru, ona *.prjx file yekutanga Libero purojekiti (inoshandiswa kugadzirwa kwechikamu).
Iyo nharo use_init inofanira kuiswa kuti nhema.
Shandisa set_sim_mem kuraira kutsanangura nzira yekubuda file UPROM.mem ndizvo
yakagadzirwa pakuitwa kwescript file pamwe pa4rtupromgen rinoitwa. - Pakuraira kukurumidza kana cygwin terminal, enda kune inoshanda dhairekitori yakagadzirwa mudanho 3.
Ita murairo wepa4rtupromgen ne-script sarudzo uye upfuure kwairi *.tcl script yakagadzirwa munhanho yapfuura.
ZveWindows
/designer/bin/pa4rtupromgen.exe \
-script./simulation/ .tcl
Pamusoro peLinux:
/bin/pa4rtupromgen
-script./simulation/ .tcl - Mushure mekubudirira kuurayiwa kwepa4rtupromgen inokwanisika, tarisa kuti UPROM.mem file inogadzirwa munzvimbo yakatsanangurwa set_sim_mem command mune *.tcl script.
- Kutevedzera iyo sNVM, tevedzera iyo snvm.mem file kubva kune yako yekutanga Libero purojekiti (inoshandiswa sechikamu kumisikidzwa) kupinda yepamusoro nhanho simulation folda yeako simulation purojekiti yekumhanyisa simulation (kunze kweLibero SoC). Kuti utevedzere zviri mukati meUPROM, tevedzera yakagadzirwa UROMM.mem file mune yepamusoro nhanho simulation folda yeiyo simulation purojekiti yekumhanyisa simulation (kunze kweLibero SoC).
Zvakakosha: Ku tevedzera mashandiro eSoC Zvikamu, dhawunirodha akatemerwa PolarFire simulation maraibhurari uye pinza iwo munzvimbo yako yekufananidza sezvatsanangurwa pano. Kuti uwane rumwe ruzivo, ona Appendikisi B—Importing Simulation Libraries muSimulation Environment.
Kuita Dhizaini Yako (Bvunza Mubvunzo)
Mushure mekupedza iyo Synthesis uye Post-Synthesis simulation munharaunda yako, unofanirwa kushandisa Libero zvakare kuita dhizaini yako, mhanyisa nguva uye kuongorora simba, uye kugadzira yako hurongwa. file.
- Gadzira nyowani Libero purojekiti yekuita kwemuviri uye marongero edhizaini. Ita shuwa yekunongedza mudziyo mumwechete semureferensi purojekiti yawakagadzira muComponent Configuration.
- Mushure mekugadzirwa kwepurojekiti, bvisa Synthesis kubva kucheni yekushandisa muDhizaini Flow hwindo (Projekiti> Zvirongwa zveProjekiti> Dhizaini Inoyerera> Uncheck Gonesa Synthesis).
- Pinza post-synthesis yako *.vm file muchirongwa ichi, (File > Ngenisa > Synthesized Verilog Netlist (VM)).
Zano: Zvinokurudzirwa kuti ugadzire chinongedzo kune ichi file, kuitira kuti kana iwe ukagadzirisazve dhizaini yako, Libero inogara ichishandisa yazvino post-synthesis netlist.
a. MuDzaini Hierarchy hwindo, cherechedza zita remudzi module.
- Ngenisa zvipingamupinyi muchirongwa cheLibero. Shandisa Constraint Manager kuendesa kunze *.pdc/*.sdc/*.ndc constraints.
a. Pinza I/O *.pdc constraint files (Constraints Manager> I/O Attributes>Import).
b. Import Floorplanning *.pdc constraint files (Constraints Maneja> Floor Planner> Import).
c. Ngenisa *.sdc kuganhurira nguva files (Constraints Maneja> Nguva> Kupinza). Kana dhizaini yako iine chero yemacores akanyorwa muOverview, chengetedza kuunza kunze kweSDC file inogadzirwa kuburikidza nederive constraint tool.
d. Import *.ndc constraint files (Constraints Manager> Netlist Attributes> Import). - Batanidza Zvipingamupinyi Files kugadzira zvishandiso.
a. Vhura Constraint Manager (Manage Constraints> Vhura Manage Contraints View).
Tarisa iyo Nzvimbo-uye-Nzira uye Nguva Yekusimbisa cheki bhokisi riri padivi pekumanikidza file kumisa kumanikidza file uye mubatanidzwa wezvishandiso. Batanidza *.pdc kumanikidzira kuNzvimbo-neNzira uye *.sdc kune zvese Nzvimbo-ne-Nzira uye Nguva Yekuongorora. Batanidza iyo *.ndc file kuunganidza Netlist.
Zano: Kana Nzvimbo neNzira zvinotadza neiyi *.sdc constraint file, wobva waunza zvimwechetezvo *.sdc file kusanganisa uye kuitazve synthesis. - Dzvanya Gadzira Netlist uye wozoisa uye Route kuti upedze danho rekugadzirisa.
- Iyo Configure Dhizaini Initialization Dhata uye Memories chishandiso chinokutendera kuti utange madhizaini ekugadzira, akadai seLSRAM, µSRAM, XCVR (transceivers), uye PCIe uchishandisa data rakachengetwa mune nonvolatile µPROM, sNVM, kana yekunze SPI Flash yekuchengetera ndangariro. Chishandiso chine ma tabo anotevera ekutsanangudza dhizaini yekutanga kutevedzana, iyo yakatarwa yevatengi vekutanga, vatengi data data.
- Dhizaini Initialization tab
- µPROM tab
- sNVM tab
- SPI Flash tab
- Mucheka RAMs tab
Shandisa ma tabo ari muchishandiso kugadzirisa dhizaini yekutanga data uye ndangariro.
Mushure mekupedza kurongeka, ita matanho anotevera kuronga data yekutanga:
• Gadzira vatengi vekutanga
• Gadzira kana kutumira kunze kweiyo bitstream
• Ronga mudziyo
Kuti uwane ruzivo rwakadzama rwekushandisa chishandiso ichi, ona Libero SoC Dhizaini Inoyerera Mushandisi Yekushandisa. Kuti uwane rumwe ruzivo nezve Tcl mirairo inoshandiswa kugadzirisa akasiyana ma tabo muchishandiso uye tsanangura ndangariro kumisikidzwa. files (*.cfg), maona Tcl Commands Reference Guide. - Gadzira purogiramu File kubva purojekiti iyi uye uishandise kuronga FPGA yako.
Mashoko Okuwedzera A—Sample SDC Constraints (Bvunza Mubvunzo
Libero SoC inogadzira SDC nguva yekumanikidza kune mamwe ma IP cores, akadai seCCC, OSC, Transceiver uye zvichingodaro. Kupfuudza zvipingaidzo zveSDC kugadzira maturusi kunowedzera mukana wekusangana nekuvharwa kwenguva nekuedza kushoma uye kushoma kwekugadzira kudzokororwa. Iyo yakazara hierarchical nzira kubva kune yepamusoro-level muenzaniso inopihwa kune ese magadzirirwo zvinhu zvinongedzerwa muzvipingaidzo.
7.1 SDC Kuchengeta Nguva (Bvunza Mubvunzo)
MuLibero IP core reference project, iyi yepamusoro-level SDC constrict file inowanikwa kubva kuConstraint Manager (Design Flow> Vhura Manage Constraint View > Nguva > Tora Zvipingamupinyi).
Chinokosha: Ona izvi file kuseta zvisungo zveSDC kana dhizaini yako iine CCC, OSC, Transceiver, uye zvimwe zvinhu. Gadzirisa iyo yakazara hierarchical nzira, kana zvichidikanwa, kuti ienderane nedhizaini yako yedhizaini kana kushandisa iyo Derive_Constraints utility uye matanho ari muAppendix C-Derive Constraints pachikamu chechikamu SDC. file.
Save the file kune rimwe zita uye unza kunze SDC file kune synthesis chishandiso, Nzvimbo-uye-Nzira Chishandiso, uye Nguva Yekusimbisa, senge chero chimwe chipingamupinyi cheSDC. files.
7.1.1 Derived SDC File (Bvunza Mubvunzo)
#Izvi file yakagadzirwa zvichibva pane inotevera SDC sosi files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
TRANSMIT_PLL/TRANSMIT_PLL_0/TRANSMIT_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PCIE_INITIATOR/PCIE_INITIATOR_0/PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** Chero zvigadziriso kune izvi file icharasika kana zvipingamupinyi zvakatorwa zvikaitwazve. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} -nguva 6.25
[ tora_mapini {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } ] create_clock -name {REF_CLK_PAD_P} -period 10 [ get_ports {REF_CLK_PAD_P } ] create_clock -name {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_is_PLL_PLL
DIV_CLK} -nguva yechisere
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK } ] create_generated_clock -zita {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CCC_CLL_CLL_CLL_0_PF_0
OUT0} -wanza_na 25 -patsanura_na 32 -kunobva
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -chikamu 0
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_0Cll_PF_Cll_0CC_0
OUT1} -wanza_na 25 -patsanura_na 32 -kunobva
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -chikamu 0
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_0Cll_PF_Cll_0CC_0
OUT2} -wanza_na 25 -patsanura_na 32 -kunobva
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -chikamu 0
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CLL_0Cll_PF_Cll_0CC_0
OUT3} -wanza_na 25 -patsanura_na 64 -kunobva
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -chikamu 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3 } ] create_generated_clock -name {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_80MHz/CLK_CD_CD_0
Y_DIV} -divide_by 2 -source
[ kuwana_mapini { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CLK_DIV_0/I_CD/A } ] [ get_pins { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz_DIV_CD_CD_CD_CD_CD_CD set_false_path -through [ get_nets { DMA_INITIATOR_inst_0/ARESETN* } ] set_false_path -from [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray* } ] -ku [ get_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1* } ] set_false_path -from [ get_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray* } ] -ku [ get_cells {DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1* } ] set_false_path -through [ get_nets { FIC0_INITIATOR_inst_0/ARESETN* } ] set_false_path -to [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[0] PCIE/PF_PF_PF_0
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5]
PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/PCIE_1/MPERST_N } ] set_false_path -from [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/TL_CLK } ] set_false_path -through [get_st_TIATOR]
Appendikisi B—Kupinza Maraibhurari Ekutevedzera Munzvimbo Yekutevedzera (Bvunza Mubvunzo)
Iyo yakasarudzika simulator yeRTL simulation neLibero SoC ndiyo ModelSim ME Pro.
Pre-akaunganidzwa maraibhurari eiyo default simulator anowanikwa neLibero kuisirwa pane dhairekitori /Designer/lib/modelsimpro/precompiled/vlog ye® mhuri dzinotsigirwa. Libero SoC inotsigirawo mamwe echitatu-bato simulators editions eModelSim, Questasim, VCS, Xcelium.
, Active HDL, uye Riviera Pro. Dhawunirodha akateedzana pre-akaunganidzwa maraibhurari kubva Libero SoC v12.0 uye gare gare zvichibva pane simulator uye shanduro yayo.
Zvakafanana neLibero nharaunda, run.do file inofanirwa kugadzirwa kuti imhanye simulation kunze kweLibero.
Gadzira iri nyore run.do file iyo ine mirairo yekumisikidza raibhurari yekubatanidza mhedzisiro, mepu yeraibhurari, kuunganidza, uye simulation. Tevedza matanho ekugadzira yakakosha run.do file.
- Gadzira raibhurari ine musoro kuchengeta mibairo yekuunganidza uchishandisa vlib command vlib presynth.
- Mepu iro rine musoro raibhurari zita kune pre-yakaunganidzwa raibhurari dhairekitori uchishandisa vmap command vmap .
- Unganidza source files-shandisa mitauro-yakananga compiler mirairo kuunganidza dhizaini files mukushanda dhairekitori.
– vlog ye .v/.sv
– vcom ye .vhd - Rodha dhizaini yekufananidza uchishandisa vsim kuraira nekutsanangura zita rechero yepamusoro-level module.
- Tevedzera dhizaini uchishandisa run command.
Mushure mekurodha dhizaini, nguva yekufananidza inomisikidzwa kune zero, uye iwe unogona kuisa iyo yekumhanya kuraira kuti utange simulation.
Mune iyo simulator yekunyora hwindo, ita run.do file as run.do run the simulation. Sample run.do file sezvinotevera.
gadzirisa chinyararire ACTELLIBNAME PolarFire chinyararire seta PROJECT_DIR "W:/Test/basic_test" kana
{[file iripo presynth/_info]} {echo “INFO: Simulation raibhurari presynth iripo” } zvimwe
{ file bvisa -force presynth vlib presynth } vmap presynth presynth vmap PolarFire
"X:/Libero/Designer/lib/modelsimpro/precompiled/vlog/PolarFire" vlog -sv -work presynth
“${PROJECT_DIR}/hdl/top.v” vlog “+incdir+${PROJECT_DIR}/stimulus” -sv -work presynth “$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb add wave /tb/*
mhanya 1000ns log /tb/* kubuda
Appendix C—Derive Constraints (Bvunza Mubvunzo)
Apendikisi iyi inotsanangura iyo Derive Constraints Tcl mirairo.
9.1 Tora Zvisungo Tcl Mirairo (Bvunza Mubvunzo)
Iyo derive_constraints utility inokubatsira kuti utore zvipingaidzo kubva kuRTL kana iyo configurator kunze kweLibero SoC dhizaini nharaunda. Kuti ugadzire zvimhingamipinyi zvekugadzira kwako, unoda Mushandisi HDL, Chikamu HDL, uye Component Constraints. files. Iyo SDC chikamu zvinomanikidza files inowanikwa pasi / chikamu/basa/ / / dhairekitori mushure mekugadziriswa kwechikamu uye chizvarwa.
Chimwe nechimwe chikamu chinomanikidza file ine set_component tcl command (inotsanangura zita rechikamu) uye rondedzero yezvipingamupinyi zvinogadzirwa mushure mekugadzirisa. Izvo zvipingamupinyi zvinogadzirwa zvichienderana nekugadzirisa uye zvakananga kune chimwe nechimwe chikamu.
Example 9-1. Component Constraint File yePF_CCC Core
Heino example yechikamu chinomanikidza file yePF_CCC musimboti:
set_component PF_CCC_C0_PF_CCC_C0_0_PF_CCC
# Microchip Corp.
# Date: 2021-Oct-26 04:36:00
# Base wachi yePLL #0
create_clock -period 10 [ get_pins {pll_inst_0/REF_CLK_0 } ] create_generated_clock -divide_by 1 -source [ get_pins {pll_inst_0/
REF_CLK_0 }] -phase 0 [ get_pins {pll_inst_0/OUT0 }] Pano, create_clock and create_generated_clock are reference and output clock constraints respectively, izvo zvinogadzirwa zvichienderana nekugadzirisa.
9.1.1 Kushanda nederive_constraints Utility (Bvunza Mubvunzo)
Tora zvipingamupinyi zvinotenderera kuburikidza nekugadzira uye kugovera zvipingamupinyi zvitsva zvemuenzaniso wega wega wechikamu zvichibva pane yakambopihwa chikamu cheSDC. files. Kune CCC mareferensi wachi, inoparadzira kumashure kuburikidza nedhizaini kuti iwane kwainobva wachi yekurevera. Kana iyo sosi iri I/O, iyo referensi wachi yekumanikidza ichaiswa paI/O. Kana iri CCC inobuda kana imwe wachi sosi (yeexample, Transceiver, oscillator), inoshandisa wachi kubva kune chimwe chikamu uye inoshuma yambiro kana nguva yacho isingaenderane. Derive constraints ichapawo zvipingamupinyi kune mamwe macros senge pa-chip oscillator kana iwe uine iwo muRTL yako.
Kushandisa derive_constraints utility, unofanira kupa .tcl file kuraira-mutsara nharo neruzivo runotevera muhurongwa hwakatsanangurwa.
- Taura ruzivo rwemudziyo uchishandisa ruzivo rwuri muchikamu set_device.
- Rondedzera nzira yekuenda kuRTL files kushandisa ruzivo rwuri muchikamu read_verilog kana read_vhdl.
- Seta yepamusoro level module uchishandisa ruzivo rwuri muchikamu set_top_level.
- Taura nzira yechikamu cheSDC files kushandisa ruzivo rwuri muchikamu read_sdc or read_ndc.
- Execute the files kushandisa ruzivo rwuri muchikamu derive_constraints.
- Rondedzera nzira yeSDC yakatorwa zvipingaidzo file uchishandisa ruzivo rwuri muchikamu nyora_sdc kana nyora_pdc kana nyora_ndc.
Example 9-2. Kuitwa uye Zviri mukati meiyo derive.tcl File
Inotevera ndeye example yekuraira-mutsara nharo yekuita iyo derive_constraints utility.
$ /bin{64}/derive_constraints derive.tcl
Zviri mukati mederive.tcl file:
# Ruzivo rwechishandiso
set_device -family PolarFire -fa MPF100T -speed -1
#RTL files
verenga_verilog -mode system_verilog chirongwa/chikamu/basa/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
read_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
verenga_verilog -mode system_verilog {purojekiti/chikamu/basa/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
read_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd}
#Chikamu SDC files
set_top_level {xcvr1}
verenga_sdc -chikamu {purojekiti/chikamu/basa/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
verenga_sdc -chikamu {purojekiti/chikamu/basa/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
#Shandisa derive_constraint command
derive_constraints
#SDC/PDC/NDC mhedzisiro files
write_sdc {project/constraint/xcvr1_derived_constraints.sdc}
write_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 set_device (Bvunza Mubvunzo)
Tsanangudzo
Taura zita remhuri, zita rekufa, uye giredhi rekumhanya.
set_device -family -fa -speed
Nharo
| Parameter | Type | Tsanangudzo |
| -mhuri | String | Taura zita remhuri. Hunhu hunogona kuitika ndiPolarFire®, PolarFire SoC. |
| -fa | String | Taura zita rekufa. |
| -speed | String | Taura giredhi yekumhanyisa mudziyo. Zvinogoneka kukosha ndeye STD kana -1. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0023 | Inodiwa parameter-kufa hakuna | Iyo yekufa sarudzo inosungirwa uye inofanirwa kutsanangurwa. |
| ERR0005 | Kufa kusingazivikanwe 'MPF30' | Kukosha kwe -die sarudzo haina kururama. Ona zvinogoneka runyorwa rwezvakakosha mune tsananguro yesarudzo. |
| ERR0023 | Parameter-kufa hakuna kukosha | Iyo yekufa sarudzo inotsanangurwa pasina kukosha. |
| ERR0023 | Inodiwa parameter-mhuri haipo | Sarudzo yemhuri inosungirwa uye inofanirwa kutaurwa. |
| ERR0004 | Mhuri isingazivikanwe 'PolarFire®' | Sarudzo yemhuri haina kururama. Ona zvinogoneka runyorwa rwezvakakosha mune tsananguro yesarudzo. |
| ………… akaenderera mberi | ||
| Error Code | Error Message | Tsanangudzo |
| ERR0023 | Parameter- mhuri inoshaya kukosha | Sarudzo yemhuri inotsanangurwa pasina kukosha. |
| ERR0023 | Inodiwa parameter-kumhanya hakuna | Iyo yekumhanyisa sarudzo inosungirwa uye inofanirwa kutaurwa. |
| ERR0007 | Kumhanya kusingazivikanwe ' ' | Iyo yekumhanyisa sarudzo haina kunaka. Ona zvinogoneka runyorwa rwezvakakosha mune tsananguro yesarudzo. |
| ERR0023 | Parameter-kumhanya hakuna kukosha | Iyo yekumhanyisa sarudzo inotsanangurwa pasina kukosha. |
Example
set_device -family {PolarFire} -fa {MPF300T_ES} -speed -1
set_device -family SmartFusion 2 -fa M2S090T -kumhanya -1
9.1.3 verenga_verilog (Bvunza Mubvunzo)
Tsanangudzo
Verenga Verilog file kushandisa Verific.
verenga_verilog [-lib ] [-modhi ]filezita>
Nharo
| Parameter | Type | Tsanangudzo |
| -lib | String | Rondedzera raibhurari ine mamodule achawedzerwa muraibhurari. |
| -modhi | String | Taura iyo Verilog standard. Hunhu hunobvira ndehweverilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. Values inyaya isinganzwisisike. Default ndeye verilog_2k. |
| filezita | String | Verilog file zita. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0023 | Parameter-lib haina kukosha | Iyo lib sarudzo inotsanangurwa pasina kukosha. |
| ERR0023 | Parameter-modhi haina kukosha | Iyo modhi sarudzo inotsanangurwa pasina kukosha. |
| ERR0015 | Isingazivikanwe mode ' ' | Iyo yerilog modhi yakatsanangurwa haizivikanwe. Ona rondedzero yezvinobvira verilog modhi mu-modhi sarudzo tsananguro. |
| ERR0023 | Inodiwa parameter file zita haripo | Hapana verilog file nzira inopihwa. |
| ERR0016 | Zvakundikana nekuda kwemutsananguri weVerific | Syntax kukanganisa mune verilog file. Verific's parser inogona kucherechedzwa mune iyo console pamusoro peiyo meseji yekukanganisa. |
| ERR0012 | set_device haina kudaidzwa | Ruzivo rwemudziyo haruna kutaurwa. Shandisa set_device command kutsanangura mudziyo. |
Example
read_verilog -mode system_verilog {component/work/top/top.v}
read_verilog -mode system_verilog_mfcu design.v
9.1.4 verenga_vhdl (Bvunza Mubvunzo)
Tsanangudzo
Wedzera VHDL file muchirongwa cheVHDL files.
verenga_vhdl [-lib ] [-modhi ]filezita>
Nharo
| Parameter | Type | Tsanangudzo |
| -lib | — | Tsanangura raibhurari umo zvinyorwa zvinofanira kuwedzerwa. |
| -modhi | — | Inotsanangura chiyero cheVHDL. Default ndeye VHDL_93. Zvingangove zvakakosha ndeizvi vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. Values inyaya isinganzwisisike. |
| filezita | — | VHDL file zita. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0023 | Parameter-lib haina kukosha | Iyo lib sarudzo inotsanangurwa pasina kukosha. |
| ERR0023 | Parameter-modhi haina kukosha | Iyo modhi sarudzo inotsanangurwa pasina kukosha. |
| ERR0018 | Isingazivikanwe mode ' ' | Iyo yakatsanangurwa VHDL modhi haizivikanwe. Ona rondedzero yezvinobvira VHDL modhi mu-modhi sarudzo tsananguro. |
| ERR0023 | Inodiwa parameter file zita haripo | Hapana VHDL file nzira inopihwa. |
| ERR0019 | Hatina kukwanisa kunyoresa invalid_path.v file | Iyo VHDL yakatsanangurwa file haipo kana kuti haina mvumo yekuverenga. |
| ERR0012 | set_device haina kudaidzwa | Ruzivo rwemudziyo haruna kutaurwa. Shandisa set_device command kutsanangura mudziyo. |
Example
read_vhdl -mode vhdl_2008 osc2dfn.vhd
read_vhdl {hdl/top.vhd}
9.1.5 set_top_level (Bvunza Mubvunzo)
Tsanangudzo
Taura zita reiyo yepamusoro-level module muRTL.
set_top_level [-lib ]
Nharo
| Parameter | Type | Tsanangudzo |
| -lib | String | Raibhurari yekutsvaga iyo yepamusoro-level module kana entity (Sarudzo). |
| zita | String | Iyo yepamusoro-level module kana zita rechinhu. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0023 | Inodiwa parameter yepamusoro nhanho haipo | Iyo yepamusoro nhanho sarudzo inosungirwa uye inofanirwa kutaurwa. |
| ERR0023 | Parameter-lib haina kukosha | Iyo lib sarudzo inotsanangurwa isina kukosha. |
| ERR0014 | Hatina kuwana danho repamusoro mu library | Iyo yakataurwa pamusoro-yepamusoro module haina kutsanangurwa muraibhurari yakapihwa. Kugadzirisa kukanganisa uku, iyo yepamusoro module kana zita reraibhurari rinofanira kugadziriswa. |
| ERR0017 | Kutsanangura zvakundikana | Kukanganisa muRTL kutsanangura maitiro. Iyo yekukanganisa meseji inogona kucherechedzwa kubva kune iyo console. |
Example
set_top_level {pamusoro}
set_top_level -lib HDl kumusoro
9.1.6 read_sdc (Bvunza Mubvunzo)
Tsanangudzo
Verenga SDC file muchikamu che database.
verenga_sdc -chikamufilezita>
Nharo
| Parameter | Type | Tsanangudzo |
| -chikamu | — | Uyu ndiwo mureza unosungirwa wekuverenga_sdc kuraira kana tawana zvipingaidzo. |
| filezita | String | Nzira yekuenda kuSDC file. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0023 | Inodiwa parameter file zita haripo. | The mandatory sarudzo file zita harina kutaurwa. |
| ERR0000 | SDC file <file_nzira> haiverengeki. | Iyo SDC yakatsanangurwa file haina mvumo yekuverenga. |
| ERR0001 | Tatadza kuvhurafile_nzira> file. | Iye SDC file haapo. Nzira inofanira kugadziriswa. |
| ERR0008 | Isipo set_component command infile_nzira> file | Iyo yakatsanangurwa chikamu cheSDC file haritauri chikamu. |
| Error Code | Error Message | Tsanangudzo |
| ERR0009 | <List of errors from sdc file> | Iye SDC file ine mirairo yesdc isiriyo. For example,
kana paine chikanganiso mu set_multicycle_path constraint: Kanganiso paunenge uchiita command read_sdc: mukatifile_nzira> file: Chikanganiso mukuraira set_multicycle_path: Isingazivikanwe parameter [get_cells {reg_a}]. |
Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 read_ndc (Bvunza Mubvunzo)
Tsanangudzo
Verenga NDC file muchikamu che database.
verenga_ndc -chikamufilezita>
Nharo
| Parameter | Type | Tsanangudzo |
| -chikamu | — | Uyu mureza unosungirwa wekuverenga_ndc kuraira kana tawana zvipingaidzo. |
| filezita | String | Nzira yekuenda kuNDC file. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0001 | Tatadza kuvhurafile_nzira> file | Iye NDC file haapo. Nzira inofanira kugadziriswa. |
| ERR0023 | Inodiwa parameter-AtclParamO_ haipo. | The mandatory sarudzo filezita harina kutaurwa. |
| ERR0023 | Inodiwa parameter-chikamu chisipo. | Component sarudzo inosungirwa uye inofanirwa kutaurwa. |
| ERR0000 | NDC file 'file_path>' haiverengeki. | Iyo NDC yakatsanangurwa file haina mvumo yekuverenga. |
Example
read_ndc -component {chikamu/work/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 deive_constraints (Bvunza Mubvunzo)
Tsanangudzo
Isa chikamu cheSDC files mudhizaini-level database.
derive_constraints
Nharo
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0013 | Yepamusoro-nhanho haina kutsanangurwa | Izvi zvinoreva kuti iyo yepamusoro-level module kana mubatanidzwa haina kutaurwa. Kugadzirisa kufona uku, buritsa iyo set_top_level command pamberi peiyo derive_constraints command. |
Example
derive_constraints
9.1.9 write_sdc (Bvunza Mubvunzo)
Tsanangudzo
Anonyora ganhuriro file muSDC format.
write_sdcfilezita>
Nharo
| Parameter | Type | Tsanangudzo |
| <filezita> | String | Nzira yekuenda kuSDC file ichagadzirwa. Iyi isarudzo inosungirwa. Kana iyo file iripo, ichanyorwa pamusoro. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0003 | Tatadza kuvhurafile nzira> file. | File nzira haisi yechokwadi. Tarisa uone kana madhairekitori evabereki aripo. |
| ERR0002 | SDC file 'file path>' hainyorwi. | Iyo SDC yakatsanangurwa file haana mvumo yekunyora. |
| ERR0023 | Inodiwa parameter file zita haripo. | Iye SDC file nzira isarudzo inosungirwa uye inofanirwa kutsanangurwa. |
Example
write_sdc "derived.sdc"
9.1.10 write_pdc (Bvunza Mubvunzo)
Tsanangudzo
Inonyora zvipingaidzo zvemuviri (Dhivha Zvipingamupinyi chete).
nyora_pdcfilezita>
Nharo
| Parameter | Type | Tsanangudzo |
| <filezita> | String | Nzira yekuenda kuPDC file ichagadzirwa. Iyi isarudzo inosungirwa. Kana iyo file nzira iripo, ichanyorwa. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Messages | Tsanangudzo |
| ERR0003 | Tatadza kuvhurafile nzira> file | The file nzira haisi yechokwadi. Tarisa uone kana madhairekitori evabereki aripo. |
| ERR0002 | PDC file 'file path>' hainyoreki. | Iyo PDC yakatsanangurwa file haana mvumo yekunyora. |
| ERR0023 | Inodiwa parameter file zita haripo | Iye PDC file nzira isarudzo inosungirwa uye inofanirwa kutsanangurwa. |
Example
nyora_pdc "derived.pdc"
9.1.11 write_ndc (Bvunza Mubvunzo)
Tsanangudzo
Inonyora zvisungo zveNDC kuita a file.
write_ndcfilezita>
Nharo
| Parameter | Type | Tsanangudzo |
| filezita | String | Nzira yekuenda kuNDC file ichagadzirwa. Iyi isarudzo inosungirwa. Kana iyo file iripo, ichanyorwa pamusoro. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Messages | Tsanangudzo |
| ERR0003 | Tatadza kuvhurafile_nzira> file. | File nzira haisi yechokwadi. Madhairekitori evabereki haapo. |
| ERR0002 | NDC file 'file_path>' hainyorwi. | Iyo NDC yakatsanangurwa file haana mvumo yekunyora. |
| ERR0023 | Inodiwa parameter _AtclParamO_ haipo. | Iye NDC file nzira isarudzo inosungirwa uye inofanirwa kutsanangurwa. |
Example
write_ndc "derived.ndc"
9.1.12 add_include_path (Bvunza Mubvunzo)
Tsanangudzo
Inotsanangura nzira yekutsvaga inosanganisira files pakuverenga RTL files.
add_include_path
Nharo
| Parameter | Type | Tsanangudzo |
| directory | String | Inotsanangura nzira yekutsvaga inosanganisira files pakuverenga RTL files. Iyi sarudzo inosungirwa. |
| Return Type | Tsanangudzo |
| 0 | Kurayira kwakabudirira. |
| Return Type | Tsanangudzo |
| 1 | Murairo watadza. Pane kukanganisa. Iwe unogona kutarisa meseji yekukanganisa mune iyo console. |
List of Errors
| Error Code | Error Message | Tsanangudzo |
| ERR0023 | Inodiwa parameter inosanganisira nzira isipo. | Sarudzo yedhairekitori inosungirwa uye inofanirwa kupihwa. |
Cherechedza: Kana iyo dhairekitori nzira haina kururama, ipapo add_include_path ichapfuudzwa pasina chikanganiso.
Nekudaro, kuverenga_verilog/read_vhd mirairo ichakundikana nekuda kweVerific's parser.
Example
add_include_path component/work/COREABC0/CORABC0_0/rtl/vlog/core
Revision History (Bvunza Mubvunzo)
Nhoroondo yekudzokorora inotsanangura shanduko dzakaitwa mugwaro. Kuchinja kwacho kunorongwa nekudzokorora, kutanga nebhuku razvino uno.
| Kudzokorora | Date | Tsanangudzo |
| F | 08/2024 | Shanduko dzinotevera dzinoitwa mudzokororo iyi: • Chikamu chakagadziridzwa Appendikisi B—Kupinza Maraibhurari Ekutevedzera Munzvimbo Yekutevedzera. |
| E | 08/2024 | Shanduko dzinotevera dzinoitwa mudzokororo iyi: • Chikamu chakagadziridzwa Overview. • Chikamu chakagadziridzwa Derived SDC File. • Chikamu chakagadziridzwa Appendikisi B—Kupinza Maraibhurari Ekutevedzera Munzvimbo Yekutevedzera. |
| D | 02/2024 | Gwaro iri rinoburitswa neLibero 2024.1 SoC Design Suite pasina shanduko kubva kuv2023.2. Yakagadziridzwa chikamu Kushanda nederive_constraints Utility |
| C | 08/2023 | Gwaro iri rinoburitswa neLibero 2023.2 SoC Design Suite pasina shanduko kubva kuv2023.1. |
| B | 04/2023 | Gwaro iri rinoburitswa neLibero 2023.1 SoC Design Suite pasina shanduko kubva kuv2022.3. |
| A | 12/2022 | Ongororo Yokutanga. |
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RUZIVO IYI INOPIWA NE MICROCHIP "SEZVAZVIRI". MICROCHIP HAIITA ZVINOmiririrwa KANA KUTI MWARATIDZO YERUPI RWERUDZI ZVINO ZVINOTAURWA KANA ZVINOREVA, KUNYORA KANA KUTAURA, ZVINOTAURWA KANA ZVIMWE ZVAKASIYANA, ZVINOENDERA NERUZIVO ZVINO sanganisira ASI ZVISI ZVINOGONA KUTI ZVINOITWA KUTI ZVINOTAURWA, ZVINOTAURWA KUTI ZVIRI MUKATI CHINANGWA CHENYU, KANA KUTI MAWARANTI ZVINOENDERANA NEZVINHU ZVAKAITWA, HUNHU, KANA KUITA. HAPANA CHIITIKO CHICHAITWA MICROCHIP KUNE MHOSVA DZEPI ZVICHAITIKA, CHAKATADZWA, CHECHITSAUKO, ZVINHU, KANA ZVINOTEVERA KURASIKA, KUKATADZWA, MUTENGO, KANA KUTI MUDARIRO WOSE CHECHINHU CHINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINO KANA KUSHANDISWA KWAZVO, ZVICHAITWA ZVINHU ZVINOITWA MAZANO ZVINOGONA KANA KUKABADZA ZVINOFONEKWA. ZVINHU ZVAKAZARA ZVINOTENDERWA NEMUTEMO, MICROCHIP YAKATAURWA YOSE PAZVINOITWA ZVINHU ZVINHU ZVINHU ZVINHU ZVINOITWA NERUZIVO KANA KUSHANDISWA KWAKO HAKUZOPIRI MUNHU WEMURIPO, KANA UCHIDA, WAWAKABHADHARA ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINOITWA NERUZIVO KANA KUSHANDISA KWAKO HAKUZOPIRI MUNHU WEMURIPO, KANA UCHIDA, WAWAKABHADHARA ZVINHU KUTI MICROCHIP.
Kushandiswa kweMicrochip zvishandiso mukutsigira hupenyu uye / kana kuchengetedza zvikumbiro zviri panjodzi yemutengi, uye mutengi anobvuma kudzivirira, kubhadharira uye kubata microchip isingakuvadzi kubva kune chero uye zvese zvinokuvadza, machira, masutu, kana mari inokonzerwa nekushandiswa kwakadaro. Hapana marezinesi anofambiswa, zviri pachena kana neimwe nzira, pasi pekodzero chero ipi zvayo yeMicrochip intellectual property kunze kwekunge zvataurwa neimwe nzira.
Trademarks
Iyo Microchip zita uye logo, iyo Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXTouchlus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, uye XMEGA zviratidzo zvakanyoreswa zveMicrochip Technology Incorporated muUSA nedzimwe nyika.
AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, uye ZL zviratidzo zvakanyoreswa zveMicrochip Technology Incorporated muUSA.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Chero Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEMArage Average, dsPICDEMAverage.net , DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCryLipto, max. maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PowerSmart, , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance , Nguva Yakavimbika, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, uye ZENA zviratidzo zveMicrochip Technology Incorporated muUSA nedzimwe nyika.
SQTP chiratidzo chesevhisi cheMicrochip Technology Incorporated muUSA
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, neSymmcom zviratidzo zvekutengeserana zveMicrochip Technology Inc. kune dzimwe nyika.
GestIC ichiratidzo chekutengeserana chakanyoreswa cheMicrochip Technology Germany II GmbH & Co. KG, inotsigira Microchip Technology Inc., kune dzimwe nyika.
Mamwe matrademark ese ataurwa pano zvinhu zvemakambani avo.
2024, Microchip Technology Incorporated uye masangano ayo. All Rights Reserved.
ISBN: 978-1-6683-0183-8
Quality Management System
Kuti uwane ruzivo nezve Microchip's Quality Management Systems, ndapota shanya www.microchip.com/quality.
Munyika Yose Kutengesa uye Basa
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MICROCHIP DS00004807F PolarFire Mhuri FPGA Tsika Kuyerera [pdf] Bhuku reMushandisi DS00004807F PolarFire Mhuri FPGA Tsika Kuyerera, DS00004807F, PolarFire Mhuri FPGA Tsika Kuyerera, Mhuri FPGA Kuyerera Kwetsika, Kuyerera Kwetsika, Kuyerera |