PolarFire Family FPGA Custom Flow User Guide
Libero SoC v2024.2

Intshayelelo (Buza umbuzo)

I-software ye-Libero System-on-Chip (SoC) ibonelela nge-Field Programmable Gate Array (FPGA) edityanisiweyo ngokupheleleyo. Nangona kunjalo, abasebenzisi abambalwa banokufuna ukusebenzisa i-third party synthesis kunye nezixhobo zokulinganisa ngaphandle kwendawo yeLibero SoC. I-Libero ngoku inokudityaniswa kwindawo yoyilo lweFPGA. Kuyacetyiswa ukuba usebenzise i-Libero SoC ukulawula yonke i-FPGA yoyilo lokuhamba.
Esi sikhokelo somsebenzisi sichaza i-Custom Flow ye-PolarFire kunye ne-PolarFire SoC izixhobo zeNtsapho, inkqubo yokudibanisa i-Libero njengenxalenye ye-FPGA yoyilo lokuhamba okukhulu. Isixhobo esixhaswayo kwiiFamilies® Le theyibhile ilandelayo idwelisa iintsapho zesixhobo ezixhaswa yiLibero SoC. Nangona kunjalo, ezinye iinkcukacha kwesi sikhokelo zinokusebenza kuphela kusapho oluthile lwezixhobo. Kule meko, ulwazi olunjalo luchongiwe ngokucacileyo.
Itheyibhile 1. Iintsapho zeDivaysi ezixhaswa nguLibero SoC

Isixhobo Usapho	Inkcazo
I-PolarFire®	Ii-FPGA zePolarFire zihambisa awona mandla asezantsi kushishino kuluhlu oluphakathi loxinaniso ngokhuseleko olukhethekileyo kunye nokuthembeka.
I-PolarFire SoC	I-PolarFire SoC yeyokuqala ye-SoC FPGA ene-deterministic, ehambelanayo ye-RISC-V CPU cluster, kunye ne-subsystem yememori ye-L2 eyenza i-Linux® kunye nezicelo zexesha langempela.

Ngaphezuluview (Buza umbuzo)

Ngelixa iLibero SoC ibonelela ngobume obudibeneyo bokuphela kokuphela koyilo lokuphuhlisa uyilo lwe-SoC kunye ne-FPGA, ikwabonelela ngokuguquguquka kokuqhuba ukudibanisa kunye nokulinganisa kunye nezixhobo zeqela lesithathu ngaphandle kwendawo yeLibero SoC. Nangona kunjalo, amanye amanyathelo oyilo kufuneka ahlale ngaphakathi kwendawo yeLibero SoC.
Le theyibhile ilandelayo idwelisa amanyathelo amakhulu kwi-FPGA yoyilo lokuhamba kwaye ibonisa amanyathelo ekufuneka i-Libero SoC isetyenziswe kuwo.
Uluhlu 1-1. Ukuhamba koYilo lweFPGA

Inyathelo lokuHamba loYilo	Kufuneka usebenzise iLibero	Inkcazo
Ukungena koYilo: HDL	Hayi	Sebenzisa umhleli/isixhobo sokujonga i-HDL yomntu wesithathu ngaphandle kweLibero® SoC ukuba uyafunwa.
Ukungena koYilo: Abaqwalaseli	Ewe	Yenza iprojekthi yokuqala yeLibero kwikhathalogu yecandelo eliphambili le-IP.
Ukuveliswa kokunyanzeliswa kwePDC/SDC okuzenzekelayo	Hayi	Izithintelo ezifunyenweyo zifuna yonke i-HDL files kunye ne-derive_constraints eluncedo xa isenziwa ngaphandle kwe-Libero SoC, njengoko kuchazwe kwiSihlomelo C-Izithintelo zokuSebenza.
Ukulinganisa	Hayi	Sebenzisa isixhobo somntu wesithathu ngaphandle kweLibero SoC, ukuba uyafunwa. Ifuna ukukhutshelwa kwamathala eencwadi okulinganisa ahlanganiswe kwangaphambili kwisixhobo ekujoliswe kuso, isifanisi ekujoliswe kuso, kunye nenguqulelo yeLibero ekujoliswe kuyo esetyenziselwa ukuphunyezwa komva.
Ukudibanisa	Hayi	Sebenzisa isixhobo somntu wesithathu ngaphandle kweLibero SoC ukuba uyafunwa.
Ukuphunyezwa koYilo: Lawula imiqobo, Qokelela uLuhlu lweNet, iNdawo kunye-neNdlela (jonga ngaphezuluview)	Ewe	Yenza iprojekthi yesibini yeLibero yokuphunyezwa kwe-backend.
Ixesha kunye nokuqinisekiswa kwamandla	Ewe	Hlala kwiprojekthi yesibini yeLibero.
Qwalasela uYilo lweDatha yokuQalisa kunye neenkumbulo	Ewe	Sebenzisa esi sixhobo ukulawula iintlobo ezahlukeneyo zeenkumbulo kunye nokuqaliswa koyilo kwisixhobo. Hlala kwiprojekthi yesibini.
Ukucwangcisa File Isizukulwana	Ewe	Hlala kwiprojekthi yesibini.

Kubalulekile: Wena kufuneka ukhuphele amathala eencwadi asele equlunqwe akhoyo Amathala eencwadi okulinganisa aQotyiweyo iphepha lokusebenzisa isifanisi somntu wesithathu.
Ngokuhamba okucocekileyo kweFabric FPGA, ngenisa uyilo lwakho usebenzisa i-HDL okanye ingeniso yeskimu kwaye uyigqithise ngokuthe ngqo
kwizixhobo zokudibanisa. Ukuhamba kusaxhaswa. I-PolarFire kunye ne-PolarFire SoC FPGA zibalulekile
iibhloko ze-IP ezinzima ezifuna ukusetyenziswa kwee-cores zoqwalaselo (SgCores) ukusuka kwiLibero SoC IP
ikhathalogu. Ukuphathwa okukhethekileyo kuyafuneka kuzo naziphi na iibhloko ezibandakanya ukusebenza kwe-SoC:

• Umlilo wePolar
  – PF_UPROM
  – PF_SYSTEM_SERVICES
  – PF_CCC
  – PF CLK DIV
  – PF_CRIPTO
  – PF_DRI
  – PF_INIT_MONITOR
  – PF_NGMUX
  – PF_OSC
  Ii-RAM (i-TPSRAM, iDPSRAM, iURAM)
  – PF_SRAM_AHBL_AXI
  – PF_XCVR_ERM
  – PF_XCVR_REF_CLK
  – PF_TX_PLL
  – PF_PCIE
  – PF_IO
  – PF_IOD_CDR
  – PF_IOD_CDR_CCC
  – PF_IOD_GENERIC_RX
  – PF_IOD_GENERIC_TX
  – PF_IOD_GENERIC_TX_CCC
  – PF_RGMII_TO_GMII
  – PF_IOD_OCTAL_DDR
  – PF_DDR3
  – PF_DDR4
  – PF_LPDDR3
  – PF_QDR
  – PF_CORESMARTBERT
  – PF_TAMPER
  – PF_TVS, njalo njalo.

Ukongeza kolu luhlu lwangaphambili lwe-SgCores, zininzi ii-IP ezithambileyo ze-DirectCore ezifumanekayo kwi-PolarFire kunye neentsapho zesixhobo se-PolarFire SoC kwikhathalogu ye-Libero SoC ezisebenzisa izibonelelo zelaphu zeFPGA.
Ukungena koyilo, ukuba usebenzisa nayiphi na enye yamacandelo angaphambili, kufuneka usebenzise i-Libero SoC inxalenye yokungeniswa koyilo (Uqwalaselo lweCandelo), kodwa unokuqhubeka lonke uNgeno lwakho loYilo (ukungena kwe-HDL, njalo njalo) ngaphandle kweLibero. Ukulawula ukuhamba koyilo lweFPGA ngaphandle kweLibero, landela amanyathelo anikiweyo kwesi sikhokelo.
1.1 Umjikelo woBomi weCandelo (Buza umbuzo)
La manyathelo alandelayo achaza umjikelo wobomi becandelo le-SoC kwaye anike imiyalelo malunga nendlela yokuphatha idatha.

1. Yenza icandelo usebenzisa isilungisi sayo kwiLibero SoC. Oku kuvelisa ezi ndidi zilandelayo zedatha:
   -HDL files
   – Inkumbulo files
   – Uvuselelo kunye nokulinganisa files
   – Icandelo leSDC file
2. YeHDL files, qinisekisa kwaye udibanise kuyo yonke i-HDL yoyilo usebenzisa isixhobo sokungena koyilo lwangaphandle / inkqubo.
3. Nikeza inkumbulo files kunye novuselelo files kwisixhobo sakho sokulinganisa.
4. ICandelo lonikezelo lweSDC file Ukufumana isixhobo soMnyanzelo kwisiZukulwana sokuQwalasela. Jonga iSihlomelo C—Derive Constrains ngeenkcukacha ezithe vetshe.
5. Kuya kufuneka wenze iprojekthi yesibini yeLibero, apho ungenisa khona i-post-Synthesis netlist kunye nemetadata yecandelo lakho, ngaloo ndlela ugqibezela unxibelelwano phakathi kwento oyenzileyo kunye nento oyiprogramu.

1.2 Ukudalwa kweProjekthi yeLibero SoC (Buza umbuzo)
Amanye amanyathelo oyilo kufuneka aqhutywe ngaphakathi kwendawo ye-Libero SoC (Itheyibhile 1-1). Ukuze la manyathelo aqhube, kufuneka wenze iiprojekthi ezimbini zeLibero SoC. Iprojekthi yokuqala isetyenziselwa ukucwangciswa kwecandelo loyilo kunye nokuveliswa, kwaye iprojekthi yesibini yeyokuphunyezwa ngokomzimba koyilo oluphezulu.
1.3 Ukuqukuqela ngokweSiko (Buza umbuzo)
Lo mfanekiso ulandelayo ubonisa:

• I-Libero SoC inokudityaniswa njengenxalenye ye-FPGA yoyilo olukhulu lokuhamba kunye ne-third party synthesis kunye nezixhobo zokulinganisa ngaphandle kwendawo ye-Libero SoC.
• Amanyathelo ahlukeneyo abandakanyekayo ekuhambeni, ukuqala kwindalo yoyilo kunye nokuthunga yonke indlela yokucwangcisa isixhobo.
• Utshintshiselwano lwedatha (amagalelo kunye neziphumo) ekufuneka zenzeke kwinqanaba ngalinye lokuhamba koyilo.

Ingcebiso:

1. SNVM.cfg, UPROM.cfg
2. *.mem file isizukulwana sokulinganisa: pa4rtupromgen.exe ithatha UPROM.cfg njengegalelo kwaye yenza iUPROM.mem.

Oku kulandelayo ngamanyathelo kuhambo oluqhelekileyo:

1. Ubumbeko lwecandelo kunye nokuveliswa:
   a. Yenza iprojekthi yokuqala yeLibero (ukusebenza njengeProjekthi yeReferensi).
   b. Khetha i-Core kwikhathalogu. Cofa kabini undoqo ukuyinika igama lecandelo kwaye uqwalasele icandelo.
   Oku kuthunyelwa ngaphandle kwedatha yecandelo kunye files. I-Component Manifests nayo iyenziwa. Jonga iiMpawu zeCandelo ngeenkcukacha. Ukufumana iinkcukacha ezithe vetshe, jonga Uqwalaselo lweCandelo.
2. Gqibezela uyilo lwakho lwe-RTL ngaphandle kweLibero:
   a. Qinisekisa icandelo HDL files.
   b. Indawo yeHDL files zidweliswe kwiiMbonakaliso zeCandelo files.
3. Yenza imiqobo ye-SDC yamacandelo. Sebenzisa i-Deriive Constrains usetyenziso ukuvelisa umqobo wexesha file(SDC) isekelwe kwi:
   a. Icandelo le-HDL files
   b. Icandelo leSDC files
   c. Umsebenzisi we-HDL files
   Ukuze ufumane iinkcukacha ezithe vetshe, bona iSihlomelo C—Derive Constraints.
4. Isixhobo sokuhlanganisa/isixhobo sokulinganisa:
   a. Fumana i-HDL files, uvuselelo files, kunye nedatha yecandelo elisuka kwiindawo ezithile njengoko kuphawulwe kwiiMpawu zeCandelo.
   b. Hlanganisa kwaye ulinganise uyilo ngezixhobo zomntu wesithathu ngaphandle kweLibero SoC.
5. Yenza iProjekthi yeLibero yesibini (Ukuphunyezwa).
6. Susa i-synthesis kwikhonkco yesixhobo sokuhamba (Iprojekthi> Useto lweProjekthi> Ukuhamba koYilo> cima i-Yenza i-Synthesis check box).
7. Thatha ngaphandle umthombo woyilo files (post-synthesis *.vm netlist evela kwisixhobo sokuhlanganisa):
   -Ngenisa i-post-synthesis *.vm uluhlu lomnatha (File>Ngenisa ngaphandle> Uluhlu lweNetlist oludityanisiweyo lweVerilog (VM)).
   – Imetadata yecandelo *.cfg files ye-uPROM kunye/okanye i-sNVM.
8. Ngenisa naliphi na icandelo lebhlokhi ye-Libero SoC files. Ibhloko files kufuneka ibekwi *.cxz file ifomathi.
   Ngolwazi oluthe kratya malunga nendlela yokwenza ibhloko, bona Isikhokelo soMsebenzisi wePolarFire Block Flow.
9. Thatha ngaphandle imiqobo yoyilo:
   – Umqobo we-I/O wokuthatha ngaphandle files (Umphathi weMithintelo > I/OAttributes > Ngenisa ngaphandle).
   – Ngenisa iplani yomgangatho *.pdc files (Umphathi weMithintelo> Isicwangcisi soMgangatho> Ngenisa ngaphandle).
   –Ngenisa ngaphandle *.sdc isithintelo sexesha files (Umphathi weZithintelo > Ixesha > Ukungenisa ngaphandle). I-SDC evela ngaphandle file yenziwe ngesixhobo seDerive Constraint.
   –Ngenisa ngaphandle *.ndc isithintelo files (Umphathi weMithintelo> NetlistAttributes > Ngenisa ngaphandle), ukuba ikhona.
10. Ukunyanzelwa file kunye nombutho wezixhobo
    – KuMphathi woMnyanzelo, nxulumanisa *.pdc files kwindawo kunye nendlela, i *.sdc files ukubeka kunye nendlela kunye noqinisekiso lwexesha, kunye ne *.ndc files ukuqulunqa uluhlu lomnatha.
11. Gqibezela ukuphunyezwa koyilo
    -Indawo kunye nendlela, qinisekisa ixesha kunye namandla, cwangcisa idatha yoyilo lokuqalisa kunye neenkumbulo, kunye nenkqubo file isizukulwana.
12. Qinisekisa uyilo
    -Qinisekisa uyilo kwi-FPGA kunye nolungiso njengoko kuyimfuneko usebenzisa izixhobo zoyilo ezibonelelwe nge-suite yokuyila ye-Libero SoC.

Uqwalaselo lwecandelo (Buza umbuzo)

Isinyathelo sokuqala sokuhamba kwesiko kukulungiselela amacandelo akho usebenzisa iprojekthi yereferensi yeLibero (ebizwa ngokuba yiprojekthi yokuqala yeLibero kwiThebhile 1-1). Kumanyathelo alandelayo, usebenzisa idatha evela kule projekthi yereferensi.
Ukuba usebenzisa nawaphi na amacandelo adweliswe ngaphambili, phantsi kwe-Overview kuyilo lwakho, yenza la manyathelo achazwe kweli candelo.
Ukuba awusebenzisi naliphi na kumacandelo angasentla, ungabhala i-RTL yakho ngaphandle kwe-Libero kwaye uyingenise ngokuthe ngqo kwi-Synthesis yakho kunye nezixhobo zokulinganisa. Emva koko ungaqhubela phambili kwicandelo le-post-synthesis kwaye ungenise kuphela i-post-synthesis yakho *.vm netlist kwiprojekthi yakho yokugqibela yokuphunyezwa kweLibero (ekwabizwa ngokuba yiprojekthi yesibini yeLibero kwiThebhile 1-1).
2.1 Ulungelelwaniso lweCandelo usebenzisa iLibero (Buza umbuzo)
Emva kokukhetha amacandelo ekufuneka asetyenziswe kuluhlu olungaphambili, yenza la manyathelo alandelayo:

1. Yenza iprojekthi entsha yeLibero (Uqwalaselo olungundoqo kunye nesiZukulwana): Khetha iSixhobo kunye noSapho ojolise kuyilo lwakho lokugqibela.
2. Sebenzisa enye okanye ngaphezulu kweecores ezikhankanywe kwiCustom Flow.
   a. Yenza i-SmartDesign kwaye uqwalasele ingundoqo oyifunayo kwaye uyifake kwi-SmartDesign component.
   b. Yazisa zonke izikhonkwane kwinqanaba eliphezulu.
   c. Yenza iSmartDesign.
   d. Cofa kabini isixhobo Sokulinganisa (nasiphi na i-Pre-Synthesis okanye i-Post-Synthesis okanye iinketho ze-Post-Layout) ukubiza isifanisi. Ungaphuma kwisifanisi emva kokuba siceliwe. Eli nyathelo livelisa ukulinganisa files iyimfuneko kwiprojekthi yakho.

Luvo: Wena Kufuneka wenze eli nyathelo ukuba ufuna ukulinganisa uyilo lwakho ngaphandle kweLibero.
Ngolwazi oluthe kratya, bona Ukulinganisa Uyilo Lwakho.
e. Gcina iprojekthi yakho-le yiprojekthi yakho yereferensi.
2.2 Iimbonakalo zeCandelo (Buza umbuzo)
Xa usenza amacandelo akho, iseti ye files yenzelwe icandelo ngalinye. Ingxelo yeComponent Manifest inika iinkcukacha ngeseti ye files yenziwe kwaye isetyenziswe kwisinyathelo ngasinye esilandelayo (Ukudibanisa, ukulinganisa, ukuVeliswa kweFirmware, njalo njalo). Le ngxelo ikunika iindawo zazo zonke ezenziweyo files ezifunekayo ukuze kuqhutyekwe nokuHamba okuSiko. Unokufikelela kwi-manifest yecandelo kwindawo yeeNgxelo: Cofa uYilo> Iingxelo ukuvula ithebhu yeeNgxelo. KwiNgxelo thebhu, ubona uluhlu lwe-manifest.txt files (Ngaphezuview), enye yecandelo ngalinye olenzileyo.
Ingcebiso: Kufuneka usete icandelo okanye imodyuli njenge '”root”' ukuze ubone i-manifest yecandelo file imixholo kwiNgxelo thebhu.
Kungenjalo, unokufikelela kwingxelo yomntu ngamnye files yecandelo ngalinye elingundoqo elenziwe okanye icandelo le-SmartDesign ukusuka /icandelo/umsebenzi/ / / _manifest.txt okanye /icandelo/umsebenzi/ / _manifest.txt. Ungafikelela nakwi-manifest file imixholo yecandelo ngalinye eveliswe kwithebhu entsha yaMacandelo eLibero, apho i file iindawo zikhankanyiwe ngokubhekiselele kuluhlu lweprojekthi.Gxininisa kwezi ngxelo zilandelayo zeComponent Manifest:

• Ukuba ufake ii-cores kwi-SmartDesign, funda i file _manifest.txt.
• Ukuba udale amacandelo eecores, funda i _manifest.txt.

Kuya kufuneka usebenzise zonke iingxelo zeeManifest zeComponent ezisebenza kuyilo lwakho. UmzekeloampLe, ukuba iprojekthi yakho ineSmartDesign enento enye okanye ngaphezulu engundoqo efakwe kuyo kwaye ujonge ukuzisebenzisa zonke kuyilo lwakho lokugqibela, kufuneka ukhethe. files zidweliswe kwiingxelo zeCandelo leManifest zawo onke loo malungu ukuze asetyenziswe kuhambo lwakho loyilo.
2.3 Utoliko olubonakalayo Files (Buza umbuzo)
Xa uvula i-manifest yecandelo file, ubona iindlela zokuya files kwiprojekthi yakho yeLibero kunye nezalathisi apho kuyilo lokuhamba ukuzisebenzisa. Unokubona ezi ntlobo zilandelayo ze files kumboniso file:

• Umthombo we-HDL files kuzo zonke izixhobo zokuHlanganisa kunye nokulinganisa
• Uvuselelo files kuzo zonke izixhobo zokulinganisa
• Ukunyanzelwa files

Okulandelayo nguMbonakaliso weCandelo lePolarFire core component.Uhlobo ngalunye lwe file iyimfuneko ezantsi kumjelo woyilo lwakho. La macandelo alandelayo achaza indibaniselwano ye files ukusuka kumboniso ukuya kuyilo lwakho lokuhamba.

Isizukulwana sokunyanzelwa (Buza umbuzo)

Xa usenza uqwalaselo kunye nokuveliswa, qinisekisa ukubhala/ukuvelisa umqobo weSDC/PDC/NDC files kuyilo lokubadlulisela kwi-Synthesis, Indawo-kunye-Umzila, kunye noQinisekisa izixhobo zeXesha.
Sebenzisa i-Derive Constraints utility ngaphandle kwendawo yeLibero ukuvelisa imiqobo endaweni yokuyibhala ngesandla. Ukusebenzisa i-Derive Constraint utility ngaphandle kwendawo yeLibero, kufuneka:

• Ukubonelela ngeHDL yomsebenzisi, icandelo le-HDL, kunye nesithintelo se-SDC secandelo files
• Chaza imodyuli yenqanaba eliphezulu
• Cacisa indawo apho ukuvelisa isithintelo esifunyenweyo files

Izithintelo zecandelo leSDC ziyafumaneka phantsi /icandelo/umsebenzi/ / / ulawulo emva koqwalaselo lwecandelo kunye nokuveliswa.
Ukufumana iinkcukacha ezithe vetshe malunga nendlela yokwenza imithintelo kuyilo lwakho, bona iSihlomelo C—Izithintelo zeDerive.

Ukudibanisa uYilo Lwakho (Buza umbuzo)

Enye yezona zinto ziphambili zokuHamba okuSiko kukuvumela ukuba usebenzise i-synthesis yomntu wesithathu
isixhobo ngaphandle Libero. Umqukuqelo wesiko uxhasa ukusetyenziswa kwe Synopsys SynplifyPro. Ukudibanisa eyakho
iprojekthi, sebenzisa le nkqubo ilandelayo:

1. Yenza iprojekthi entsha kwisixhobo sakho se-Synthesis, ujolise kusapho lwesixhobo esifanayo, kufa, kunye nephakheji njengeprojekthi yeLibero oyenzileyo.
   a. Thatha eyakho i-RTL files njengoko uqhele ukwenza.
   b. Cwangcisa imveliso ye-Snthesis ibeyi-Structural Verilog (.vm).
   Icebiso: Ulwakhiwo I-Verilog (.vm) kuphela kwefomati yemveliso ye-synthesis exhaswayo kwi-PolarFire.
2. Thatha ngaphandle icandelo HDL files kwiprojekthi yakho yoNxibelelwano:
   a. Kwicandelo ngalinye leNgxelo yeZibonakaliso: Kunye file phantsi komthombo we-HDL files kuzo zonke izixhobo zokuHlanganisa kunye nokulinganisa, ngenisa i file kwiProjekthi yakho yeSinthesi.
3. Ngenisa ngaphandle i file polarfire_syn_comps.v (ukuba usebenzisa Synopsys Synplify) ukusuka
   Indawo yokufakela>/idatha/aPA5M kwiprojekthi yakho ye-Synthesis.
4. Thatha ngaphandle iSDC ebiveliswe ngaphambili file ngokusebenzisa iDerived Constraint tool (jonga iSihlomelo
   A—Sample SDC Constraints) kwisixhobo se-Synthesis. Lo mqobo file inyanzelisa isixhobo sokudibanisa ukuphumeza ukuvalwa kwexesha ngomzamo omncinci kunye noyilo oluphindwayo olumbalwa.

Kubalulekile: 

• Ukuba uceba ukusebenzisa enye *.sdc file ukunyanzela iNdawo kunye-neNdlela ngexesha lesigaba sophumezo loyilo, kufuneka ungenise ngaphandle le *.sdc kwiprojekthi yodibaniso. Oku kukuqinisekisa ukuba akukho magama ento yoyilo adityanisiweyo kuluhlu lwenethi oludityanisiweyo kunye nemiqobo yeNdawo kunye neNdlela ngexesha lokuphunyezwa kwenkqubo yoyilo. Ukuba awuyibandakanyi le *.sdc file Kwinyathelo le-Synthesis, uluhlu lomnatha oluveliswe kwi-Synthesis lunokusilela kwiNdawo kunye neNdlela yenyathelo ngenxa yoyilo lwegama lento edityanisiweyo.
  a. Ngenisa iimpawu zoLungelelaniso lweNetlist *.ndc, ukuba zikho, kwisixhobo sokuHlanganisa.
  b. Qhuba i-Synthesis.
• Indawo ekuyo imveliso yesixhobo sakho sokuHlanganisa inoluhlu lwe-*.vm lomnatha file yenziwe isithuba Synthesis. Kufuneka ungenise uluhlu lwe-netlist kwiProjekthi yokuPhunyezwa kweLibero ukuze uqhubeke nenkqubo yoyilo.

Ukulinganisa Uyilo Lwakho (Buza umbuzo)

Ukulinganisa uyilo lwakho ngaphandle kweLibero (oko kukuthi, usebenzisa indawo yakho yokulinganisa kunye nesifanisi), yenza la manyathelo alandelayo:

1. Yila Files:
   a. Ukulinganisa kwangaphambili:
   • Ngenisa i-RTL yakho kwiprojekthi yakho yokulinganisa.
   • KwiNgxelo yeeNkcukacha zeCandelo ngalinye.
   – Ngenisa nganye file phantsi komthombo we-HDL files kuzo zonke izixhobo zokuHlanganisa kunye nokulinganisa kwiprojekthi yakho yokulinganisa.
   • Qokelela ezi files ngokwemiyalelo yesifanisi sakho.
   b. Ukulinganisa emva kokwenziwa:
   •Ngenisa i-post-synthesis yakho *.vm netlist (eveliswe kuNxibelelwano loYilo lwakho) kwiprojekthi yakho yokulinganisa kwaye uyiqulunqe.
   c. Ukulinganisa emva koyilo:
   • Okokuqala, gqibezela uyilo lwakho (jonga ukuphumeza uyilo lwakho). Qinisekisa ukuba iprojekthi yakho yokugqibela yeLibero ikwimo yasemva koyilo.
   • Cofa kabini ukuvelisa iBackAnnotated Files kwiLibero Design Flow window. Ivelisa ezimbini files:
   /umyili/ / _ba.v/vhd /umyili/
   / _ba.sdf
   • Thatha ngaphandle zombini ezi files kwisixhobo sakho sokulinganisa.
2. Uvuselelo kunye noLungiselelo files:
   a. Kwicandelo ngalinye leNgxelo yeZibonakaliso:
   • Khuphela zonke files phantsi kwe-Stimulus Files kuwo onke amacandelo eZixhobo zokulinganisa ukuya kulawulo lweengcambu zeprojekthi yakho yokulinganisa.
   b. Qinisekisa ukuba nayiphi na i-Tcl files kwizintlu ezandulelayo (kwinyathelo lesi-2.a) ziqhutywa kuqala, phambi kokuqala kokulinganisa.
   c. I-UPROM.mem: Ukuba usebenzisa undoqo we-UPROM kuyilo lwakho ngokhetho Sebenzisa umxholo wokulinganisa onikwe amandla kumthengi omnye okanye ngaphezulu wokugcina idatha onqwenela ukulinganisa, kufuneka usebenzise i-pa4rtupromgen ephunyeziweyo (pa4rtupromgen.exe kwiifestile) ukwenza i-UPROM.mem file. I pa4rtupromgen ephunyeziweyo ithatha UPROM.cfg file njengamagalelo nge Tcl script file kwaye ikhupha iUPROM.mem file efunekayo kukulinganisa. Le UPROM.mem file kufuneka ikhutshelwe kwisiqulathi seefayili zokulinganisa phambi kokuba kwenziwe ukulinganisa. Umzekeloample ebonisa pa4rtupromgen usebenziso oluphunyeziweyo inikwe kula manyathelo alandelayo. I-UPROM.cfg file iyafumaneka kulawulo /icandelo/umsebenzi/ / kwiprojekthi yeLibero oyisebenzise ukwenza icandelo leUPROM.
   d. snvm.mem: Ukuba usebenzisa undoqo weeNkonzo zeNkqubo kuyilo lwakho kwaye uqwalasele ithebhu ye-sNVM embindini ngokhetho Sebenzisa umxholo wokulinganisa owenzelwa umxhasi omnye okanye ngaphezulu onqwenela ukulinganisa, i-snvm.mem file yenziwe ngokuzenzekelayo ukuya
   uvimba weefayili /icandelo/umsebenzi/ / kwiprojekthi yeLibero oyisebenzise ukwenza icandelo leeNkonzo zeNkqubo. Le snvm.mem file kufuneka ikhutshelwe kwisiqulathi seefayili zokulinganisa phambi kokuba kwenziwe ukulinganisa.
3. Yenza isiqulathi seefayili esisebenzayo kunye nesiqulathi seefayili esisezantsi esinegama lokulinganisa phantsi kwefolda esebenzayo.
   I-pa4rtupromgen ephunyeziweyo ilindele ubukho bokulinganisa kwifolda esezantsi kwisiqulathi seefayili esisebenzayo kwaye *.tcl iskripthi sibekwe kwifolda esezantsi yokulinganisa.
4. Khuphela i-UPROM.cfg file ukusuka kwiprojekthi yokuqala yeLibero eyenzelwe ukuveliswa kwecandelo kwifolda esebenzayo.
5. Ncamathelisa le miyalelo ilandelayo kwi *.tcl script kwaye uyibeke kwifolda yokulinganisa eyenziwe kwinyathelo lesi-3.
   Sample *.tcl yezixhobo zePolarFire kunye nePolarFire Soc Family ukwenza i-URPOM.mem file
   ukusuka UPROM.cfg
   set_device -fam -fa -pkg
   set_input_cfg -indlela
   set_sim_mem -indlelaFile/UPROM.mem>
   gen_sim -use_init bubuxoki
   Ngegama elililo langaphakathi eliza kusetyenziselwa ukufa kunye nephakheji, bona i *.prjx file yeprojekthi yokuqala yeLibero (esetyenziselwa ukuveliswa kwecandelo).
   Ingxoxo use_init kufuneka imiselwe kubuxoki.
   Sebenzisa i-set_sim_mem umyalelo ukucacisa indlela eya kwimveliso file UPROM.mem leyo
   iveliswe ekuphumezeni iskripthi file nge pa4rtupromgen ephunyeziweyo.
6. Kwi-prompt yomyalelo okanye i-terminal ye-cygwin, yiya kuluhlu olusebenzayo olwenziwe kwinyathelo lesi-3.
   Phumeza umyalelo we-pa4rtupromgen ngokhetho lwe-script kwaye udlulele kuyo *.tcl okushicilelweyo okwenziwe kwinyathelo langaphambili.
   YeeWindows
   /designer/bin/pa4rtupromgen.exe \
   -script./ukulinganisa/ .tcl
   YeLinux:
   /bin/pa4rtupromgen
   -script./ukulinganisa/ .tcl
7. Emva kokuphunyezwa ngempumelelo pa4rtupromgen ephunyeziweyo, khangela ukuba UPROM.mem file uveliswa kwindawo ekhankanyiweyo kwi-set_sim_mem umyalelo kwi *.tcl script.
8. Ukulinganisa i-sNVM, khuphela i-snvm.mem file ukusuka kwiprojekthi yakho yokuqala yeLibero (esetyenziselwa uqwalaselo lwecandelo) kwifolda yokulinganisa inqanaba eliphezulu leprojekthi yakho yokulinganisa ukuqhuba ukulinganisa (ngaphandle kweLibero SoC). Ukulinganisa imixholo ye-UPROM, khuphela i-UPROM.mem eyenziweyo file Kwinqanaba eliphezulu lokulinganisa leprojekthi yakho yokulinganisa ukuze uqhube ukulinganisa (ngaphandle kweLibero SoC).

Kubalulekile: Ukuya Lingisa ukusebenza kwe-SoC Components, khuphela iilayibrari zokulinganisa zePolarFire kwaye uzingenise kwindawo yakho yokulinganisa njengoko kuchaziwe apha. Ukufumana iinkcukacha ezithe vetshe, bona iSihlomelo B—Ukungeniswa kwamaThala eeNcwadi okulinganisa kwiNdawo yokulinganisa.

Ukuphumeza Uyilo Lwakho (Buza umbuzo)

Emva kokugqiba i-Synthesis kunye ne-Post-Synthesis simulation kwindawo yakho, kuya kufuneka usebenzise i-Libero kwakhona ukuphumeza uyilo lwakho, sebenzisa ixesha kunye nohlalutyo lwamandla, kwaye uvelise inkqubo yakho. file.

1. Yenza iprojekthi entsha yeLibero yokuphunyezwa ngokomzimba kunye noyilo loyilo. Qinisekisa ukujolisa isixhobo esifana naso kwiprojekthi yereferensi oyenzileyo kuqwalaselo lweCandelo.
2. Emva kokudalwa kweprojekthi, susa i-Synthesis kwikhonkco lesixhobo kwi-Design Flow window (iProjekthi> Useto lweProjekthi> Ukuhamba koYilo> Sukukhangela i-Synthesis).
3.  Thatha ngaphandle i-post-synthesis yakho *.vm file kule projekthi, (File > Thatha ngaphandle > Uluhlu lweNetlist lweVerilog (VM) oluDityanisiweyo).
   Ingcebiso: Kucetyiswa ukuba wenze ikhonkco kule nto file, ukuze ukuba uphinde udibanise uyilo lwakho, iLibero ihlala isebenzisa i-post-synthesis netlist yamva nje.
   a. Kwifestile yoyilo lweHierarchy, qaphela igama lemodyuli eyingcambu.
4. Ngenisa imiqobo kwiprojekthi yeLibero. Sebenzisa uMphathi woMnyanzelo ukungenisa *.pdc/*.sdc/*.ndc imithintelo.
   a. Thatha ngaphandle I/O *.pdc isithintelo files (Umphathi weMithintelo> Iimpawu ze-I/O > Ukungenisa ngaphandle).
   b. Thatha ngaphandle iFloorplanning *.pdc isithintelo files (Umphathi weMithintelo> Isicwangcisi soMgangatho > Ukungenisa elizweni).
   c. Thatha ngaphandle *.sdc isithintelo sexesha files (Umphathi weZithintelo > Ixesha > Thatha ngaphandle). Ukuba uyilo lwakho lunazo naziphi na iicores ezidweliswe kwi-Overview, qinisekisa ukungenisa iSDC file iveliswe nge-derive contraindication tool.
   d. Ngenisa *.ndc isithintelo files (Umphathi weMithintelo > Iimpawu zeNetlist > Thatha ngaphandle).
5. Nxulumanisa imiqobo Files ukuyila izixhobo.
   a. Vula uMphathi weSinyanzelo (Lawula izithintelo> Vula izithintelo zokulawula View).
   Jonga ibhokisi yeNdawo kunye-neNdlela kunye noQinisekiso lwexesha ecaleni komqobo file ukumisela umqobo file kunye nombutho wezixhobo. Nxulumanisa *.pdc isithintelo kwiNdawo-neNdlela kunye ne *.sdc kuzo zombini iNdawo kunye-neNdlela kunye noQinisekiso lweXesha. Nxulumanisa *.ndc file Ukuqulunqa uluhlu lweNetlist.
   Icebiso: Ukuba Indawo kunye nendlela iyasilela ngalo *.sdc isithintelo file, emva koko thatha ngaphandle kwale nto inye *.sdc file ukudibanisa kunye nokuphinda kuqhutywe udibaniso.
6. Cofa Ukuqokelela Uluhlu lweNet kwaye emva koko Beka kunye Nomzila ukugqiba inyathelo loyilo.
7. Qwalasela uYilo lokuQalisa iDatha kunye nesixhobo seeMemori sikuvumela ukuba uqalise iibhloko zoyilo, ezifana neLSRAM, µSRAM, XCVR (iitransceivers), kunye nePCIe usebenzisa idatha egcinwe kwi-nonvolatile µPROM, sNVM, okanye imemori yangaphandle ye-SPI yokugcina Flash. Isixhobo sineethebhu ezilandelayo zokuchaza ukucaciswa kokulandelelana kokuqalwa koyilo, ukucaciswa kwabathengi bokuqalisa, abathengi bedatha yomsebenzisi.
   -Ithebhu yokuQalisa uyilo
   – µPROM ithebhu
   -ithebhu ye-sNVM
   -SPI Flash tab
   – Ilaphu RAMs ithebhu
   Sebenzisa iithebhu kwisixhobo ukuqwalasela idatha yokuqaliswa koyilo kunye neenkumbulo.Emva kokugqiba ulungelelwaniso, yenza la manyathelo alandelayo ukucwangcisa idatha yokuqalisa:
   • Ukuvelisa abathengi bokuqala
   • Veza okanye uthumele ngaphandle i-bitstream
   • Cwangcisa isixhobo
   Ngolwazi oluneenkcukacha malunga nendlela yokusebenzisa esi sixhobo, jonga iSikhokelo soMsebenzisi weLibero SoC Design Flow. Ngolwazi oluthe kratya kwimiyalelo ye-Tcl esetyenziselwa ukuqwalasela iithebhu ezahlukeneyo kwisixhobo kwaye ukhankanye uqwalaselo lwenkumbulo files (*.cfg), bona Tcl Imiyalelo Reference Guide.
8. Yenza iNkqubo File ukusuka kule projekthi kwaye uyisebenzise ukucwangcisa iFPGA yakho.

Isihlomelo A—Sampimiqobo yeSDC (Buza umbuzo

I-Libero SoC ivelisa izithintelo zexesha le-SDC kwii-cores ezithile ze-IP, ezifana ne-CCC, i-OSC, i-Transceiver njalo njalo. Ukugqithisa imiqobo ye-SDC ukuyila izixhobo kwandisa ithuba lokudibana nokuvalwa kwexesha ngomzamo omncinci kunye noyilo oluphindwayo olumbalwa. Umendo ogcweleyo wehierarchical ukusuka kumzekelo womgangatho ophezulu unikwe zonke izinto zoyilo ezikhankanyiweyo kwimithintelo.
7.1 Izithintelo zeXesha leSDC (Buza umbuzo)
Kwiprojekthi yereferensi ye-IP ye-Libero, lo mqobo we-SDC wezinga eliphezulu file iyafumaneka kuMphathi woMnyanzelo (Uyilo lokuPhuma> Vula uMthinteli woLawulo View > Ixesha > Fumana imiqobo).
Kubalulekile: Yabona oku file ukuseta imiqobo yeSDC ukuba uyilo lwakho luqulathe iCCC, OSC, Transceiver, kunye namanye amacandelo. Guqula umendo opheleleyo woluhlu, ukuba kuyimfuneko, ukutshatisa ubume boyilo lwakho okanye usebenzise iDerive_Constraints into eluncedo kunye namanyathelo akwiSihlomelo C—Fumana imiqobo kwinqanaba lecandelo leSDC. file.
Gcina i file kwigama elahlukileyo kwaye ungenise ngaphandle iSDC file kwisixhobo sokudibanisa, iNdawo-kunye-neSixhobo seNdlela, kunye noQinisekiso lweXesha, njengaso nasiphi na esinye isithintelo seSDC files.
7.1.1 Derived SDC File (Buza umbuzo)
# Oku file yenziwe ngokusekwe kulo mthombo ulandelayo weSDC files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
TRANSMIT_PLL/TRANSMIT_PLL_0/TRANSMIT_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PCIE_INITIATOR/PCIE_INITIATOR_0/PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** Naluphi na utshintsho kule file iyakulahleka ukuba imiqobo efunyenweyo iphinda iqhutywe. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} -ixesha 6.25
[ get_pins { CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } ] create_clock -igama {REF_CLK_PAD_P} -ixesha le-10 [ get_ports { REF_CLK_PAD_P } ] create_clock -igama {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_ist_PLL_
DIV_CLK} -ixesha 8
[ get_pins { CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK } ] create_generated_clock -igama {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CCC_CLK_CLL_CLL_0_CLK_
OUT0} -phinda-phinda_ngama-25 -yahlula-hlula ngama-32 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -isigaba 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0 } ] create_generated_clock -igama {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CC_0_CllPF_CllPF_CLL_0
OUT1} -phinda-phinda_ngama-25 -yahlula-hlula ngama-32 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -isigaba 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1 } ] create_generated_clock -igama {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CC_0_CllPF_CllPF_CLL_0
OUT2} -phinda-phinda_ngama-25 -yahlula-hlula ngama-32 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -isigaba 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2 } ] create_generated_clock -igama {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_CC_0_CllPF_CllPF_CLL_0
OUT3} -phinda-phinda_ngama-25 -yahlula-hlula ngama-64 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -isigaba 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3 } ] create_generated_clock -igama {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_80MHz/CLK_CD_0CD_XNUMX
Y_DIV} -yahlula_nge-2 -umthombo
[ get_pins { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CLK_DIV_0/I_CD/A } ] [ get_pins { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CD_DIV_CD] set_false_path -ngokusebenzisa [ get_nets { DMA_INITIATOR_inst_0/ARESETN* } ] set_false_path -ukusuka [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray* } ] -ukuya [ ukufumana_iiseli { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1* } ] set_false_path -ukusuka [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray* } ] -ukuya [ ukufumana_iiseli { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1* } ] set_false_path -through [ get_nets { FIC0_INITIATOR_inst_0/ARESETN* } ] set_false_path -ukuya [ get_pins {PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[0] PCIE/PCIE/PF_PF_
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/PCIE_1/MPERST_N } ] set_false_path -ukusuka [ get_pins { PCIE/PF_PCIE_C0_0/PCIE_1/TL_CLK } ] set_false_path -through [get_stNTIATOR] Isihlomelo B—Ukungeniswa kwamaThala eeNcwadi okulinganisa kwiNdawo yokulinganisa (Buza umbuzo)
Isifanisi esingagqibekanga sokulinganisa i-RTL kunye neLibero SoC yiModelSim ME Pro.
Amathala eencwadi aqokelelwe kwangaphambili kwisilingisi esingagqibekanga ayafumaneka ngofakelo lweLibero kulawulo /Designer/lib/modelsimpro/precompiled/vlog for® iintsapho ezixhaswayo. ILibero SoC ikwaxhasa ezinye ii-simulators zeqela lesithathu editions zeModelSim, Questasim, VCS, Xcelium
, I-HDL esebenzayo, kunye neRiviera Pro. Khuphela ngokulandelelanayo amathala eencwadi aqokelelwe kwangaphambili Libero SoC v12.0 kwaye kamva ngokusekelwe kwi-simulator kunye nenguqulo yayo.
Ngokufana nokusingqongileyo kweLibero, run.do file kufuneka idalwe ukuqhuba ukulinganisa ngaphandle kweLibero.
Yenza i-run.do elula file enemiyalelo yokuseka ithala leencwadi leziphumo zokuhlanganiswa, imephu yethala leencwadi, ukuhlanganiswa, kunye nokulinganisa. Landela la manyathelo ukwenza i-run.do esisiseko file.

1. Yenza ilayibrari enengqiqo ukugcina iziphumo zokuhlanganiswa usebenzisa i-vlib command vlib presynth.
2. Imephu yegama lethala leencwadi eliqokelelweyo kwithala leencwadi eliqokelelwe kwangaphambili usebenzisa i-vmap yomyalelo we-vmap .
3. Qokelela umthombo files—sebenzisa imiyalelo yomqokeleli yolwimi-lulodwa ukuqulunqa uyilo files kulawulo olusebenzayo.
   – vlog ye.v/.sv
   – vcom ukwenzela .vhd
4. Layisha uyilo lokulinganisa usebenzisa i-vsim umyalelo ngokuchaza igama layo nayiphi na imodyuli yomgangatho ophezulu.
5. Xelisa uyilo usebenzisa sebenzisa umyalelo.
   Emva kokulayisha uyilo, ixesha lokulinganisa limiselwe ku-zero, kwaye ungangenisa umyalelo wokubaleka ukuqalisa ukulinganisa.
   Kwifestile yoshicilelo lokulinganisa, yenza run.do file njengoko run.do sebenzisa ukulinganisa. Sample run.do file ngoku Landelayo.

Cwangcisa ukuseta ACTELLIBNAME PolarFire ngokuzolileyo iseta PROJECT_DIR “W:/Test/basic_test” ukuba
{[file ikhona presynth/_info]} {echo “INFO: Ukulinganisa ilayibrari presynth ikhona” } enye
{ file cima -force presynth vlib presynth } vmap presynth presynth vmap PolarFire
"X:/Libero/Designer/lib/modelsimpro/precompiled/vlog/PolarFire" vlog -sv -work presynth
“${PROJECT_DIR}/hdl/top.v” vlog “+incdir+${PROJECT_DIR}/isivuseleli” -sv -work presynth “$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb yongeza amaza /tb/*
sebenzisa i-1000ns log /tb/* phuma

IsiHlomelo C—Izithintelo zokufumana (Buza umbuzo)

Esi sihlomelo sichaza imiyalelo ye-Derive Constraints Tcl.
9.1 Fumana imiqobo kwiMiyalelo yeTcl (Buza umbuzo)
I-derive_constraints utility ikunceda ukuba ufumane izithintelo kwi-RTL okanye i-configurator ngaphandle kwendawo yoyilo ye-Libero SoC. Ukuvelisa izithintelo kuyilo lwakho, udinga iHDL yoMsebenzisi, icandelo leHDL, kunye neComponent Contraints. files. Imiqobo yecandelo leSDC files ziyafumaneka ngaphantsi /icandelo/umsebenzi/ / / ulawulo emva koqwalaselo lwecandelo kunye nokuveliswa.
Isinyanzelo secandelo ngalinye file iqulathe set_component tcl umyalelo (lichaza igama lecandelo) kunye noluhlu lwezithintelo ezenziwe emva koqwalaselo. Izithintelo ziveliswa ngokusekelwe kuqwalaselo kwaye zithe ngqo kwicandelo ngalinye.
Exampkwi 9-1. Umnyanzelo wecandelo File yePF_CCC Core
Nantsi i-example yesithintelo secandelo file yePF_CCC engundoqo:
set_component PF_CCC_C0_PF_CCC_C0_0_PF_CCC
# IMicrochip Corp.
# Umhla: 2021-Oct-26 04:36:00
# Iwotshi esisiseko yePLL #0
create_clock -ixesha le-10 [ get_pins { pll_inst_0/REF_CLK_0} ] create_generated_clock -dide_by 1 -source [ get_pins {pll_inst_0/
REF_CLK_0 } ] -isigaba 0 [ get_pins { pll_inst_0/OUT0 } ] Apha, create_clock kwaye create_generated_clock zireferensi kunye nemiqobo yewotshi ephumayo ngokulandelelanayo, eveliswa ngokusekwe kuqwalaselo.
9.1.1 Ukusebenza nge-derive_constraints Utility (Buza umbuzo)
Izithintelo zityhutyha kuyilo kunye nokwabiwa kwemithintelo emitsha kumzekelo ngamnye wecandelo ngokusekwe kwicandelo leSDC ebibonelelwe ngaphambili. files. Kwiiwotshi zereferensi yeCCC, isasaza umva ngoyilo lokufumana umthombo wewotshi yereferensi. Ukuba umthombo yi-I/O, umqobo wewotshi yereferensi iya kumiselwa kwi-I/O. Ukuba yimveliso yeCCC okanye omnye umthombo wewotshi (umzekeloample, Transceiver, oscillator), isebenzisa iwotshi ukusuka kwelinye icandelo kwaye ixela isilumkiso ukuba izithuba azihambelani. Izithintelo zokufumana ziyakwabela imiqobo kwezinye iimacros ezinjenge-on-chip oscillators ukuba unazo kwi-RTL yakho.
Ukuphumeza i-derive_constraints into eluncedo, kufuneka unikeze i-.tcl file impikiswano yomgca womyalelo ngolwazi olulandelayo ngokulandelelana okuchaziweyo.

1. Cacisa ulwazi lwesixhobo usebenzisa ulwazi olukwicandelo set_device.
2. Chaza indlela eya kwi-RTL files isebenzisa ulwazi olukwicandelo read_verilog okanye read_vhdl.
3. Seta imodyuli yenqanaba eliphezulu usebenzisa ulwazi olukwicandelo set_top_level.
4. Chaza indlela eya kwicandelo leSDC files usebenzisa ulwazi olukwicandelo read_sdc okanye read_ndc.
5. Yenza i files kusetyenziswa ulwazi olukwicandelo deive_constraints.
6.  Chaza indlela eya kwi-SDC yemiqobo file usebenzisa ulwazi olukwicandelo bhala_sdc okanye bhala_pdc okanye bhala_ndc.

Example 9-2. Ukuphunyezwa kunye neziqulatho ze-derive.tcl File
Oku kulandelayo yi-example mpikiswano yomgca-womyalelo ukuphumeza into eluncedo ye-derive_constraints.
$ /bin{64}/derive_constraints derive.tcl
Imixholo ye-derive.tcl file:
# Ulwazi lwesixhobo
set_device -family PolarFire -die MPF100T -speed -1
#RTL files
read_verilog -mode system_verilog project/component/work/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
read_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
read_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
funda_vhdl -imowudi ye-vhdl_2008 {iprojekthi/hdl/xcvr1.vhd}
#Icandelo leSDC files
set_top_level {xcvr1}
funda_sdc -icandelo {iprojekthi/icandelo/umsebenzi/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
funda_sdc -icandelo {iprojekthi/icandelo/umsebenzi/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
#Sebenzisa i-derive_constraint command
deive_constraints
#SDC/PDC/NDC isiphumo files
write_sdc {project/constraint/xcvr1_derived_constraints.sdc}
write_pdc {iprojekthi/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 seti_isixhobo (Buza umbuzo)
Inkcazo
Chaza igama losapho, igama lokufa, kunye nenqanaba lesantya.
set_device -usapho -fa -isantya
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
-usapho	Umtya	Chaza igama losapho. Amaxabiso anokwenzeka yiPolarFire®, PolarFire SoC.
-fa	Umtya	Chaza igama ledayiti.
-isantya	Umtya	Chaza ibakala lesantya sesixhobo. Amaxabiso anokubakho ngala STD okanye -1.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0023	Iparamitha efunekayo-ukufa akukho	Ukhetho lokufa lunyanzelekile kwaye kufuneka luchazwe.
I-ERR0005	Ukufa okungaziwayo 'MPF30'	Ixabiso lika -die ukhetho alilunganga. Bona uluhlu olunokwenzeka lwamaxabiso kwinkcazo yokhetho.
I-ERR0023	Ipharamitha-ukufa alikho ixabiso	Ukhetho lokufa luchaziwe ngaphandle kwexabiso.
I-ERR0023	Iparamitha efunekayo-usapho lulahlekile	Ukhetho losapho lunyanzelekile kwaye kufuneka lucaciswe.
I-ERR0004	Usapho olungaziwayo 'PolarFire®'	Inketho yosapho ayilunganga. Bona uluhlu olunokwenzeka lwamaxabiso kwinkcazo yokhetho.

………… qhubeka
Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0023	Ipharamitha-usapho lulahlekile	Ukhetho losapho luchaziwe ngaphandle kwexabiso.
I-ERR0023	Ipharamitha efunekayo-isantya silahlekile	Ukhetho lwesantya lunyanzelekile kwaye kufuneka luchazwe.
I-ERR0007	Isantya esingaziwayo ' '	Ukhetho lwesantya alulunganga. Bona uluhlu olunokwenzeka lwamaxabiso kwinkcazo yokhetho.
I-ERR0023	Ipharamitha-isantya asinaxabiso	Ukhetho lwesantya luchaziwe ngaphandle kwexabiso.

Example
set_device -family {PolarFire} -die {MPF300T_ES} -speed -1
set_device -family SmartFusion 2 -die M2S090T -speed -1
9.1.3 funda_iverilog (Buza umbuzo)
Inkcazo
Funda iVerilog file usebenzisa i-Verific.
funda_verilog [-lib ] [-imowudi ]fileigama>
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
-lib	Umtya	Cacisa ithala leencwadi eliqulethe iimodyuli eziza kongezwa kwithala leencwadi.
-imowudi	Umtya	Chaza umgangatho weVerilog. Amaxabiso anokubakho ngala verilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. Ixabiso alinaluvelwano. Ukuhlala kukho verilog_2k.
fileigama	Umtya	Verilog file igama.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0023	IParameter-i-lib ayinaxabiso	I lib ukhetho luxelwe ngaphandle kwexabiso.
I-ERR0023	Ipharamitha-imowudi ayinaxabiso	Indlela yokukhetha ichaziwe ngaphandle kwexabiso.
I-ERR0015	Indlela engaziwayo ' '	Indlela yeverilog echaziweyo ayaziwa. Bona uluhlu olunokwenzeka lwemowudi ye-verilog kwi-indlela yokhetho lwenkcazo.
I-ERR0023	Iparamitha efunekayo file igama alikho	Akukho verilog file umendo unikiwe.
I-ERR0016	Ayiphumelelanga ngenxa yomhlalutyi we-Verific	Imposiso yesivakalisi kwiverilog file. I-Verific's parser inokubonwa kwi-console engentla komyalezo wemposiso.
I-ERR0012	set_device akabizwa	Ulwazi lwesixhobo aluchazwanga. Sebenzisa set_device umyalelo ukuchaza isixhobo.

Example
read_verilog -mode system_verilog {component/work/top/top.v}
read_verilog -mode system_verilog_mfcu design.v
9.1.4 funda_vhdl (Buza umbuzo)
Inkcazo
Yongeza iVHDL file kuluhlu lweVHDL files.
funda_vhdl [-lib ] [-imowudi ]fileigama>
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
-lib	—	Cacisa ithala leencwadi apho umxholo kufuneka wongezwe.
-imowudi	—	Ichaza umgangatho weVHDL. Ukuhlala kukho VHDL_93. Amaxabiso anokubakho ngala vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. Ixabiso alinaluvelwano.
fileigama	—	VHDL file igama.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0023	IParameter-i-lib ayinaxabiso	I lib ukhetho luxelwe ngaphandle kwexabiso.
I-ERR0023	Ipharamitha-imowudi ayinaxabiso	Indlela yokukhetha ichaziwe ngaphandle kwexabiso.
I-ERR0018	Indlela engaziwayo ' '	Indlela ekhankanyiweyo yeVHDL ayaziwa. Bona uluhlu lwendlela yeVHDL enokwenzeka kwi-mode yenkcazo yenketho.
I-ERR0023	Iparamitha efunekayo file igama alikho	Akukho VHDL file umendo unikiwe.
I-ERR0019	Ayikwazanga ukubhalisa invalid_path.v file	I-VHDL echaziweyo file ayikho okanye ayinamvumelwano yokufunda.
I-ERR0012	set_device akabizwa	Ulwazi lwesixhobo aluchazwanga. Sebenzisa set_device umyalelo ukuchaza isixhobo.

Example
read_vhdl -mode vhdl_2008 osc2dfn.vhd
funda_vhdl {hdl/top.vhd}
9.1.5 set_top_level (Buza umbuzo)
Inkcazo
Chaza igama lemodyuli yomgangatho ophezulu kwi-RTL.
set_top_level [-lib ]
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
-lib	Umtya	Ithala leencwadi lokukhangela imodyuli ekwinqanaba eliphezulu okanye iziko (Ngokuzikhethela).
igama	Umtya	Imodyuli yomgangatho ophezulu okanye igama lequmrhu.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0023	Umphakamo ophezulu weparamitha ofunekayo awukho	Inketho yomgangatho ophezulu inyanzelekile kwaye kufuneka icaciswe.
I-ERR0023	IParameter-i-lib ayinaxabiso	I lib ukhetho luxelwe ngaphandle kwamaxabiso.
I-ERR0014	Ayikwazanga ukufumana umgangatho ophezulu kwithala leencwadi	Umnqongo womgangatho ophezulu ochaziweyo awuchazwanga kwithala leencwadi elinikiweyo. Ukulungisa le mpazamo, imodyuli ephezulu okanye igama lethala leencwadi kufuneka lilungiswe.
I-ERR0017	Ukucacisa akuphumelelanga	Imposiso kwinkqubo yokucacisa i-RTL. Umyalezo wemposiso unokubonwa kwi-console.

Example
set_top_level {phezulu}
set_top_level -lib hdl phezulu
9.1.6 funda_sdc (Buza umbuzo)
Inkcazo
Funda iSDC file kwisiseko sedatha yecandelo.
funda_sdc -icandelofileigama>
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
-icandelo	—	Le yiflegi enyanzelekileyo yomyalelo wokufunda_sdc xa sifumana imiqobo.
fileigama	Umtya	Indlela eya kwiSDC file.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0023	Iparamitha efunekayo file igama alikho.	Ukhetho olunyanzelekileyo file igama alichazwanga.
I-ERR0000	I-SDC file <file_indlela> ayifundeki.	I-SDC echaziweyo file ayinamvumelwano yokufunda.
I-ERR0001	Ayikwazi ukuvulafile_indlela> file.	I-SDC file ayikho. Umendo kufuneka ulungiswe.
I-ERR0008	Akukho myalelo wesethi_yecandelo phakathifile_indlela> file	Icandelo elichaziweyo leSDC file ayichazi icandelo.

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0009	<List of errors from sdc file>	I-SDC file iqulethe imiyalelo engachanekanga ye-sdc. Umzekeloample, xa kukho impazamo kwi-set_multicycle_path constraint: Impazamo ngelixa usenza umyalelo read_sdc: kwifile_indlela> file: Imposiso kumyalelo set_multicycle_path: Iparameter engaziwayo [fumana_iiseli {reg_a}].

Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 funda_ndc (Buza umbuzo)
Inkcazo
Funda i-NDC file kwisiseko sedatha yecandelo.
funda_ndc -icandelofileigama>
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
-icandelo	—	Le yiflegi enyanzelekileyo yomyalelo wokufunda_ndc xa sifumana imiqobo.
fileigama	Umtya	Indlela eya kwi-NDC file.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0001	Ayikwazi ukuvulafile_indlela> file	I-NDC file ayikho. Umendo kufuneka ulungiswe.
I-ERR0023	Iparamitha efunekayo—AtclParamO_ ayikho.	Ukhetho olunyanzelekileyo fileigama alichazwanga.
I-ERR0023	Iparamitha efunekayo-icandelo alikho.	Ukhetho lwecandelo lunyanzelekile kwaye kufuneka lucaciswe.
I-ERR0000	NDC file 'file_indlela>' ayifundeki.	I-NDC echaziweyo file ayinamvumelwano yokufunda.

Example
funda_ndc -icandelo {icandelo/umsebenzi/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 i-derive_constraints (Buza umbuzo)
Inkcazo
Qinisekisa icandelo leSDC files kwisiseko sesiseko senqanaba loyilo.
deive_constraints
Iingxoxo

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0013	Inqanaba eliphezulu alichazwanga	Oku kuthetha ukuba imodyuli ekwinqanaba eliphezulu okanye iqumrhu alichazwanga. Ukulungisa le fowuni, khupha i set_top_level umyalelo phambi komyalelo we-derive_constraints.

Example
deive_constraints
9.1.9 bhala_sdc (Buza umbuzo)
Inkcazo
Ubhala isithintelo file ngefomathi yeSDC.
bhala_sdcfileigama>
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
<fileigama>	Umtya	Indlela eya kwiSDC file iya kwenziwa. Olu lukhetho olusisinyanzelo. Ukuba i file ikhona, iya kubhalwa ngaphezulu.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0003	Ayikwazi ukuvulafile indlela> file.	File indlela ayilunganga. Jonga ukuba abalawuli bakhona na.
I-ERR0002	I-SDC file 'file indlela>' ayibhaleki.	I-SDC echaziweyo file ayinayo imvume yokubhala.
I-ERR0023	Iparamitha efunekayo file igama alikho.	I-SDC file umendo lukhetho olusisinyanzelo kwaye kufuneka lucaciswe.

Example
bhala_sdc "derived.sdc"
9.1.10 bhala_pdc (Buza umbuzo)
Inkcazo
Ubhala imiqobo yomzimba (Fumana izithintelo kuphela).
bhala_pdcfileigama>
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
<fileigama>	Umtya	Indlela eya kwiPDC file iya kwenziwa. Olu lukhetho olusisinyanzelo. Ukuba i file indlela ikhona, iya kubhalwa ngaphezulu.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Imiyalezo yemposiso	Inkcazo
I-ERR0003	Ayikwazi ukuvulafile indlela> file	I file indlela ayilunganga. Jonga ukuba abalawuli bakhona na.
I-ERR0002	PDC file 'file indlela>' ayibhaleki.	I-PDC echaziweyo file ayinayo imvume yokubhala.
I-ERR0023	Iparamitha efunekayo file igama alikho	IPDC file umendo lukhetho olusisinyanzelo kwaye kufuneka lucaciswe.

Example
bhala_pdc "derved.pdc"
9.1.11 bhala_ndc (Buza umbuzo)
Inkcazo
Ubhala imiqobo ye-NDC ibe a file.
bhala_ndcfileigama>
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
fileigama	Umtya	Indlela eya kwi-NDC file iya kwenziwa. Olu lukhetho olusisinyanzelo. Ukuba i file ikhona, iya kubhalwa ngaphezulu.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Imiyalezo yemposiso	Inkcazo
I-ERR0003	Ayikwazi ukuvulafile_indlela> file.	File indlela ayilunganga. Uvimba weefayili awukho.
I-ERR0002	NDC file 'file_umendo>' ayibhaleki.	I-NDC echaziweyo file ayinayo imvume yokubhala.
I-ERR0023	Iparamitha efunekayo _AtclParamO_ ayikho.	I-NDC file umendo lukhetho olusisinyanzelo kwaye kufuneka lucaciswe.

Example
write_ndc "derived.ndc"
9.1.12 yongeza_bandakanya_indlela (Buza umbuzo)
Inkcazo
Ixela indlela yokukhangela iquka files xa ufunda i-RTL files.
yongeza_bandakanya_indlela
Iingxoxo

Ipharamitha	Uhlobo	Inkcazo
ulawulo	Umtya	Ixela indlela yokukhangela iquka files xa ufunda i-RTL files. Olu khetho lunyanzelekile.

Uhlobo lokuBuyisa	Inkcazo
0	Umyalelo uphumelele.

Uhlobo lokuBuyisa	Inkcazo
1	Umyalelo awuphumelelanga. Kukho impazamo. Unokujonga umyalezo wemposiso kwi-console.

Uluhlu lweempazamo

Ikhowudi yemposiso	Umyalezo wemposiso	Inkcazo
I-ERR0023	Iparameter efunekayo iquka indlela engekhoyo.	Ukhetho lolawulo lunyanzelekile kwaye kufuneka lubonelelwe.

Qaphela: Ukuba indlela yolawulo ayilunganga, ngoko add_include_path iyakugqithiswa ngaphandle kwempazamo.
Nangona kunjalo, imiyalelo ye-read_verilog/read_vhd iya kusilela ngenxa ye-Verific's parser.
Example
add_include_path component/work/CORABC0/CORABC0_0/rtl/vlog/core

Imbali yohlaziyo (Buza umbuzo)

Imbali yohlaziyo ichaza utshintsho oluthe lwaphunyezwa kuxwebhu. Ezi nguqulelo zidweliswe ngohlaziyo, kuqalwa kolona papasho lwangoku.

Uhlaziyo	Umhla	Inkcazo
F	08/2024	Olu tshintsho lulandelayo lwenziwa kolu hlaziyo: • Icandelo elihlaziyiweyo kwiSihlomelo B—Ukungeniswa kwamaThala eeNcwadi oMfaniso kwiNdawo yokulinganisa.
E	08/2024	Olu tshintsho lulandelayo lwenziwa kolu hlaziyo: • Icandelo elihlaziyiweyo ngaphezuluview. • Icandelo elihlaziyiweyo iDerived SDC File. • Icandelo elihlaziyiweyo kwiSihlomelo B—Ukungeniswa kwamaThala eeNcwadi oMfaniso kwiNdawo yokulinganisa.
D	02/2024	Olu xwebhu lukhutshwe kunye neLibero 2024.1 SoC Design Suite ngaphandle kotshintsho kwi-v2023.2. Icandelo elihlaziyiweyo Ukusebenza ne-derive_constraints Utility
C	08/2023	Olu xwebhu lukhutshwe kunye neLibero 2023.2 SoC Design Suite ngaphandle kotshintsho kwi-v2023.1.
B	04/2023	Olu xwebhu lukhutshwe kunye neLibero 2023.1 SoC Design Suite ngaphandle kotshintsho kwi-v2022.3.
A	12/2022	Uhlaziyo lokuqala.

Microchip FPGA Inkxaso
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Qhagamshelana neZiko leNkxaso yobuGcisa nge webindawo kwi www.microchip.com/support. Khankanya inombolo yeCandelo leSixhobo seFPGA, khetha udidi lwetyala elifanelekileyo, kwaye uyilo lokulayisha files ngelixa usenza imeko yenkxaso yobugcisa.
Qhagamshelana neNkonzo yabaThengi ngenkxaso yemveliso engeyiyo eyobugcisa, njengamaxabiso emveliso, ukuphuculwa kwemveliso, ulwazi lokuhlaziya, isimo somyalelo kunye nokugunyaziswa.

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Ulwazi lweMicrochip
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• Inkxaso yeMveliso - Amaxwebhu eDatha kunye neerrata, amanqaku esicelo kunye ne-sampiinkqubo, izixhobo zoyilo, izikhokelo zabasebenzisi kunye namaxwebhu enkxaso yehardware, ukukhutshwa kwesoftware yamva nje kunye nesoftware egciniweyo
• Inkxaso yezobuGcisa ngokuBanzi-Imibuzo eQhwayo (FAQs), izicelo zenkxaso yobugcisa, amaqela eengxoxo kwi-intanethi, uluhlu lwamalungu enkqubo yoyilo lweMicrochip
• Ishishini leMicrochip - Umkhethi weMveliso kunye nezikhokelo zokuodola, ushicilelo lwamva nje lweMicrochip, uluhlu lweesemina kunye nemisitho, uluhlu lweeofisi zentengiso yeMicrochip, abasasazi kunye nabameli befektri.

Inkonzo yesaziso soTshintsho kwimveliso
Inkonzo yesaziso yokutshintsha imveliso yeMicrochip inceda ukugcina abathengi bangoku kwiimveliso zeMicrochip. Ababhalisi baya kufumana isaziso se-imeyile nanini na kukho utshintsho, uhlaziyo, uhlaziyo okanye iimpazamo ezinxulumene nosapho lwemveliso ethile okanye isixhobo sophuhliso esinomdla. Ukubhalisa, yiya ku www.microchip.com/pcn kwaye ulandele imiyalelo yobhaliso.

Uxhaso lwabathengi
Abasebenzisi beemveliso zeMicrochip banokufumana uncedo ngeendlela ezininzi:

• Umsasazi okanye uMmeli
• I-Ofisi yoThengiso yasekuhlaleni
• Embedded Solutions Engineer (ESE)
• Uxhaso lobuchwepheshe

Abathengi kufuneka baqhagamshelane nomthengisi wabo, ummeli okanye i-ESE ngenkxaso. Iiofisi zeentengiso zasekuhlaleni zikwafumaneka ukunceda abathengi. Uluhlu lweeofisi zokuthengisa kunye neendawo zibandakanyiwe kolu xwebhu. Inkxaso yobugcisa ifumaneka nge webindawo e: www.microchip.com/support
Microchip Devices Code Protection Feature
Qaphela ezi nkcukacha zilandelayo zenqaku lokhuseleko lwekhowudi kwiimveliso zeMicrochip:

• Iimveliso zeMicrochip ziyahlangabezana nemigaqo equlethwe kwiMicrochip Data Sheet yazo.
• IMicrochip ikholelwa ukuba usapho lwayo lweemveliso lukhuselekile xa lusetyenziswa ngendlela ecetywayo, ngokwemigaqo yokusebenza, naphantsi kweemeko eziqhelekileyo.
• Ixabiso leMicrochip kwaye likhusela ngokungqongqo amalungelo epropathi enomgangatho ophezulu wokuqonda. Iinzame zokwaphula ikhowudi yokukhusela iimpawu zeMicrochip zithintelwe ngokungqongqo kwaye zinokwaphula umthetho weDigital Millennium Copyright Act.
• Ayikho i-Microchip okanye nawuphi na umenzi we-semiconductor onokuqinisekisa ukhuseleko lwekhowudi yayo. Ukukhuselwa kwekhowudi akuthethi ukuba siqinisekisa ukuba imveliso "ayinakwaphulwa". Ukhuseleko lwekhowudi luhlala luvela. I-Microchip izinikele ekuphuculeni ngokuqhubekayo iimpawu zokukhusela ikhowudi kwiimveliso zethu.

Isaziso soMthetho
Olu papasho kunye nolwazi olulapha lunokusetyenziswa kuphela ngeemveliso zeMicrochip, kubandakanywa ukuyila, ukuvavanya, kunye nokudibanisa iimveliso zeMicrochip kunye nesicelo sakho. Ukusetyenziswa kolu lwazi ngayo nayiphi na enye indlela kwaphula le migaqo. Ulwazi malunga nosetyenziso lwesixhobo lunikezelwa kuphela ukulungiselela wena kwaye lunokuthi luthathelwe indawo luhlaziyo. Luxanduva lwakho ukuqinisekisa ukuba isicelo sakho siyadibana neenkcukacha zakho. Qhagamshelana neofisi yakho yentengiso yeMicrochip yengingqi ngenkxaso eyongezelelweyo okanye, ufumane inkxaso eyongezelelweyo kwi www.microchip.com/en-us/support/design-help/client-support-services.
OLU LWAZI LUBONWA NGE-MICROCHIP “NJENGOKO ZINJALO”. I-MICROCHIP AYENZA Mmeli OKANYE IZIQINISEKISO ZALO NALUPHI UHLOBO, ENOKUBA ICHAZEKILE OKANYE IYATHENWA, IYABHALWA OKANYE NGOMLOMO, NGOMTHETHO OKANYE NGOLUNYE, ENXULUMENE NOLWAZI KUBANDAKANYA KODWA AYIMDALWA KUSO NAsiphi na isiQinisekiso, isiqinisekiso, isiqinisekiso, isiqinisekiso, okanye isiqinisekiso. INJONGO, OKANYE IZIQINISEKISO INXULUMENE NEMEKO, UMGANGATHO, OKANYE UKUSEBENZA. AKUKHO SIGANEKO IYA KUTHWATHWA NALUPHI NA I-MICROCHIP ESIYA KUTHWALA NGALO NALUPHI NA ULWAZI, OLUKHETHEKILEYO, LWESOHLWAYO, NGESIGANEKO, OKANYE OKUPHUMELELE Ilahleko, UMONAKALO, IINDLEKO, OKANYE INKCITHO YALO NOLUPHI NA UHLOBO ELUYANXULUMENE NOLWAZI OKANYE UKUSETYENZISWA KWALO, NANGONA INGCACISO, NANGENZWENI. OKUSEKO OKANYE UMONAKALO UYABONAKALA. NGOKUPHELELEYO UXANDUVA LUVUMELEKILEYO NGOMTHETHO, UXANDUVA LWONKE LE-MICROCHIP KULONKE AMABANGO NGAYO NAYIPHI NA IINDLELA EZINXULUMENE NOLWAZI OKANYE UKUSETYENZISWA KWALO AKUYI KUGQIBELA ISIXA SOMRHUMO, UKUBA NAKHO, OWUHLAWULE NGQO UKUBA ULWAZI LWAZI.
Ukusetyenziswa kwezixhobo zeMicrochip kwinkxaso yobomi kunye / okanye izicelo zokhuseleko ngokupheleleyo kumngcipheko womthengi, kwaye umthengi uyavuma ukukhusela, ukuhlawula kwaye ubambe iMicrochip engenabungozi kuyo nayiphi na kunye nawo wonke umonakalo, i-laims, iisuti, okanye iindleko ezibangelwa ukusetyenziswa okunjalo. Akukho zilayisenisi zigqithiswayo, ngokungafihlisiyo okanye ngenye indlela, phantsi kwawo nawaphi na amalungelo epropathi yemveliso yeMicrochip ngaphandle kokuba kuchazwe ngenye indlela.
Iimpawu zokuthengisa
Igama leMicrochip kunye nelogo, ilogo yeMicrochip, iAdaptec, iAVR, ilogo yeAVR, iAVR Freaks, iBesTime, iBitCloud, iCryptoMemory, iCryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, kunye neXMEGA ziimpawu zorhwebo ezibhalisiweyo zeMicrochip Technology Incorporated e-USA nakwamanye amazwe.
AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, I-TimeCesium, i-TimeHub, i-TimePictra, i-TimeProvider, kunye ne-ZL ziimpawu zorhwebo ezibhalisiweyo ze-Microchip Technology Incorporated e-USA.
Uxinzelelo oluphambili olusondeleyo, i-AKS, i-Analog-for-the-Digital Age, nayiphi na i-Capacitor, i-AnyIn, i-AnyOut, i-Augmented Switching, i-BlueSky, i-BodyCom, i-Clockstudio, i-CodeGuard, i-CryptoAuthentication, i-CryptoAutomotive, i-CryptoCompanion, i-CryptoController, i-dsPICDEM, i-dsPICDEMEverage, i-DSPICDEMverage. , DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Uqhagamsheleko, JitterBlocker, Knob-on-DinkryLipto, i-MaxCripto-Display, i-Max maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSicon , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance , Ixesha elithenjiweyo, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewI-Span, i-WiperLock, i-XpressConnect, kunye ne-ZENA ziimpawu zorhwebo ze-Microchip Technology Incorporated e-USA nakwamanye amazwe.
I-SQTP luphawu lwenkonzo ye-Microchip Technology Incorporated e-USA
Ilogo ye-Adaptec, Frequency on Demand, Silicon Storage Technology, kunye ne Symmcom ziimpawu zorhwebo ezibhalisiweyo ze Microchip Technology Inc. kwamanye amazwe.
I-GestIC luphawu lwentengiso olubhalisiweyo lwe-Microchip Technology Germany II GmbH & Co. KG, i-subsidiary ye-Microchip Technology Inc., kwamanye amazwe.
Zonke ezinye iimpawu zorhwebo ezikhankanywe apha ziyipropathi yeenkampani zabo.
Ngo-2024, i-Microchip Technology Incorporated kunye ne-subsidiaries yayo. Onke Amalungelo Agciniwe.
ISBN: 978-1-6683-0183-8
Inkqubo yoLawulo loMgangatho
Ngolwazi malunga neMicrochip's Quality Management Systems, nceda undwendwele www.microchip.com/quality.
Intengiso kunye neNkonzo yeHlabathi liphela

AMAMERIKA	I-ASIA/PACIFIC	I-ASIA/PACIFIC	I-YUROYA
IOfisi yoShishino 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Umnxeba: 480-792-7200 Ifeksi: 480-792-7277 Uxhaso lobuchwepheshe: www.microchip.com/support Web Idilesi: www.microchip.com eAtlanta Duluth, GA Umnxeba: 678-957-9614 Ifeksi: 678-957-1455 Austin, TX Umnxeba: 512-257-3370 eBoston Westborough, MA Umnxeba: 774-760-0087 Ifeksi: 774-760-0088 eChicago Itasca, IL Umnxeba: 630-285-0071 Ifeksi: 630-285-0075 eDallas Ukudibanisa, TX Umnxeba: 972-818-7423 Ifeksi: 972-818-2924 eDetroit Novi, MI Umnxeba: 248-848-4000 eHouston, TX Umnxeba: 281-894-5983 Indianapolis Noblesville, IN Umnxeba: 317-773-8323 Ifeksi: 317-773-5453 Umnxeba: 317-536-2380 Ilos angeles UMthunywa Viejo, CA Umnxeba: 949-462-9523 Ifeksi: 949-462-9608 Umnxeba: 951-273-7800 Raleigh, NC Umnxeba: 919-844-7510 ENew York, NY Umnxeba: 631-435-6000 San Jose, CA Umnxeba: 408-735-9110 Umnxeba: 408-436-4270 Canada - Toronto Umnxeba: 905-695-1980 Ifeksi: 905-695-2078	EOstreliya - eSydney Umnxeba: 61-2-9868-6733 China-Beijing Umnxeba: 86-10-8569-7000 China-Chengdu Umnxeba: 86-28-8665-5511 China - Chongqing Umnxeba: 86-23-8980-9588 China-Dongguan Umnxeba: 86-769-8702-9880 China - Guangzhou Umnxeba: 86-20-8755-8029 China-Hangzhou Umnxeba: 86-571-8792-8115 China-Hong Kong SAR Umnxeba: 852-2943-5100 China-Nanjing Umnxeba: 86-25-8473-2460 China - Qingdao Umnxeba: 86-532-8502-7355 China - Shanghai Umnxeba: 86-21-3326-8000 China – Shenyang Umnxeba: 86-24-2334-2829 China-Shenzhen Umnxeba: 86-755-8864-2200 China - Suzhou Umnxeba: 86-186-6233-1526 China - Wuhan Umnxeba: 86-27-5980-5300 China - Xian Umnxeba: 86-29-8833-7252 China - Xiamen Umnxeba: 86-592-2388138 China - Zhuhai Umnxeba: 86-756-3210040	EIndiya-Bangalore Umnxeba: 91-80-3090-4444 EIndiya-eNew Delhi Umnxeba: 91-11-4160-8631 Indiya-IPune Umnxeba: 91-20-4121-0141 Japan - Osaka Umnxeba: 81-6-6152-7160 EJapan - eTokyo Umnxeba: 81-3-6880-3770 Korea - Daegu Umnxeba: 82-53-744-4301 Korea - Seoul Umnxeba: 82-2-554-7200 IMalaysia-Kuala Lumpur Umnxeba: 60-3-7651-7906 EMalaysia - ePenang Umnxeba: 60-4-227-8870 IiPhilippines - eManila Umnxeba: 63-2-634-9065 Singapho Umnxeba: 65-6334-8870 ITaiwan-Hsin Chu Umnxeba: 886-3-577-8366 ITaiwan-Kaohsiung Umnxeba: 886-7-213-7830 ITaiwan-iTaipei Umnxeba: 886-2-2508-8600 EThailand - eBangkok Umnxeba: 66-2-694-1351 IVietnam - iHo Chi Minh Umnxeba: 84-28-5448-2100	EOstriya-Wels Umnxeba: 43-7242-2244-39 Ifeksi: 43-7242-2244-393 EDenmark - eCopenhagen Umnxeba: 45-4485-5910 Ifeksi: 45-4485-2829 EFinland - Espoo Umnxeba: 358-9-4520-820 EFransi - eParis Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 EJamani - Ukutya Umnxeba: 49-8931-9700 EJamani-Haan Umnxeba: 49-2129-3766400 EJamani - Heilbronn Umnxeba: 49-7131-72400 EJamani-Karlsruhe Umnxeba: 49-721-625370 EJamani-Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 EJamani - iRosenheim Umnxeba: 49-8031-354-560 USirayeli - iHod Hasharon Umnxeba: 972-9-775-5100 EItali - eMilan Umnxeba: 39-0331-742611 Ifeksi: 39-0331-466781 EItali - ePadova Umnxeba: 39-049-7625286 ENetherlands – Drunen Umnxeba: 31-416-690399 Ifeksi: 31-416-690340 INorway - iTrondheim Umnxeba: 47-72884388 Poland - Warsaw Umnxeba: 48-22-3325737 I-Romania-Bucharest Tel: 40-21-407-87-50 Spain -Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 eSweden-Gothenberg Tel: 46-31-704-60-40 eSweden-Stockholm Umnxeba: 46-8-5090-4654 E-UK-Wokingham Umnxeba: 44-118-921-5800 Ifeksi: 44-118-921-5820

Amaxwebhu / Izibonelelo

MICROCHIP DS00004807F PolarFire Family FPGA Custom Flow [pdf] Isikhokelo somsebenzisi DS00004807F PolarFire Family FPGA Custom Flow, DS00004807F, PolarFire Family FPGA Custom Stream, Family FPGA Custom Queen, Flow Custom, Flow

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