PolarFire Family FPGA Custom Flow User Guide
Libero SoC v2024.2

Folasaga (Fai se Fesili)

O le polokalame Libero System-on-Chip (SoC) e maua ai se siosiomaga faʻatulagaina atoatoa Field Programmable Gate Array (FPGA). Ae ui i lea, o nai tagata faʻaoga atonu e manaʻo e faʻaoga lona tolu-vaega faʻasologa ma faʻataʻitaʻiga meafaigaluega i fafo atu o le siosiomaga Libero SoC. Libero e mafai nei ona tuʻufaʻatasia i totonu o le siosiomaga mamanu FPGA. E fautuaina e faʻaaoga le Libero SoC e faʻatautaia ai le faʻasologa atoa o le mamanu FPGA.
O loʻo faʻamatalaina e lenei taʻiala faʻaoga le Faʻasologa Faʻapitoa mo PolarFire ma PolarFire SoC Family device, o se faʻagasologa e tuʻufaʻatasia ai le Libero e avea o se vaega o le tele o le FPGA design flow. Supported Device Families® O le laulau o loʻo i lalo o loʻo lisiina ai aiga masini e lagolagoina e Libero SoC. Ae ui i lea, o nisi faʻamatalaga i lenei taʻiala atonu e faʻaoga i se aiga patino o masini. I lenei tulaga, o ia faʻamatalaga e manino le iloa.
Fuafuaga 1. Aiga o masini e lagolagoina e Libero SoC

Aiga masini	Fa'amatalaga
PolarFire®	PolarFire FPGAs e tu'uina atu le malosi aupito maualalo o le alamanuia i le vaeluagalemu densities ma tulaga ese le saogalemu ma le fa'atuatuaina.
PolarFire SoC	PolarFire SoC o le SoC FPGA muamua fa'atasi ai ma se fa'amautu, fa'amautu RISC-V CPU fa'aputu, ma se fa'atonuga L2 manatua subsystem e mafai ai Linux® ma taimi-taimi talosaga.

Ua umaview (Fai se Fesili)

Aʻo tuʻuina atu e Libero SoC se siosiomaga faʻataʻitaʻiga tuʻufaʻatasia tuʻufaʻatasia e atiaʻe ai SoC ma FPGA mamanu, e maua ai foʻi le fetuutuunaʻi e faʻatautaia le faʻasologa ma le faʻataʻitaʻiga ma meafaigaluega lona tolu i fafo atu o le siosiomaga Libero SoC. Ae ui i lea, o nisi laasaga mamanu e tatau ona tumau i totonu ole siosiomaga Libero SoC.
O le laulau o loʻo i lalo o loʻo lisiina ai laasaga tetele i le FPGA design flow ma faʻaalia ai laasaga e tatau ona faʻaogaina ai le Libero SoC.
Laulau 1-1. FPGA Fuafuaga tafe

Laasaga Fuafuaga	E tatau ona faʻaaoga Libero	Fa'amatalaga
Fuafuaga Ulufale: HDL	Leai	Fa'aoga le fa'atonu HDL/mea faigaluega siaki i fafo atu o Libero® SoC pe a mana'omia.
Fa'ailoga Tusia: Configurators	Ioe	Fausia muamua le poloketi Libero mo le fa'asologaina o vaega autu o le IP catalog.
Otometi PDC/SDC fa'atupu fa'alavelave	Leai	O fa'agata fa'atupu e mana'omia uma HDL files ma se aoga derive_constraints pe a faatino i fafo atu o le Libero SoC, e pei ona faamatalaina i le Fa'aopoopo C—Auina Fa'agata.
Fa'ata'oto	Leai	Fa'aoga meafaigaluega lona tolu i fafo atu o Libero SoC, pe a mana'omia. Manaomia le la'uina mai o faletusi fa'ata'ita'i ua uma ona tu'ufa'atasia mo masini fa'atatau, simulator fa'atatau, ma le fa'atatau Libero fa'aoga mo le fa'atinoga pito i tua.
Fa'asologa	Leai	Fa'aoga meafaigaluega lona tolu i fafo atu o Libero SoC pe a mana'omia.
Fuafuaga Fa'atinoga: Puleaina Fa'agata, Fa'aputuga Netlist, Nofoaga-ma- Auala (silasila i lugaview)	Ioe	Fausia se poloketi Libero lona lua mo le faʻatinoga o tua.
Taimi ma le Pule Fa'amaonia	Ioe	Nofo i le poloketi lona lua Libero.
Fa'atulaga Fuafuaga Initialization Faamatalaga ma Faamanatuga	Ioe	Fa'aoga lenei mea faigaluega e pulea ai ituaiga eseese o manatuaga ma mamanu amata ile masini. Tumau i le poloketi lona lua.
Polokalama File Tupulaga	Ioe	Tumau i le poloketi lona lua.

Taua: O oe e tatau ona la'u mai faletusi ua uma ona tu'ufa'atasia e maua i le PreCompiled Simulation Libraries itulau e fa'aoga ai se simulator isi vaega.
I totonu ole Fabric FPGA tafe mama, ulufale i lau mamanu e faʻaaoga ai le HDL poʻo le faʻailoga faʻailoga ma pasi saʻo
i meafaigaluega fa'apipi'i. O lo'o lagolagoina pea le tafe. PolarFire ma PolarFire SoC FPGAs e taua tele
poloka IP malosi fa'apitoa e mana'omia le fa'aogaina o fa'atonuga (SgCores) mai le Libero SoC IP
fa'amaumauga. E manaʻomia le taulimaina faʻapitoa mo soʻo se poloka e aofia ai galuega SoC:

• PolarAfi
  – PF_UPROM
  – PF_SYSTEM_SERVICES
  – PF_CCC
  – PF CLK DIV
  – PF_CRYPTO
  – PF_DRI
  – PF_INIT_MONITOR
  – PF_NGMUX
  – PF_OSC
  - RAM (TPSRAM, DPSRAM, URAM)
  – PF_SRAM_AHBL_AXI
  – PF_XCVR_ERM
  – PF_XCVR_REF_CLK
  – PF_TX_PLL
  – PF_PCIE
  – PF_IO
  – PF_IOD_CDR
  – PF_IOD_CDR_CCC
  – PF_IOD_GENERIC_RX
  – PF_IOD_GENERIC_TX
  – PF_IOD_GENERIC_TX_CCC
  – PF_RGMII_TO_GMII
  – PF_IOD_OCTAL_DDR
  – PF_DDR3
  – PF_DDR4
  – PF_LPDDR3
  – PF_QDR
  – PF_CORESMARTBERT
  – PF_TAMPER
  – PF_TVS, ma isi.

I le faaopoopo atu i le SgCores o loʻo lisiina muamua, o loʻo i ai le tele o DirectCore malu IP o loʻo avanoa mo PolarFire ma PolarFire SoC masini aiga i le Libero SoC Catalog o loʻo faʻaogaina punaoa ie FPGA.
Mo le tusiaina o mamanu, afai e te faʻaogaina se tasi o vaega muamua, e tatau ona e faʻaogaina le Libero SoC mo se vaega o le faʻasologa o le mamanu (Component Configuration), ae e mafai ona e faʻaauau le vaega o totoe o lau Design Entry (HDL entry, ma isi) i fafo atu o Libero. Ina ia pulea le FPGA mamanu tafe i fafo atu o Libero, mulimuli i laasaga o loʻo tuʻuina atu i le vaega o totoe o lenei taʻiala.
1.1 Vaega o le Ta'amilosaga o le Ola (Fai se Fesili)
O laasaga nei o loʻo faʻamatalaina ai le taamilosaga o le olaga o se vaega SoC ma tuʻuina atu faʻatonuga ile faʻaogaina o faʻamaumauga.

1. Fausia le vaega e faʻaaoga ai lona faʻaoga ile Libero SoC. Ole mea lea e maua ai ituaiga fa'amaumauga nei:
   - HDL files
   – Manatu files
   – Fa'aosofia ma Fa'ata'ita'iga files
   - Vaega SDC file
2. Mo le HDL files, vave faʻapipiʻi ma tuʻufaʻatasia i latou i le vaega o totoe o le HDL design e faʻaaoga ai le meafaigaluega / faʻagasologa o mea e faʻaogaina ai fafo.
3. Tuuina atu manatuaga files ma fa'aosofia files i lau meafaigaluega simulation.
4. Sapalai Vaega SDC file e maua ai le mea faigaluega fa'agata mo le fa'atupuina o fa'alavelave. Silasila i le Fa'aopoopoga C—Ausia Fa'agata mo nisi fa'amatalaga.
5. E tatau ona e faia se poloketi Libero lona lua, lea e te faʻaulufale mai ai le post-Synthesis netlist ma au metadata vaega, ma faʻamaeʻa ai le fesoʻotaʻiga i le va o mea na e gaosia ma mea na e faʻapipiʻiina.

1.2 Libero SoC Poloketi Fausia (Fai se Fesili)
O nisi laasaga mamanu e tatau ona faʻatautaia i totonu ole siosiomaga Libero SoC (Laulau 1-1). Mo nei laasaga e tamoe, e tatau ona e fatuina ni poloketi Libero SoC e lua. O le poloketi muamua o loʻo faʻaaogaina mo le faʻatulagaina o vaega o le mamanu ma le faʻatupuina, ma o le poloketi lona lua e mo le faʻatinoina faaletino o le mamanu pito i luga.
1.3 Fa'asologa Fa'apitoa (Fai se Fesili)
O lo'o fa'aalia i le ata lenei:

• Libero SoC e mafai ona tuʻufaʻatasia e avea o se vaega o le tele o le FPGA design flow faʻatasi ai ma le faʻaogaina o mea faʻapitoa ma faʻataʻitaʻiga i fafo atu o le siosiomaga Libero SoC.
• Laasaga eseese e aofia ai i le tafe, amata mai le fausiaina o mamanu ma su'i le auala atoa i le polokalame o le masini.
• Le fesuiaiga o faʻamatalaga (faʻapipiʻi ma mea e fai) e tatau ona tupu i laasaga taʻitasi o mamanu.

Motugaafa:

1. SNVM.cfg, UPROM.cfg
2. *.mem file fa'atupuina mo Fa'ata'ita'iga: pa4rtupromgen.exe ave UPROM.cfg e fai ma fa'aoga ma fa'atupuina UPROM.mem.

O laasaga nei i le fa'asologa masani:

1. Fa'aopoopo vaega ma fa'atupuina:
   a. Fausia se poloketi Libero muamua (e avea o se Poloketi Faʻamatalaga).
   e. Filifili le Core mai le Catalog. Fa'alua kiliki le autu e tu'u ai se igoa vaega ma fa'atulaga le vaega.
   E otometi lava ona auina atu i fafo faʻamatalaga vaega ma files. E fa'atupuina fo'i se Fa'aaliga Fa'aopoopo. Va'ai Fa'aaliga Fa'aopoopo mo fa'amatalaga. Mo nisi fa'amatalaga, va'ai Fa'atonu Fa'aopoopo.
2. Fa'auma lau mamanu RTL i fafo atu o Libero:
   a. Fa'apipi'i le vaega HDL files.
   e. Le nofoaga o le HDL files o lo'o lisiina i le Fa'aaliga Fa'aopoopo files.
3. Fa'atupu fa'alavelave SDC mo vaega. Fa'aaogā le fa'agata o le fa'atupuina o le fa'agata taimi file(SDC) fa'avae ile:
   a. Vaega HDL files
   e. Vaega SDC files
   i. Tagata fa'aoga HDL files
   Mo nisi fa'amatalaga, taga'i i le Fa'aopoopo C—Auina Fa'agata.
4. Meafaigaluega/meafaigaluega fa'ata'oto:
   a. Maua le HDL files, fa'aosofia files, ma fa'amatalaga vaega mai nofoaga fa'apitoa e pei ona ta'ua i le Fa'aaliga Fa'aopoopo.
   e. Fa'apipi'i ma fa'ata'ita'i le fa'ata'ita'iga ma mea faigaluega lona tolu i fafo atu o le Libero SoC.
5. Fausia lau Poloketi Libero lona lua (Fa'atinoga).
6. Ave'ese fa'asologa mai le filifili mea faigaluega fa'asolo mamanu (Project > Project Settings > Design Flow > fa'amama le Enable Synthesis check box).
7. Fa'aulufale mai le puna mamanu files (post-synthesis *.vm netlist mai meafaigaluega fa'apipi'i):
   – Fa'aulufale mai pe a mae'a fa'asologa *.vm netlist (File> Fa'aulufaleina> Fa'aigoaina Verilog Netlist (VM)).
   – Metadata vaega *.cfg files mo uPROM ma/poʻo le sNVM.
8. Fa'aulufale mai so'o se vaega poloka poloka Libero SoC files. O le poloka files e tatau ona i totonu o le *.cxz file faatulagaga.
   Mo nisi faʻamatalaga ile auala e fai ai se poloka, vaʻai PolarFire Block Flow User Guide.
9. Fa'aulufale mai le fa'atapula'aina o mamanu:
   – Fa'aulufale mai I/O fa'agata files (Fa'atonu Pule > I/OAttributes > Fa'aulufale mai).
   – Fa'aulufaleina o fola *.pdc files (Pule Fa'agata > Fuafuaga Folafola > Fa'aulufale mai).
   – Fa'aulufaleina *.sdc taimi fa'atapula'aina files ( Pule Fa'agata > Taimi > Fa'aulufale mai). Fa'aulufale mai le SDC file fa'atupuina e ala i le mea faigaluega Fa'agata.
   – Fa'aulufaleina *.ndc fa'agata files (Fa'atonu Pule> NetlistAttributes> Fa'aulufale mai), pe a iai.
10. Taofi file ma meafaigaluega fa'atasi
    – I le Pule Fa'atonu, fa'afeso'ota'i le *.pdc files e tu'u ma ala, o le *.sdc files e tu'u ma ala ma fa'amaoniga taimi, ma le *.ndc files e Tuufaatasia Netlist.
11. Faʻataunuʻuina le mamanu atoatoa
    - Nofoaga ma le ala, faʻamaonia le taimi ma le malosi, faʻapipiʻi faʻamaumauga faʻavae mamanu ma manatuaga, ma polokalame file tupulaga.
12. Fa'amaonia le mamanu
    - Faʻamaonia le mamanu i luga o le FPGA ma debug pe a manaʻomia e faʻaaoga ai meafaigaluega mamanu tuʻuina atu i le Libero SoC design suite.

Fa'asologa o vaega (Fai se Fesili)

O le laasaga muamua i le aganuʻu masani o le faʻapipiʻiina lea o au vaega e faʻaaoga ai se faʻataʻitaʻiga o le Libero (faʻapitoa foʻi le poloketi Libero muamua i le Laulau 1-1). I laasaga mulimuli ane, e te faʻaogaina faʻamatalaga mai lenei galuega faʻasino.
Afai o loʻo e faʻaaogaina soʻo se vaega o loʻo lisiina muamua, i lalo ole Ovaview i lau mamanu, fai laasaga o loʻo faʻamatalaina i lenei vaega.
Afai e te le o faʻaaogaina soʻo se vaega o loʻo i luga, e mafai ona e tusia lau RTL i fafo atu o Libero ma faʻaulu saʻo mai i totonu o au meafaigaluega faʻapitoa ma Simulation. Ona mafai lea ona e agai atu i le vaega post-synthesis ma na o le faaulufaleina mai o lau post-synthesis *.vm netlist i lau galuega faatino mulimuli Libero (e ta'ua foi lona lua Libero poloketi i le Laulau 1-1).
2.1 Fa'asologa o vaega Fa'aaogāina Libero (Fai se Fesili)
A maeʻa ona filifilia vaega e tatau ona faʻaaogaina mai le lisi muamua, fai laasaga nei:

1. Fausia se galuega fou Libero (Fa'atonuga Autu ma Tupulaga): Filifili le Meafaigaluega ma le Aiga e te fa'amoemoe i ai lau mamanu mulimuli.
2. Fa'aoga se tasi po'o le sili atu o 'autu o lo'o ta'ua i le Custom Flow.
   a. Fausia se SmartDesign ma faʻapipiʻi le autu manaʻomia ma faʻapipiʻi i le vaega SmartDesign.
   e. Siitia pine uma i le tulaga maualuga.
   i. Fausia le SmartDesign.
   o. Fa'alua kiliki le mea faigaluega Fa'ata'ita'i (so'o se Pre-Synthesis po'o Post-Synthesis po'o Post-Layout filifiliga) e fa'aoga ai le simulator. E mafai ona e alu ese mai le simulator pe a uma ona faʻaogaina. O lenei laasaga e faʻatupuina ai le faʻataʻitaʻiga filee mana'omia mo lau poloketi.

Motugaafa: O oe e tatau ona faia lenei laasaga pe afai e te manaʻo e faʻataʻitaʻiina lau mamanu i fafo atu o Libero.
Mo nisi fa'amatalaga, va'ai Fa'ata'ita'i o Lau Fa'ailoga.
u. Fa'asaoina lau poloketi—o lau galuega fa'asino lea.
2.2 Fa'aaliga Fa'apitoa (Fai se Fesili)
A e gaosia au vaega, se seti o files ua gaosia mo vaega taitasi. O le lipoti o le Component Manifest o loʻo faʻamatalaina le seti o files fa'atupuina ma fa'aogaina i laasaga ta'itasi mulimuli ane (Synthesis, Simulation, Firmware Generation, ma isi). O lenei lipoti e tu'uina atu ia te oe nofoaga o mea uma na gaosia files e mana'omia e fa'agasolo ai le Fa'asologa Fa'asinomaga. E mafai ona e mauaina le vaega faʻaalia i le vaega o Lipoti: Kiliki Design> Lipoti e tatala ai le Lipoti faʻamau. I le lisi o Lipoti, e te va'aia ai se seti o manifest.txt files (Ovaview), tasi mo vaega taitasi na e fatuina.
Motugaafa: E tatau ona e setiina se vaega po'o se module e fai ma '”root”' e va'ai ai le vaega fa'aalia file mea i totonu o le Lipoti fa'amau.
I le isi itu, e mafai ona e mauaina le lipoti faʻaaliga taʻitasi files mo vaega autu ta'itasi na gaosia po'o vaega SmartDesign mai /vaega/galuega/ / / _manifest.txt po'o /vaega/galuega/ / _manifest.txt. E mafai fo'i ona e maua le fa'aaliga file mea o lo'o i totonu o vaega ta'itasi na fa'atupuina mai i le lisi fou o Vaega i Libero, lea o le file o lo'o ta'ua nofoaga e fa'atatau i le lisi o galuega.Taulai atu i lipoti nei Component Manifest:

• Afai na e faʻapipiʻiina fatu i totonu o se SmartDesign, faitau le file _manifest.txt.
• Afai na e fatuina vaega mo 'au, faitau le _manifest.txt.

E tatau ona e fa'aogaina uma lipoti Fa'aaliga Fa'atusa e fa'atatau i lau mamanu. Mo example, afai o lau poloketi o loʻo i ai se SmartDesign ma se tasi pe sili atu vaega autu faʻapipiʻiina i totonu ma e te faʻamoemoe e faʻaoga uma i lau mamanu mulimuli, ona tatau lea ona e filifilia files o lo'o lisiina i le Component Manifests lipoti o na vaega uma mo le fa'aogaina i lau fa'asologa o mamanu.
2.3 Fa'amatala Fa'aaliga Files (Fai se Fesili)
A e tatalaina se vaega faʻaaliga file, e te iloa atu ala i files i lau poloketi Libero ma faʻamatalaga i le mea o loʻo tafe ai le mamanu e faʻaoga ai. Atonu e te va'ai i ituaiga nei o files i se fa'aaliga file:

• HDL puna files mo meafaigaluega uma Fa'asologa ma Fa'ata'ita'iga
• Fa'aosofia files mo meafaigaluega uma Simulation
• Taofi files

O lo'o mulimuli mai le Fa'aaliga Fa'apitoa o se vaega autu PolarFire.O ituaiga taitasi o file e mana'omia i lalo i lau fa'asologa o mamanu. O vaega nei o lo'o fa'amatalaina le tu'ufa'atasiga o le files mai le faʻaaliga i lau faʻasologa o mamanu.

Fa'atupu Fa'alavelave (Fai se Fesili)

A fa'atinoina le fa'atulagaina ma le fa'atupuina, fa'amautinoa e tusi/faia le SDC/PDC/NDC fa'agata files mo le mamanu e pasi atu i latou i le Synthesis, Place-and-Route, ma Faʻamaonia meafaigaluega Taimi.
Fa'aoga le fa'aogaina o le Fa'atupu Fa'agata i fafo atu o le si'osi'omaga o Libero e fa'atupu ai fa'alavelave nai lo le tusia ma le lima. Ina ia fa'aogaina le fa'aoga o le Derive Constraint i fafo atu o le siosiomaga Libero, e tatau ona e:

• Tuuina atu le tagata fa'aoga HDL, vaega HDL, ma vaega SDC fa'agata files
• Fa'ailoa le vaega pito i luga module
• Fa'ailoa le nofoaga e fa'atupu ai le fa'atupu fa'alavelave files

O fa'agata vaega SDC o lo'o maua i lalo /vaega/galuega/ / / directory pe a maeʻa le faʻatulagaina o vaega ma le faʻatupuina.
Mo nisi fa'amatalaga i le fa'atupuina o fa'alavelave mo lau mamanu, va'ai le Fa'aopoopo C—Fa'atapula'aina.

Tu'ufa'atasia Lau Fa'ailoga (Fai se Fesili)

O se tasi o vaega autu o le Custom Flow o le faʻatagaina oe e faʻaogaina se faʻasologa o isi vaega
meafaigaluega i fafo atu o Libero. Ole aganu'u masani e lagolagoina le fa'aogaina ole Synopsys SynplifyPro. Ina ia tuufaatasia lau
galuega faatino, fa'aaoga le faiga lenei:

1. Fausia se poloketi fou i lau meafaigaluega Fa'aupuga, faʻatatau i le aiga masini tutusa, oti, ma afifi e pei o le Libero poloketi na e faia.
   a. Fa'aulufale mai lau lava RTL filee pei ona e masani ai.
   e. Seti le fa'asologa o le Synthesis e avea ma Structural Verilog (.vm).
   Motugaafa: Structural O Verilog (.vm) e na'o le pau lea o le fa'asologa o fa'asologa o fa'asologa o galuega i PolarFire.
2. Fa'aulufaleina Vaega HDL files i lau galuega fa'akomepiuta:
   a. Mo Lipoti o Fa'aaliga Fa'aaliga taitasi: Mo ta'itasi file i lalo ole HDL puna files mo meafaigaluega uma Fa'asologa ma Simulation, fa'aulufale mai le file i lau Poloketi Synthesis.
3. Fa'aulufale mai le file polarfire_syn_comps.v (pe a faʻaaogaina Synopsys Synplify) mai
   Nofoaga fa'apipi'i>/fa'amatalaga/aPA5M i lau galuega fa'atino.
4. Fa'aulufale mai le SDC na faia muamua file e ala i le mea faigaluega Fa'agata (va'ai Fa'aopoopo
   A—Sample SDC Fa'agata) i totonu o le meafaigaluega fa'asuesue. O lenei fa'alavelave file fa'atapula'aina le meafaigaluega tu'ufa'atasia e ausia ai le tapuni taimi ma le fa'aitiitia o taumafaiga ma fa'aitiitia le fa'asologa o mamanu.

Taua: 

• Afai e te fuafua e fa'aoga tutusa *.sdc file e taofiofia le Nofoaga ma le Auala i le taimi o le faʻatinoga o le mamanu, e tatau ona e faʻaulufaleina le *.sdc i totonu o le galuega faʻapipiʻi. O le mea lea e fa'amautinoa ai e leai ni mea fa'atusa e fetaui ma igoa i totonu o le upega fa'apipi'i fa'atasi ma fa'agata Nofoaga-ma-Ala i le taimi o le fa'atinoga o le fa'asologa o le mamanu. Afai e te le fa'aofiina le *.sdc file i le Laasaga Fa'aopoopo, o le upegatafa'ilagi e maua mai le Synthesis e ono fa'aletonu le La'asaga o le Nofoaga ma le Auala ona o le le fetaui o igoa o mea.
  a. Fa'aulu mai Attributes Netlist *.ndc, pe afai ei ai, i totonu o le meafaigaluega Fa'aopoopo.
  e. Fa'agasolo Fa'atasi.
• O le nofoaga o lo'o iai lau fa'aoga meafaigaluega fa'apitoa e iai le *.vm netlist file fa'atupuina fa'asologa fa'asologa. E tatau ona e fa'aulufale mai le lisi o upega i totonu o le Libero Implementation Project e fa'aauau ai le faiga o le mamanu.

Fa'ata'ita'iina o Lau Fa'ailoga (Fai se Fesili)

Ina ia faʻataʻitaʻiina lau mamanu i fafo atu o Libero (o lona uiga, faʻaaogaina lau lava siʻosiʻomaga faʻataʻitaʻiga ma simulator), fai laasaga nei:

1. Fuafuaga Files:
   a. Fa'ata'ita'iga a'o le'i fa'aogaina:
   • Fa'aulufale mai lau RTL i lau galuega fa'ata'ita'i.
   • Mo Lipoti o Fa'aaliga Fa'apitoa ta'itasi.
   – Fa'aulufale mai ta'itasi file i lalo ole HDL puna files mo meafaigaluega uma Fa'atusa ma Fa'ata'ita'iga i lau galuega fa'atusa.
   • Tuufaatasia mea nei filee pei o faatonuga a lau simulator.
   e. Fa'ata'ita'iga pe a mae'a fa'asologa:
   • Fa'aulufale mai lau post-synthesis *.vm netlist (fausia i le Synthesizing Your Design) i lau galuega fa'ata'ita'i ma tu'ufa'atasia.
   i. Fa'ata'ita'iga pe a uma le fa'atulagaina:
   • Muamua, fa'amae'a le fa'atinoina o lau mamanu (silasila i le Fa'atinoina o Lau Fuafuaga). Ia mautinoa o lau poloketi Libero mulimuli o loʻo i ai i le tulaga post-layout.
   • Kiliki fa'alua Fa'atupu Tu'u Fa'amatalaga Files i le faamalama Libero Design Flow. E maua ai le lua files:
   /designer/ / _ba.v/vhd /designer/
   / _ba.sdf
   • Fa'aulufale mai ia mea uma e lua files i lau meafaigaluega fa'atusa.
2. Fa'aosofia ma Fa'atonu files:
   a. Mo Lipoti Fa'aaliga Fa'apitoa ta'itasi:
   • Kopi uma files i lalo ole Stimulus Files mo vaega uma o Meafaigaluega Faʻataʻitaʻiga i le faʻamaumauga aʻa o lau poloketi Faʻataʻitaʻiga.
   e. Ia mautinoa o soʻo se Tcl files i lisi muamua (i le Laasaga 2.a) e faʻatinoina muamua, aʻo leʻi amataina le faʻataʻitaʻiga.
   i. UPROM.mem: Afai e te faʻaogaina le UPROM autu i lau mamanu ma le filifiliga Faʻaaoga anotusi mo faʻataʻitaʻiga e mafai mo se tasi poʻo le sili atu o faʻamaumauga teu oloa e te manaʻo e faʻataʻitaʻiina, e tatau ona e faʻaogaina le pa4rtupromgen (pa4rtupromgen.exe i luga o windows) e faʻatupu ai le UPROM.mem file. O le pa4rtupromgen executable e ave le UPROM.cfg file e fai ma fa'aoga e ala ile Tcl script file ma maua ai le UPROM.mem file manaʻomia mo faʻataʻitaʻiga. O lenei UPROM.mem file e tatau ona kopi i le pusa faʻataʻitaʻiga aʻo leʻi faia le faʻataʻitaʻiga. O se example fa'aalia o le fa'aogaina o le pa4rtupromgen o lo'o tu'uina atu i la'asaga nei. O le UPROM.cfg file o lo'o maua ile fa'atonuga /vaega/galuega/ / i le poloketi Libero na e faʻaaogaina e gaosia ai le vaega UPROM.
   o. snvm.mem: Afai e te faʻaogaina le System Services core i lau mamanu ma faʻapipiʻi le sNVM tab i le autu ma le filifiliga Faʻaaoga mea mo le faʻataʻitaʻiga e mafai mo se tasi pe sili atu tagata e te manaʻo e faʻataʻitaʻi, a snvm.mem file e otometi ona gaosia i
   le lisi /vaega/galuega/ / i le poloketi Libero na e faʻaaogaina e faʻatupuina ai le vaega o le System Services. O lenei snvm.mem file e tatau ona kopi i le pusa faʻataʻitaʻiga aʻo leʻi faia le faʻataʻitaʻiga.
3. Fausia se faila galue ma se faila laʻititi e taʻua o le simulation i lalo o le faila galue.
   O le pa4rtupromgen executable faamoemoeina le i ai o le simulation sub folder i le galuega faila ma le * .tcl script o loʻo tuʻuina i le simulation sub folder.
4. Kopi le UPROM.cfg file mai le uluai poloketi Libero na faia mo le gaosiga o vaega i totonu o le faila galue.
5. Fa'apipi'i tulafono nei i totonu o le *.tcl script ma tu'u i totonu o le pusa fa'ata'ita'i na faia i le Laasaga 3.
   Sample *.tcl mo masini PolarFire ma PolarFire Soc Family e gaosia ai le URPOM.mem file
   mai UPROM.cfg
   seti_masini -fam - oti -pkg
   seti_input_cfg -ala
   seti_sim_mem -alaFile/UPROM.mem>
   gen_sim -use_init sese
   Mo le igoa sa'o totonu e fa'aoga mo le mate ma le afifi, va'ai le *.prjx file o le uluai poloketi Libero (faʻaaogaina mo le gaosiga o vaega).
   Ole finauga use_init e tatau ona seti ile sese.
   Fa'aaoga le seti_sim_mem poloaiga e fa'ailoa ai le ala i le gaioiga file UPROM.mem o le
   fa'atupuina i le fa'atinoina o le tusitusiga file fa'atasi ai ma le pa4rtupromgen e mafai ona fa'atinoina.
6. I le command prompt poʻo le cygwin terminal, alu i le lisi galue na faia i le laasaga 3.
   Fa'atino le fa'atonuga pa4rtupromgen ma le–script filifiliga ma pasi i ai le *.tcl script na faia i le laasaga muamua.
   Mo Windows
   /designer/bin/pa4rtupromgen.exe \
   –script./simulation/ .tcl
   Mo Linux:
   /bin/pa4rtupromgen
   –script./simulation/ .tcl
7. A maeʻa le faʻatinoina o le pa4rtupromgen executable, siaki le UPROM.mem file e gaosia i le nofoaga o loʻo faʻamaonia i le seti_sim_mem poloaiga i le * .tcl script.
8. Ina ia fa'atusa le sNVM, kopi le snvm.mem file mai lau poloketi Libero muamua (faʻaaogaina mo le faʻatulagaina o vaega) i totonu o le pusa faʻataʻitaʻiga pito i luga o lau faʻataʻitaʻiga faʻataʻitaʻiga e faʻatautaia ai faʻataʻitaʻiga (i fafo atu o Libero SoC). Ina ia fa'atusa mea UPROM, kopi le UPROM.mem ua gaosia file i totonu o le pusa faʻataʻitaʻiga pito i luga o lau poloketi faʻataʻitaʻiga e faʻatautaia ai faʻataʻitaʻiga (i fafo atu o le Libero SoC).

Taua: I fa'ata'ita'i le fa'atinoga o SoC Components, la'u mai faletusi fa'ata'ita'i a PolarFire ma fa'aulufale mai i totonu o lau si'osi'omaga fa'ata'ita'iga e pei ona fa'amatalaina iinei. Mo nisi fa'amatalaga, taga'i i le Fa'aopoopoga B—Fa'aulufaleina o Faletusi Fa'atusa ile Si'osi'omaga Fa'atusa.

Fa'atinoina o Lau Fuafuaga (Fai se Fesili)

A maeʻa le faʻataʻitaʻiga o le Synthesis ma le Post-Synthesis i lou siosiomaga, e tatau ona e toe faʻaogaina le Libero e faʻatino ai lau mamanu, faʻatautaia taimi ma suʻesuʻega eletise, ma faʻatupu lau polokalame. file.

1. Fausia se poloketi Libero fou mo le faʻatinoga faaletino ma le faʻatulagaina o le mamanu. Ia mautinoa e fa'atatau i le masini lava e tasi e pei o le galuega fa'asino na e faia i le Component Configuration.
2. A maeʻa le faʻatulagaina o le poloketi, aveese le Synthesis mai le filifili meafaigaluega i le faʻamalama o le Fuafuaga (Project> Project Settings> Design Flow> Uncheck Enable Synthesis).
3.  Fa'aulufale mai lau post-synthesis *.vm file i lenei poloketi, (File > Fa'aulufale mai > Fa'atasia Verilog Netlist (VM)).
   Motugaafa: E fautuaina e te faia se sootaga i lenei mea file, o lea afai e te toe faʻafouina lau mamanu, e faʻaaoga pea e Libero le upega tafaʻilagi lata mai post-synthesis.
   a. I le matala Design Hierarchy, matau le igoa o le module root.
4. Fa'aulufale mai fa'agata i totonu ole poloketi Libero. Fa'aoga le Pule Fa'atonu e fa'aulu mai ai *.pdc/*.sdc/*.ndc fa'agata.
   a. Fa'aulufale mai I/O *.pdc fa'agata files (Pule Fa'agata > Uiga I/O > Fa'aulufale mai).
   e. Fa'aulufale Fuafuaga *.pdc fa'agata files (Pule Fa'agata > Fuafuaga Folafola > Fa'aulufale mai).
   i. Fa'aulufale *.sdc taimi fa'atapula'aina files ( Pule Fa'agata > Taimi > Fa'aulufale mai). Afai o lau mamanu o loʻo i ai soʻo se fatu o loʻo lisiina i lugaview, fa'amautinoa e fa'aulufale mai le SDC file fa'atupuina e ala i mea faigaluega fa'agata.
   o. Fa'aulufale *.ndc fa'agata files ( Pule Fa'agata > Uiga Netlist > Fa'aulufale mai).
5. Fa'agata Fa'atasi Files e mamanuina meafaigaluega.
   a. Tatala Pule Fa'atonu (Manage Constraints > Open Manage Constraints View).
   Siaki le Nofoaga-ma-Ala ma le Taimi Fa'amaonia pusa siaki i tafatafa o le fa'agata file e fa'atupu fa'agata file ma meafaigaluega fa'atasi. Fa'afeso'ota'i le *.pdc fa'agata i le Place-and-Route ma le *.sdc i le Nofoaga-ma-Ala ma le Taimi Fa'amaonia. Fa'afeso'ota'i le *.ndc file e Tuufaatasia Netlist.
   Motugaafa: Afai Ua le manuia le Nofoaga ma le Auala i lenei *.sdc fa'agata file, ona faaulufale mai lea *.sdc file e fa'atupu fa'atasi ma toe ta'avale fa'atasi.
6. Kiliki Compile Netlist ona tu'u lea ma le Auala e fa'auma ai le la'asaga fa'atulagaina.
7. O le Configure Design Initialization Data and Memories tool e mafai ai ona e amataina poloka mamanu, e pei o le LSRAM, µSRAM, XCVR (transceivers), ma le PCIe e faʻaaoga ai faʻamatalaga o loʻo teuina i le nonvolatile μPROM, sNVM, poʻo fafo SPI Flash memory storage. O le meafaigaluega o loʻo i ai faʻamaufaʻailoga o loʻo i lalo mo le faʻamalamalamaina o le faʻamatalaga o le faʻasologa o le amataga o le mamanu, o le faʻamatalaga o tagata faʻatau muamua, tagata faʻatau faʻamatalaga.
   - Fuafuaga Initialization tab
   - µPROM laupepa
   - sNVM laupepa
   - SPI Flash tab
   - Faʻailoga RAM ie
   Fa'aoga fa'amau i le mea faigaluega e fa'atulaga ai fa'amaumauga o fa'amatalaga amata ma manatuaga.A mae'a le fa'atulagaina, fai laasaga nei e fa'apolokalame ai fa'amaumauga amata:
   • Fa'atupuina tagata fa'atau
   • Fausia pe auina atu i fafo le bitstream
   • Polokalama le masini
   Mo faʻamatalaga auiliili ile faʻaogaina o lenei meafaigaluega, vaʻai Libero SoC Design Flow User Guide. Mo nisi faʻamatalaga i luga o tulafono Tcl faʻaaogaina e faʻapipiʻi ai laupepa eseese i le meafaigaluega ma faʻamaonia le faʻatulagaina o mafaufauga files (*.cfg), vaai Tcl Commands Reference Guide.
8. Fausia se Polokalama File mai lenei poloketi ma fa'aoga e fa'apolokalame ai lau FPGA.

Fa'aopoopo A—Sample SDC Fa'agata (Fai se Fesili

Libero SoC fa'atupu SDC taimi fa'agata mo nisi IP cores, pei o le CCC, OSC, Transceiver ma isi. O le tu'uina atu o fa'agata a le SDC i mea faigaluega fa'ata'atia e fa'atuputeleina ai le avanoa e fa'ato'a tapunia ai le taimi ma le fa'aitiitia o taumafaiga ma fa'aitiitia le fa'asologa o mamanu. O le ala fa'akomepiuta atoa mai le fa'ata'ita'iga pito i luga o lo'o tu'uina atu mo mea fa'atusa uma o lo'o fa'asino i totonu o fa'alavelave.
7.1 SDC Tapulaa Taimi (Fai se Fesili)
I le Libero IP autu fa'asino galuega, lenei tulaga maualuga SDC fa'agata file e maua mai le Pule Fa'atonu (Design Flow > Open Manage Constraint View > Taimi > Fa'atupu Fa'agata).
Taua: Vaai lenei file e seti le SDC fa'agata pe afai o lau mamanu o loʻo i ai CCC, OSC, Transceiver, ma isi vaega. Suia le ala fa'atulagaina atoa, pe a mana'omia, ia fa'afetaui lau fa'asologa o le mamanu po'o le fa'aoga o le fa'aoga o le Derive_Constraints ma la'asaga i le Fa'aopoopo C—Fa'atupu Fa'agata ile vaega SDC. file.
Faasaoina le file i se isi igoa ma aumai le SDC file i le meafaigaluega fa'apipi'i, Place-and-Route Tool, ma Taimi Fa'amaoniga, pei lava o so'o se fa'agata SDC. files.
7.1.1 Fa'avae SDC File (Fai se Fesili)
# Lenei file na fa'atupuina e fa'atatau i le puna SDC lea files:
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
CLK_DIV/CLK_DIV_0/CLK_DIV_CLK_DIV_0_PF_CLK_DIV.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
TRANSMIT_PLL/TRANSMIT_PLL_0/TRANSMIT_PLL_TRANSMIT_PLL_0_PF_TX_PLL.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
DMA_INITIATOR/DMA_INITIATOR_0/DMA_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
FIC0_INITIATOR/FIC0_INITIATOR_0/FIC0_INITIATOR.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
ICICLE_MSS/ICICLE_MSS.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PF_PCIE_C0/PF_PCIE_C0_0/PF_PCIE_C0_PF_PCIE_C0_0_PF_PCIE.sdc
# /drive/icicle_kit_ref_des/icicle-kit-reference-design-master/MPFS_ICICLE/component/work/
PCIE_INITIATOR/PCIE_INITIATOR_0/PCIE_INITIATOR.sdc
# /drive/aPA5M/cores/constraints/osc_rc160mhz.sdc
# *** So'o se suiga i lenei mea file o le a leiloa pe a toe fa'aogaina fa'agata fa'atupu. ***
create_clock -name {CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK} -vaitaimi 6.25
[ maua pine { CLOCKS_AND_RESETS_inst_0/OSCILLATOR_160MHz_inst_0/OSCILLATOR_160MHz_0/
I_OSC_160/CLK } ] create_clock -igoa {REF_CLK_PAD_P} -vaitaimi 10 [ get_ports { REF_CLK_PAD_P } ] create_clock -igoa {CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/TRANSt_0PLL
DIV_CLK} -vaitaimi 8
[ get_pins { CLOCKS_AND_RESETS_inst_0/TRANSMIT_PLL_0/TRANSMIT_PLL_0/txpll_isnt_0/DIV_CLK } ] create_generated_clock -igoa {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x/CLK_0_inst_0/CCC_FIC_x/CLK_0_inst_clock
OUT0} -faatele_i le 25 -vaevae_i le 32 -puna
[ maua pine { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -vaega 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT0 } ] create_generated_clock -igoa {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_inst_0/CCC_FIC_x_CLK/PF_0
OUT1} -faatele_i le 25 -vaevae_i le 32 -puna
[ maua pine { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -vaega 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT1 } ] create_generated_clock -igoa {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_inst_0/CCC_FIC_x_CLK/PF_0
OUT2} -faatele_i le 25 -vaevae_i le 32 -puna
[ maua pine { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -vaega 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT2 } ] create_generated_clock -igoa {CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK_inst_0/CCC_FIC_x_CLK/PF_0
OUT3} -faatele_i le 25 -vaevae_i le 64 -puna
[ maua pine { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/REF_CLK_0 } ] -vaega 0
[ get_pins { CLOCKS_AND_RESETS_inst_0/CCC_FIC_x_CLK/PF_CCC_C0_0/pll_inst_0/OUT3 } ] create_generated_clock -igoa {CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz_to_CLK_0MHz
Y_DIV} -vaevae_i le 2 -puna
[ get_pins { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80MHz/CLK_DIV_0/I_CD/A } ] [ get_pins { CLOCKS_AND_RESETS_inst_0/CLK_160MHz_to_CLK_80_MHz/DIV_DIV} seti_ala_sese -e ala i [ get_nets { DMA_INITIATOR_inst_0/ARESETN* } ] seti_ala_sese -mai [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/rdGrayCounter*/cntGray* } ] -to [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
rdPtr_s1* } ] set_false_path -mai [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/
genblk1*/wrGrayCounter*/cntGray* } ] -to [ get_cells { DMA_INITIATOR_inst_0/*/SlvConvertor_loop[*].slvcnv/slvCDC/genblk1*/
wrPtr_s1* } ] seti_ala_sese -e ala i [ get_nets { FIC0_INITIATOR_inst_0/ARESETN* } ] seti_ala_sese -i [ get_pins { PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[0] PCIE/PF_0/PCIE_C0
PCIE_1/INTERRUPT[1] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[2] PCIE/PF_PCIE_C0_0/PCIE_1/
INTERRUPT[3] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[4] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[5] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[6] PCIE/PF_PCIE_C0_0/PCIE_1/INTERRUPT[7] PCIE/PF_PCIE_C0_0/
PCIE_1/WAKEREQ PCIE/PF_PCIE_C0_0/PCIE_1/MPERST_N } ] seti_ala_sese -mai [ get_pins { PCIE/PF_PCIE_C0_0/PCIE_1/TL_CLK } ] seti_ala_sese -e ala i [ get_nets/_REST_INI] Fa'aopoopo B—Fa'aulufaleina o Faletusi Fa'ata'ita'i ile Si'osi'omaga Fa'atusa (Fai se Fesili)
O le simulator le aoga mo RTL simulation ma Libero SoC o le ModelSim ME Pro.
O faletusi ua uma ona tu'ufa'atasia mo le simulator fa'aletonu o lo'o avanoa ma fa'apipi'i Libero ile fa'atonuga /Designer/lib/modelsimpro/precompiled/vlog for® lagolago aiga. O loʻo lagolagoina foi e Libero SoC isi faʻataʻitaʻiga simulators lona tolu o ModelSim, Questasim, VCS, Xcelium
, Active HDL, ma Riviera Pro. La'u mai i lalo faletusi na mua'i tuufaatasia mai Libero SoC v12.0 ma mulimuli ane faʻavae i luga o le simulator ma lona faʻasologa.
E tutusa ma le siosiomaga Libero, run.do file e tatau ona faia e faʻataʻitaʻi faʻataʻitaʻiga i fafo atu o Libero.
Fausia se run.do faigofie file o lo'o i ai fa'atonuga e fa'atūina ai le faletusi mo fa'ai'uga tu'ufa'atasia, fa'afanua faletusi, tu'ufa'atasiga, ma fa'atusa. Mulimuli i laasaga e fai ai se run.do faavae file.

1. Fausia se faletusi talafeagai e teu ai faʻamaumauga tuʻufaʻatasia e faʻaaoga ai le vlib command vlib presynth.
2. Fa'afanua le igoa o le faletusi sa'o ile fa'atonuga o le faletusi na fa'apipi'i muamua e fa'aaoga ai le vmap command vmap .
3. Tuufaatasi puna files—fa'aoga fa'atonuga tu'ufa'atasi gagana e tu'ufa'atasia le mamanu files i totonu o le tusi galue.
   – vlog mo .v/.sv
   – vcom mo .vhd
4. Uta le mamanu mo faʻataʻitaʻiga e faʻaaoga ai le vsim poloaiga e ala i le faʻamaonia o igoa o soʻo se vaega pito i luga.
5. Fa'ata'ita'i le mamanu e fa'aaoga ai le fa'atonuga.
   A maeʻa le utaina o le mamanu, faʻatulagaina le taimi faʻataʻitaʻiga i le zero, ma e mafai ona e ulufale i le faʻatonuga o le taʻavale e amata ai le faʻataʻitaʻiga.
   I le faʻamalama faʻasologa o le simulator, faʻatino run.do file e pei o le run.do tamoe le simulation. Sample run.do file e pei ona taua i lalo.

seti filemu ACTELLIBNAME PolarFire seti filemu PROJECT_DIR “W:/Test/basic_test” pe afai
{[file exists presynth/_info]} { echo “INFO: Simulation library presynth exists” } isi
{ file tape -force presynth vlib presynth } vmap presynth presynth vmap PolarFire
“X:/Libero/Designer/lib/modelsimpro/precompiled/vlog/PolarFire” vlog -sv -work presynth
“${PROJECT_DIR}/hdl/top.v” vlog “+incdir+${PROJECT_DIR}/stimulus” -sv -work presynth “$
{PROJECT_DIR}/stimulus/tb.v” vsim -L PolarFire -L presynth -t 1ps presynth.tb faaopoopo galu /tb/*
tamoe 1000ns log /tb/* alu ese

Fa'aopoopo C—Ave Fa'agata (Fai se Fesili)

O lenei faʻaopoopoga o loʻo faʻamatalaina ai le Deive Constraints Tcl commands.
9.1 Fa'atupu Fa'agata Tcl Poloaiga (Fai se Fesili)
O le derive_constraints aoga e fesoasoani ia te oe e maua ai faʻalavelave mai le RTL poʻo le configurator i fafo atu o le siosiomaga mamanu Libero SoC. Ina ia fa'atupu fa'alavelave mo lau mamanu, e te mana'omia le User HDL, Component HDL, ma Component Constraints files. O le SDC vaega fa'agata files o lo'o avanoa i lalo /vaega/galuega/ / / directory pe a maeʻa le faʻatulagaina o vaega ma le faʻatupuina.
Fa'agata vaega ta'itasi file e aofia ai le seti_component tcl poloaiga (faʻamaonia le igoa o le vaega) ma le lisi o faʻalavelave na faia pe a uma le faʻatulagaina. O faʻalavelave e faʻavaeina i luga o le faʻatulagaga ma e faʻapitoa i vaega taʻitasi.
Example 9-1. Vaega Fa'agata File mo le PF_CCC Core
O se ex leaample o se vaega faatapulaaina file mo le PF_CCC autu:
seti_vaega PF_CCC_C0_PF_CCC_C0_0_PF_CCC
# Microchip Corp.
# Aso: 2021-Oke-26 04:36:00
# Uati faavae mo PLL #0
fai_uati -vaitaimi 10 [ get_pins { pll_inst_0/REF_CLK_0 } ] create_generated_clock -vaevae_i le 1 -source [ get_pins { pll_inst_0/
REF_CLK_0 } ] -vase 0 [ get_pins { pll_inst_0/OUT0 } ] O iinei, create_clock ma create_generated_clock o fa'asinoga ma fa'alavelave uati, lea e gaosia e fa'atatau i le fa'atulagaina.
9.1.1 Galulue ma derive_constraints Utility (Fai se Fesili)
Fa'atupu fa'alavelave fa'asaga i le mamanu ma tu'ufa'atasiga fa'agata fou mo fa'ata'ita'iga ta'itasi o vaega fa'avae ile vaega SDC na tu'uina atu muamua. files. Mo le CCC fa'asino uati, e fa'asalalauina i tua e ala i le mamanu e su'e ai le puna o le fa'amatalaga uati. Afai ole fa'apogai ole I/O, ole fa'atonuga ole uati ole a fa'atulaga ile I/O. Afai o se CCC gaioiga po'o se isi fa'apogai uati (mo fa'aample, Transceiver, oscillator), e faʻaaogaina le uati mai le isi vaega ma lipotia se lapataiga pe a le fetaui va. Fa'atupu fa'agata o le a fa'asoa ai fo'i fa'agata mo nisi macros pei ole on-chip oscillators pe a iai i lau RTL.
Ina ia fa'atino le aoga derive_constraints, e tatau ona e tu'uina atu se .tcl file finauga laina fa'atonu ma fa'amatalaga nei i le fa'atonuga fa'atonu.

1. Fa'ailoa fa'amatalaga masini e fa'aoga ai fa'amatalaga ile vaega set_device.
2. Fa'ailoa le ala ile RTL files fa'aogaina le fa'amatalaga i le vaega read_verilog po'o le read_vhdl.
3. Seti vaega pito i luga e fa'aaoga ai fa'amatalaga ile vaega set_top_level.
4. Fa'ailoa le ala ile vaega SDC files fa'aogaina fa'amatalaga i le vaega read_sdc po'o le read_ndc.
5. Fa'atino le files fa'aaogaina fa'amatalaga i le vaega derive_constraints.
6.  Fa'ailoa le ala ile SDC fa'atupu fa'agata file fa'aaoga le fa'amatalaga i le vaega write_sdc po'o le write_pdc po'o le write_ndc.

Example 9-2. Fa'atinoga ma Anotusi o le derive.tcl File
O le mea lenei o se example faʻatonuga-laina finauga e faʻatino ai le aoga derive_constraints.
$ /bin{64}/derive_constraints derive.tcl
O mea o loʻo i totonu o le derive.tcl file:
# Faʻamatalaga masini
seti_masini -aiga PolarFire -mate MPF100T -saosaoa -1
# RTL files
read_verilog -mode system_verilog project/component/work/txpll0/
txpll0_txpll0_0_PF_TX_PLL.v
faitau_verilog -mode system_verilog {project/component/work/txpll0/txpll0.v}
faitau_verilog -mode system_verilog {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.v}
faitau_verilog -mode system_verilog {project/component/work/xcvr0/xcvr0.v}
faitau_vhdl -mode vhdl_2008 {project/hdl/xcvr1.vhd}
#Vaega SDC files
seti_pito_tulaga {xcvr1}
faitau_sdc -tulaga {project/component/work/txpll0/txpll0_0/
txpll0_txpll0_0_PF_TX_PLL.sdc}
faitau_sdc -vaega {project/component/work/xcvr0/I_XCVR/
xcvr0_I_XCVR_PF_XCVR.sdc}
#Use derive_constraint poloaiga
derive_constraints
#SDC/PDC/NDC i'uga files
write_sdc {project/constraint/xcvr1_derived_constraints.sdc}
write_pdc {project/constraint/fp/xcvr1_derived_constraints.pdc}
9.1.2 seti_masini (Fai se Fesili)
Fa'amatalaga
Fa'ailoa igoa ole aiga, igoa oti, ma le togi saoasaoa.
seti_masini -aiga - oti -saosaoa
finauga

Parameter	Ituaiga	Fa'amatalaga
-aiga	manoa	Fa'ailoa le igoa ole aiga. O fa'atatau e ono iai o PolarFire®, PolarFire SoC.
- oti	manoa	Fa'ailoa le igoa o le oti.
-saosaoa	manoa	Fa'ailoa mai le vasega saosaoa o le masini. O fa'atatau e ono mafai ona iai STD po'o le -1.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0023	Fa'ailoga mana'omia—o lo'o misi	O le filifiliga pe'a e fa'atulafonoina ma e tatau ona fa'amaonia.
ERR0005	Le iloa mate 'MPF30'	E le sa'o le tau o le filifiliga -die. Va'ai le lisi e mafai ona fa'atatau i le fa'amatalaga o filifiliga.
ERR0023	Parameter—ua misi le tau	O le filifiliga mate e faʻamaonia e aunoa ma se tau.
ERR0023	Fa'ailoga mana'omia—e misi le aiga	O le filifiliga a le aiga e fa'atulafonoina ma e tatau ona fa'amaonia.
ERR0004	Le iloa aiga 'PolarFire®'	E le sa'o le filifiliga a le aiga. Va'ai le lisi e mafai ona fa'atatau i le fa'amatalaga o filifiliga.

………… faaauau
Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0023	Parameter—e leai se taua o le aiga	O le filifiliga a le aiga e faʻamaonia e aunoa ma se tau.
ERR0023	Fa'ailoga mana'omia—ua misi le saoasaoa	Ole filifiliga saosaoa e fa'atulafonoina ma e tatau ona fa'amaonia.
ERR0007	Le iloa le saoasaoa ' '	E le sa'o le filifiliga saosaoa. Va'ai le lisi e mafai ona fa'atatau i le fa'amatalaga o filifiliga.
ERR0023	Parameter—o le saoasaoa e misi le tau	O le filifiliga saosaoa ua faʻamaonia e aunoa ma se tau.

Example
seti_meamea -aiga {PolarFire} -mate {MPF300T_ES} -saosaoa -1
seti_masini -aiga SmartFusion 2 -mate M2S090T -saosaoa -1
9.1.3 faitau_verilog (Fai se Fesili)
Fa'amatalaga
Faitau se Verilog file fa'aaoga Verific.
read_verilog [-lib ] [-faiga ]fileigoa>
finauga

Parameter	Ituaiga	Fa'amatalaga
-lib	manoa	Fa'ailoa le faletusi o lo'o i ai modules e fa'aopoopo i totonu o le faletusi.
-tulaga	manoa	Fa'ailoa le tulaga Verilog. O fa'atatauga e ono iai o le verilog_95, verilog_2k, system_verilog_2005, system_verilog_2009, system_verilog, verilog_ams, verilog_psl, system_verilog_mfcu. O fa'atauga e le fa'atatau i mata'itusi. Ole fa'aoga ole verilog_2k.
fileigoa	manoa	Verilog file igoa.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0023	Parameter—lib e misi le tau	O le filifiliga lib ua faʻamaonia e aunoa ma se tau.
ERR0023	Parameter—o le auala e misi le tau	O le auala filifiliga e faʻamaonia e aunoa ma se tau.
ERR0015	Le iloa auala ' '	E le o iloa le faiga o le verilog. Va'ai le lisi o le fa'aogaina o le verilog mode in—mode option description.
ERR0023	Fa'ailoga mana'omia file ua misi le igoa	Leai se verilog file ua saunia le ala.
ERR0016	Ua le manuia ona o le parser a Verific	Syntax sese i verilog file. E mafai ona matauina le parser a Verific i le fa'amafanafanaga i luga a'e o le fe'au sese.
ERR0012	set_device e le o taʻua	E le o fa'amaonia mai le fa'amatalaga o le masini. Fa'aaoga le seti_device poloaiga e fa'amatala ai le masini.

Example
faitau_verilog -mode system_verilog {component/work/top/top.v}
faitau_verilog -mode system_verilog_mfcu design.v
9.1.4 faitau_vhdl (Fai se Fesili)
Fa'amatalaga
Fa'aopoopo se VHDL file i le lisi o le VHDL files.
faitau_vhdl [-lib ] [-faiga ]fileigoa>
finauga

Parameter	Ituaiga	Fa'amatalaga
-lib	—	Fa'ailoa le faletusi e tatau ona fa'aopoopoina ai mea.
-tulaga	—	Fa'amaoti le tulaga VHDL. Ole tulaga ole VHDL_93. O fa'atauga talafeagai o vhdl_93, vhdl_87, vhdl_2k, vhdl_2008, vhdl_psl. O fa'atauga e le fa'atatau i mata'itusi.
fileigoa	—	VHDL file igoa.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0023	Parameter—lib e misi le tau	O le filifiliga lib ua faʻamaonia e aunoa ma se tau.
ERR0023	Parameter—o le auala e misi le tau	O le auala filifiliga e faʻamaonia e aunoa ma se tau.
ERR0018	Le iloa auala ' '	E le o iloa le faiga VHDL. Va'ai le lisi ole VHDL fa'aogaina ile-mode fa'amatalaga filifiliga.
ERR0023	Fa'ailoga mana'omia file ua misi le igoa	Leai VHDL file ua saunia le ala.
ERR0019	Le mafai ona resitala invalid_path.v file	Le VHDL faʻamaonia file e le o iai pe leai ni fa'atagaga faitau.
ERR0012	set_device e le o taʻua	E le o fa'amaonia mai le fa'amatalaga o le masini. Fa'aaoga le seti_device poloaiga e fa'amatala ai le masini.

Example
faitau_vhdl -mode vhdl_2008 osc2dfn.vhd
faitau_vhdl {hdl/top.vhd}
9.1.5 set_top_level (Fai se Fesili)
Fa'amatalaga
Fa'ailoa le igoa ole vaega pito i luga ile RTL.
set_top_level [-lib ]
finauga

Parameter	Ituaiga	Fa'amatalaga
-lib	manoa	Le faletusi e su'e ai le vaega pito i luga po'o le fa'alapotopotoga (filifiliga).
igoa	manoa	Le vaega pito i luga module po'o le igoa fa'alapotopotoga.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0023	O lo'o misi le ta'otoga pito i luga	Ole filifiliga pito i luga e fa'atulafonoina ma e tatau ona fa'amaonia.
ERR0023	Parameter—lib e misi le tau	O le filifiliga lib ua faʻamaonia e aunoa ma ni tau.
ERR0014	Le mafai ona maua le tulaga maualuga i le faletusi	O le vaega pito i luga ua fa'amaonia e le o fa'amalamalamaina i le faletusi ua tu'uina atu. Ina ia foia lenei mea sese, e tatau ona faasa'o le igoa pito i luga po'o le faletusi.
ERR0017	Ua le manuia le auiliiliina	Sese ile faiga ole fa'amalamalamaga ole RTL. E mafai ona matauina le savali sese mai le faʻamafanafanaga.

Example
seti_pito_tulaga {pito}
set_top_level -lib hdl pito i luga
9.1.6 read_sdc (Fai se Fesili)
Fa'amatalaga
Faitau se SDC file i totonu o le vaega fa'amaumauga.
faitau_sdc -vaegafileigoa>
finauga

Parameter	Ituaiga	Fa'amatalaga
-vaega	—	Ole fu'a fa'atulafonoina lea mo le read_sdc fa'atonuga pe a tatou maua fa'agata.
fileigoa	manoa	Auala i le SDC file.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0023	Fa'ailoga mana'omia file ua misi le igoa.	Ole filifiliga fa'atulafonoina file e le o ta'u maia le igoa.
ERR0000	SDC file <file_path> e le mafai ona faitau.	Le SDC fa'amaonia file e leai ni fa'atagaga faitau.
ERR0001	Le mafai ona tatalafile_ala> file.	O le SDC file e le o iai. E tatau ona faasa'o le ala.
ERR0008	Ua misi le seti_component poloaiga i totonufile_ala> file	Le vaega faʻamaonia o le SDC file e le o faʻamaonia le vaega.

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0009	<List of errors from sdc file>	O le SDC file o lo'o i ai tulafono sdc sese. Mo example, pe a i ai se mea sese i set_multicycle_path faʻalavelave: Sese aʻo faʻatinoina le poloaiga read_sdc: ifile_ala> file: Sese ile fa'atonuga set_multicycle_path: Fa'ailoga le iloa [get_cells {reg_a}].

Example
read_sdc -component {./component/work/ccc0/ccc0_0/ccc0_ccc0_0_PF_CCC.sdc}
9.1.7 read_ndc (Fai se Fesili)
Fa'amatalaga
Faitau se NDC file i totonu o le vaega fa'amaumauga.
faitau_ndc -vaegafileigoa>
finauga

Parameter	Ituaiga	Fa'amatalaga
-vaega	—	Ole fu'a fa'atulafonoina lea mo le read_ndc fa'atonuga pe a tatou maua fa'agata.
fileigoa	manoa	Auala i le NDC file.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0001	Le mafai ona tatalafile_ala> file	O le NDC file e le o iai. E tatau ona faasa'o le ala.
ERR0023	Fa'ailoga mana'omia—AtclParamO_ o lo'o misi.	Ole filifiliga fa'atulafonoina filee le o ta'u maia le igoa.
ERR0023	Fa'ailoga mana'omia—e misi le vaega.	O le filifiliga vaega e fa'atulafonoina ma e tatau ona fa'amaonia.
ERR0000	NDC file 'file_path>' e le mafai ona faitau.	O le NDC faʻamaonia file e leai ni fa'atagaga faitau.

Example
faitau_ndc -tulaga {component/work/ccc1/ccc1_0/ccc_comp.ndc}
9.1.8 derive_constraints (Fai se Fesili)
Fa'amatalaga
SDC vaega vave files i totonu o le faʻamaumauga tuʻufaʻatasia mamanu.
derive_constraints
finauga

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0013	E le fa'amalamalamaina le tulaga maualuga	O lona uiga e le o fa'amaoti mai le vaega pito i luga po'o le fa'alapotopotoga. Ina ia faaleleia lenei valaau, tuuina atu le seti_top_level poloaiga a'o le'i faia le poloaiga derive_constraints.

Example
derive_constraints
9.1.9 write_sdc (Fai se Fesili)
Fa'amatalaga
Tusia se tapulaa file i le SDC faatulagaga.
tusi_sdcfileigoa>
finauga

Parameter	Ituaiga	Fa'amatalaga
<fileigoa>	manoa	Auala i le SDC file o le a gaosia. Ole filifiliga fa'atulafonoina lea. Afai o le file o lo'o i ai, o le a suia.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0003	Le mafai ona tatalafile ala> file.	File e le sa'o le ala. Siaki pe iai fa'amaumauga matua.
ERR0002	SDC file 'file ala>' e le mafai ona tusia.	Le SDC fa'amaonia file e leai se fa'atagaga tusitusi.
ERR0023	Fa'ailoga mana'omia file ua misi le igoa.	O le SDC file ala o se filifiliga faʻamalosia ma e tatau ona faʻamaonia.

Example
write_sdc “derived.sdc”
9.1.10 write_pdc (Fai se Fesili)
Fa'amatalaga
Tusia tapula'a fa'aletino (Na'o Fa'agata).
tusi_pdcfileigoa>
finauga

Parameter	Ituaiga	Fa'amatalaga
<fileigoa>	manoa	Auala i le PDC file o le a gaosia. Ole filifiliga fa'atulafonoina lea. Afai o le file o lo'o i ai le ala, o le a suia.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0003	Le mafai ona tatalafile ala> file	O le file e le sa'o le ala. Siaki pe iai fa'amaumauga matua.
ERR0002	PDC file 'file ala>' e le mafai ona tusia.	Le PDC faʻamaonia file e leai se fa'atagaga tusitusi.
ERR0023	Fa'ailoga mana'omia file ua misi le igoa	Le PDC file ala o se filifiliga faʻamalosia ma e tatau ona faʻamaonia.

Example
write_pdc “derived.pdc”
9.1.11 write_ndc (Fai se Fesili)
Fa'amatalaga
Tusia tapulaa NDC i le a file.
tusi_ndcfileigoa>
finauga

Parameter	Ituaiga	Fa'amatalaga
fileigoa	manoa	Auala i le NDC file o le a gaosia. Ole filifiliga fa'atulafonoina lea. Afai o le file o lo'o i ai, o le a suia.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0003	Le mafai ona tatalafile_ala> file.	File e le sa'o le ala. E le o iai fa'amaumauga a matua.
ERR0002	NDC file 'file_path>' e le mafai ona tusia.	O le NDC faʻamaonia file e leai se fa'atagaga tusitusi.
ERR0023	O lo'o misi le tapula'a mana'omia _AtclParamO_.	O le NDC file ala o se filifiliga faʻamalosia ma e tatau ona faʻamaonia.

Example
write_ndc “derived.ndc”
9.1.12 add_include_path (Fai se Fesili)
Fa'amatalaga
Fa'amaoti se ala e su'e ai e aofia ai files pe a faitau RTL files.
add_include_path
finauga

Parameter	Ituaiga	Fa'amatalaga
fa'atonuga	manoa	Fa'amaoti se ala e su'e ai e aofia ai files pe a faitau RTL files. O lenei filifiliga e fa'amalosia.

Fa'afo'i Ituaiga	Fa'amatalaga
0	Na manuia le poloaiga.

Fa'afo'i Ituaiga	Fa'amatalaga
1	Ua le manuia le poloaiga. E iai se mea sese. E mafai ona e matauina le savali sese i le faʻamafanafanaga.

Lisi o Mea Sese

Fa'ailoga sese	Feau Sese	Fa'amatalaga
ERR0023	Fa'ailoga mana'omia e aofia ai le ala o lo'o misi.	O le filifiliga fa'atonu e fa'atulafonoina ma e tatau ona tu'uina atu.

Manatua: Afai e le sa'o le ala fa'atonu, ona pasia lea o le add_include_path e aunoa ma se mea sese.
Ae ui i lea, read_verilog/read_vhd poloaiga o le a le manuia ona o le Verific's parser.
Example
add_include_path component/work/COREABC0/COREABC0_0/rtl/vlog/core

Toe Iloilo Tala'aga (Fai se Fesili)

O le tala fa'asolopito o lo'o fa'amatalaina suiga na fa'atinoina i le pepa. O suiga o lo'o lisiina e ala i toe iloiloga, amata i le lomiga aupito lata mai.

Toe Iloiloga	Aso	Fa'amatalaga
F	08/2024	O suiga nei ua faia i lenei toe iloiloga: • Fa'afou vaega Fa'aopoopo B—Auina mai Faletusi Fa'ata'ita'i ile Si'osi'omaga Fa'ata'ita'iga.
E	08/2024	O suiga nei ua faia i lenei toe iloiloga: • Fa'afou vaega Ovaview. • Fa'afouina le vaega Fa'asolo mai SDC File. • Fa'afou vaega Fa'aopoopo B—Auina mai Faletusi Fa'ata'ita'i ile Si'osi'omaga Fa'ata'ita'iga.
D	02/2024	O lenei pepa o loʻo tuʻuina atu i le Libero 2024.1 SoC Design Suite e aunoa ma ni suiga mai le v2023.2. Fa'afou vaega Galulue ma derive_constraints Utility
C	08/2023	O lenei pepa o loʻo tuʻuina atu i le Libero 2023.2 SoC Design Suite e aunoa ma ni suiga mai le v2023.1.
B	04/2023	O lenei pepa o loʻo tuʻuina atu i le Libero 2023.1 SoC Design Suite e aunoa ma ni suiga mai le v2022.3.
A	12/2022	Toe Iloiloga Muamua.

Microchip FPGA Lagolago
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Fa'afeso'ota'i le Nofoaga Autu Lagolago Fa'apitoa e ala ile webnofoaga i www.microchip.com/support. Ta'u le numera o le Vaega o Meafaigaluega FPGA, filifili le vaega o mataupu talafeagai, ma fa'apipi'i le mamanu files a'o faia se mataupu lagolago fa'apitoa.
Fa'afeso'ota'i Auaunaga Fa'atau mo le lagolago o oloa e le fa'apitoa, e pei o le tau o oloa, fa'aleleia o oloa, fa'afouga fa'amatalaga, tulaga oka, ma le fa'atagaina.

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Microchip Fa'amatalaga
Le Microchip Webnofoaga
Microchip e maua le lagolago i luga ole laiga e ala i la matou webnofoaga i www.microchip.com/. Lenei web'upega tafa'ilagi e fa'aoga e fai ai files ma fa'amatalaga faigofie ona maua e tagata fa'atau. O nisi o mea e maua e aofia ai:

• Lagolago oloa - Pepa faʻamatalaga ma mea sese, faʻamatalaga talosaga ma samppolokalame, punaoa mamanu, ta'iala a le tagata fa'aoga ma pepa lagolago mo meafaigaluega, fa'asalalauga fou fa'akomepiuta ma polokalama fa'amaumauga
• Lagolago Faʻatekinisi Lautele - Fesili e masani ona fesiligia (FAQs), talosaga lagolago faʻapitoa, faʻasalalauga i luga ole laiga, Microchip design partner programme list
• Pisinisi o Microchip - Faʻatau oloa ma taʻiala faʻatonu, faʻasalalauga lata mai a Microchip, lisi o semina ma mea na tutupu, lisi o ofisa faʻatau Microchip, tufatufaina ma sui fale gaosimea

Au'aunaga Fa'asilasilaga Suiga o Mea
O le auaunaga fa'asilasilaga suiga o oloa a Microchip e fesoasoani e fa'amautu ai tagata fa'atau i oloa Microchip. O le a maua e le au fai saofaga le faʻamatalaga imeli i soʻo se taimi e iai suiga, faʻafouga, toe teuteuga poʻo mea sese e fesoʻotaʻi ma se aiga o oloa faʻapitoa poʻo meafaigaluega atinaʻe e fiafia i ai. Ina ia lesitala, alu i www.microchip.com/pcn ma mulimuli i faatonuga o le resitalaina.

Lagolago Tagata Fa'atau
O tagata fa'aoga o oloa Microchip e mafai ona maua fesoasoani e ala i le tele o auala:

• Fa'asoa po'o le Sui
• Ofisa Fa'atauga Fa'alotoifale
• Embedded Solutions Engineer (ESE)
• Lagolago Fa'atekinisi

E tatau i tagata fa'atau ona fa'afeso'ota'i le latou tufatufaina, sui po'o le ESE mo le lagolago. O loʻo avanoa foʻi ofisa faʻatau i le lotoifale e fesoasoani i tagata faʻatau. O se lisi o ofisa fa'atau ma nofoaga o lo'o aofia i totonu o lenei pepa. E maua le lagolago fa'apitoa e ala ile webnofoaga i: www.microchip.com/support
Fa'ailoga Puipuiga o Fa'ailoga Fa'atonu a Microchip
Manatua faʻamatalaga o loʻo i lalo o le faʻaogaina o le puipuiga o tulafono i luga o oloa Microchip:

• O oloa Microchip e fetaui ma faʻamatalaga o loʻo i totonu o la latou Pepa Faʻamatalaga Microchip.
• E talitonu Microchip o lona aiga o oloa e saogalemu pe a faʻaaogaina i le auala faʻamoemoeina, i totonu o faʻamatalaga faʻaogaina, ma i lalo o tulaga masani.
• Microchip fa'atauaina ma puipuia fa'amalosi ana aia tatau tau meatotino. O taumafaiga e soli le tulafono o le puipuiga o le oloa Microchip e matua fa'asaina ma e ono solia ai le Digital Millennium Copyright Act.
• E le mafai e le Microchip poʻo se isi mea gaosi semiconductor ona faʻamaonia le saogalemu o lana tulafono. O le puipuiga o tulafono laiti e le o lona uiga tatou te faʻamautinoa o le oloa e "le mafai ona motusia". O le puipuiga o tulafono laiti o lo'o fa'asolosolo pea. Microchip ua tuuto atu i le faʻaauauina pea o le faʻaleleia atili o uiga puipuia o tulafono a tatou oloa.

Faasilasilaga Faaletulafono
O lenei lomiga ma faʻamatalaga o loʻo i totonu e mafai ona faʻaaogaina naʻo oloa Microchip, e aofia ai le mamanu, suʻega, ma tuʻufaʻatasia oloa Microchip ma lau talosaga. O le fa'aogaina o nei fa'amatalaga i so'o se isi lava faiga e solia ai nei aiaiga. O fa'amatalaga e uiga i le fa'aogaina o masini e tu'uina atu mo na'o lou fa'amalieina ma e ono suia i fa'afouga. O lau matafaioi le faʻamautinoa o lau talosaga e fetaui ma au faʻamatalaga. Fa'afeso'ota'i lou ofisa fa'atau Microchip fa'apitonu'u mo se lagolago fa'aopoopo pe, maua se lagolago fa'aopoopo ile www.microchip.com/en-us/support/design-help/client-support-services.
O LENEI FAʻAMATALAGA E TUUINA E MICROCHIP "AS IS". E LEAI FAIA E LE MICROCHIP ni sui po'o so'o se ituaiga pe fa'aalia pe fa'amata'u, tu'utusi pe tu'ugutu, fa'aletulafono po'o se isi mea, e feso'ota'i ma fa'amatalaga e aofia ai ae le tapula'a i so'o se fa'amaoniaga fa'amaonia, fa'amaonia, ma fa'atauga FAASOLOGA E FAI I ONA TULAGA, TULAGA, POO LE FAIGALUEGA. E LEAI SE MEA E TATAU AI MICROCHIP MO SO'O SE FA'AMATALAGA, FA'AMATALAGA, FA'ASA'OGA, FA'AMATALAGA, PO'O LE FA'A'ALI'AGA MA'U'U, FA'AFIA, TAU, PO'O LE TU'U'UINA O SO'O SE I'UGA SO'O SE FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA, PE'O LE MEA NA FA'AUPUNA'I, E tusa lava pe fa'aletonu. FA'AFIO PO'O LE FA'AFIA E MAFAI ILOA. I LE AGATOGA FA'AALIGA E LE TULAFONO, O LE UMA AOFA'IGA A MICROCHIP I TOTOGI UMA I SO'O SE AUALA E FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA E LE'A LOLOA I LE TOTOGI O TOTOGI, AFAI E IAI, NA E TOTOGI SA'O I LE MICROCHIP MO LE FA'AMATALAGA.
O le fa'aogaina o masini Microchip i le tausiga o le ola ma/po'o le saogalemu o lo'o i le tulaga lamatia o le tagata fa'atau, ma e malie le tagata fa'atau e puipuia, fa'aleaga ma taofia Microchip le afaina mai so'o se mea leaga, tagi, suti, po'o tupe alu e mafua mai i lea fa'aoga. E leai ni laisene e tu'uina atu, fa'aalia po'o se isi mea, i lalo o so'o se Microchip aia tatau tau le atamai se'i vagana ua ta'ua.
Fa'ailoga Fa'ailoga
Le igoa Microchip ma le logo, le Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ma XMEGA o fa'ailoga fa'amaufa'ailoga a Microchip Technology Incorporated i Amerika ma isi atunu'u.
AgileSwitch, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed ​​Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, TimeCesium, TimeHub, TimePictra, TimeProvider, ma ZL o faʻailoga resitalaina o Microchip Technology Incorporated i Amerika.
Taofi Fa'aigoa Fa'atasi, AKS, Analog-mo-le-Digital Age, So'o se Capacitor, So'o se In, So'o'Out, Suiga Fa'aopoopo, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net Matching, Dynamic Average Matching , DAM, ECAN, Espresso T1S, EtherGREEN, EyeOpen, GridTime, IdealBridge, IGaT, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Parallel, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, MarginLink, maxC maualugaView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Faʻamaonia logo, MPLIB, MPLINK, mSiC, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, Power MOS IV, Power MOS 7, PowerSmart, PureSilicon , QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Aofa'i Tumau , Taimi Fa'atuatuaina, TSHARC, Turing, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ma ZENA o fa'ailoga fa'ailoga a Microchip Technology Incorporated i Amerika ma isi atunu'u.
SQTP ose fa'ailoga tautua a Microchip Technology Incorporated i Amerika
O le logo Adaptec, Frequency on Demand, Silicon Storage Technology, ma Symmcom o fa'ailoga fa'amaufa'ailoga a Microchip Technology Inc. i isi atunu'u.
GestIC ose fa'ailoga fa'amaufa'ailoga a Microchip Technology Germany II GmbH & Co. KG, ose lala o Microchip Technology Inc., i isi atunu'u.
O isi fa'ailoga tau fefa'ataua'iga uma o lo'o ta'ua ii o meatotino a latou kamupani.
2024, Microchip Technology Incorporated ma ona lala. Ua Taofia Aia Tatau Uma.
ISBN: 978-1-6683-0183-8
Faiga Fa'atonuga
Mo faʻamatalaga e uiga i Microchip's Quality Management Systems, faʻamolemole asiasi www.microchip.com/quality.
Fa'atauga ma Au'aunaga i le Lalolagi Atoa

AMERIKA	ASIA/ PASIFIK	ASIA/ PASIFIK	Europa
Ofisa Autasi 2355 Sisifo Chandler Blvd. Chandler, AZ 85224-6199 Telefoni: 480-792-7200 Fax: 480-792-7277 Lagolago Fa'atekinisi: www.microchip.com/support Web tuatusi: www.microchip.com Atlanta Duluth, GA Telefoni: 678-957-9614 Fax: 678-957-1455 Austin, TX Telefoni: 512-257-3370 Boston Westborough, MA Telefoni: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Telefoni: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Telefoni: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Telefoni: 248-848-4000 Houston, TX Telefoni: 281-894-5983 Indianapolis Noblesville, IN Telefoni: 317-773-8323 Fax: 317-773-5453 Telefoni: 317-536-2380 Los Angeles Misiona Viejo, CA Telefoni: 949-462-9523 Fax: 949-462-9608 Telefoni: 951-273-7800 Raleigh, NC Telefoni: 919-844-7510 Niu Ioka, NY Telefoni: 631-435-6000 San Jose, CA Telefoni: 408-735-9110 Telefoni: 408-436-4270 Kanata - Toronto Telefoni: 905-695-1980 Fax: 905-695-2078	Ausetalia – Sini Telefoni: 61-2-9868-6733 Saina - Beijing Telefoni: 86-10-8569-7000 Saina – Chengdu Telefoni: 86-28-8665-5511 Saina – Chongqing Telefoni: 86-23-8980-9588 Saina – Dongguan Telefoni: 86-769-8702-9880 Saina – Guangzhou Telefoni: 86-20-8755-8029 Saina – Hangzhou Telefoni: 86-571-8792-8115 Saina - Hong Kong SAR Telefoni: 852-2943-5100 Saina – Nanjing Telefoni: 86-25-8473-2460 Saina – Qingdao Telefoni: 86-532-8502-7355 Saina – Shanghai Telefoni: 86-21-3326-8000 Saina – Shenyang Telefoni: 86-24-2334-2829 Saina – Shenzhen Telefoni: 86-755-8864-2200 Saina – Suzhou Telefoni: 86-186-6233-1526 Saina - Wuhan Telefoni: 86-27-5980-5300 Saina – Xian Telefoni: 86-29-8833-7252 Saina – Xiamen Telefoni: 86-592-2388138 Saina – Zhuhai Telefoni: 86-756-3210040	Initia – Bangalore Telefoni: 91-80-3090-4444 Initia – New Delhi Telefoni: 91-11-4160-8631 Initia - Pune Telefoni: 91-20-4121-0141 Iapani - Osaka Telefoni: 81-6-6152-7160 Iapani - Tokyo Telefoni: 81-3-6880-3770 Korea – Daegu Telefoni: 82-53-744-4301 Korea – Seoul Telefoni: 82-2-554-7200 Meleisia – Kuala Lumpur Telefoni: 60-3-7651-7906 Meleisia – Penang Telefoni: 60-4-227-8870 Filipaina – Manila Telefoni: 63-2-634-9065 Singapore Telefoni: 65-6334-8870 Taiuani – Hsin Chu Telefoni: 886-3-577-8366 Taiuani – Kaohsiung Telefoni: 886-7-213-7830 Taiuani – Taipei Telefoni: 886-2-2508-8600 Taialani – Bangkok Telefoni: 66-2-694-1351 Vietnam – Ho Chi Minh Telefoni: 84-28-5448-2100	Ausetalia – Uelese Telefoni: 43-7242-2244-39 Fax: 43-7242-2244-393 Tenimaka – Copenhagen Telefoni: 45-4485-5910 Fax: 45-4485-2829 Finelani – Espoo Telefoni: 358-9-4520-820 Farani – Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Siamani – Garching Telefoni: 49-8931-9700 Siamani – Haan Telefoni: 49-2129-3766400 Siamani – Heilbronn Telefoni: 49-7131-72400 Siamani – Karlsruhe Telefoni: 49-721-625370 Siamani – Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Siamani – Rosenheim Telefoni: 49-8031-354-560 Isaraelu – Hod Hasaron Telefoni: 972-9-775-5100 Italia – Milan Telefoni: 39-0331-742611 Fax: 39-0331-466781 Italia – Padova Telefoni: 39-049-7625286 Netherlands – Drunen Telefoni: 31-416-690399 Fax: 31-416-690340 Nouei – Trondheim Telefoni: 47-72884388 Polani – Warsaw Telefoni: 48-22-3325737 Romania – Bucharest Tel: 40-21-407-87-50 Sepania - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Suetena – Gothenberg Tel: 46-31-704-60-40 Suetena - Stockholm Telefoni: 46-8-5090-4654 Peretania - Wokingham Telefoni: 44-118-921-5800 Fax: 44-118-921-5820

Pepa / Punaoa

MICROCHIP DS00004807F PolarFire Aiga FPGA Fa'asologa Fa'apitoa [pdf] Taiala mo Tagata Fa'aoga DS00004807F PolarFire Aiga FPGA Fa'asinomaga Fa'aleaganu'u, DS00004807F, PolarFire Aiga FPGA Fa'aleaganu'u Fa'asolo, Aiga FPGA Fa'asinomaga Fa'asinomaga, Fa'asologa Fa'asinomaga, Fa'asolo

Fa'asinomaga

• Tusi Taiala