ALTERA Arria 10 Arabara Memory Cube Adarí Design Eksample

Arabara Memory Cube Adarí Design Example Itọsọna olumulo pese alaye lori apẹrẹ ati lilo ti HMC Adarí hardware oniru example. Itọsọna naa jẹ imudojuiwọn fun Quartus Prime Design Suite 16.0 ati pe o jẹ imudojuiwọn kẹhin ni May 2, 2016.
Apẹrẹ ExampItọsọna Ibẹrẹ Iyara n pese awọn ilana igbesẹ-nipasẹ-igbesẹ fun iṣakojọpọ, simulating, ti ipilẹṣẹ, ati idanwo apẹrẹ Alakoso HMC tẹlẹample. Tọkasi olusin 1-1 fun ipariview ti awọn igbesẹ idagbasoke.

Apẹrẹ Example Apejuwe

Awọn HMC Adarí hardware oniru example pẹlu ọpọlọpọ awọn paati gẹgẹbi Board Arria 10 Device, HMC Adarí IP Core, Agogo & Tun TX PLLs, Data Ibeere Ibere ​​Generator ati Idahun Atẹle, TX/TX FIFO MAC, RX MAC, Idanwo Avalon-MM Iṣakoso ati LED, Adarí Ipo Interface , Avalon-MM I 2C Master, Initialization State Machine, TX Lane Swapper, Transceiver x16, RX Lane Swapper, Arria 10 Transceiver Reconfiguration Interface, ati HMC Device. Awọn exampapẹrẹ le nilo awọn eto kan pato lati ṣiṣẹ daradara lori Apo Idagbasoke Arria 10 GX FPGA pẹlu kaadi ọmọbinrin HMC.

Alaye ni Afikun

Awọn Afikun Alaye apakan pese awọn alaye lori awọn liana be fun awọn ti ipilẹṣẹ oniru example, itan atunyẹwo ti itọsọna olumulo, awọn apejọ kikọ ti a lo ninu itọsọna naa, ati bii o ṣe le kan si Intel fun atilẹyin.

Awọn ilana Lilo ọja

Tẹle awọn ilana ti o wa ni isalẹ lati lo apẹrẹ hardware Adarí HMC example:

1. Ṣe akopọ apẹrẹ example lilo a labeabo
2. Ṣe kikopa iṣẹ-ṣiṣe
3. Ṣe ina apẹrẹ example
4. Ṣe akopọ apẹrẹ example lilo kuotisi NOMBA
5. Ṣe idanwo apẹrẹ hardware

Akiyesi pe awọn hardware iṣeto ni ati igbeyewo files fun apẹrẹ example wa ni / example_design / Nhi, nigba ti kikopa files wa ni / example_design / SIM.

Lati ṣe iranlọwọ fun ọ lati loye bii o ṣe le lo Adari Memory Cube IP mojuto arabara, mojuto ṣe ẹya testbench simulatable ati aṣa apẹrẹ ohun elo kan.ample ti o atilẹyin akopo ati hardware igbeyewo. Nigbati o ba ṣe ina apẹrẹ example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware. O le ṣe igbasilẹ apẹrẹ akojọpọ si Intel® Arria® 10 GX FPGA Apo Idagbasoke.

Alaye ti o jọmọ
Arabara Memory onigun Adarí IP mojuto User Itọsọna

Apẹrẹ Example Directory Be

Awọn hardware iṣeto ni ati igbeyewo files (apẹrẹ hardware example) wa ninuample_ design_install_dir>/ example_design/par. Simulation naa files (testbench fun kikopa nikan) wa ninuample_design_install_dir>/ example_design / SIM.

Apẹrẹ Example irinše

Awọn HMC Adarí hardware oniru example pẹlu awọn eroja wọnyi:

• HMC Adarí IP mojuto pẹlu CDR aago itọkasi ṣeto si 125 MHz ati pẹlu aiyipada RX ìyàwòrán ati TX eto.
  Akiyesi: Apẹrẹ example nilo awọn eto wọnyi lati ṣiṣẹ daradara lori Apo Idagbasoke Arria 10 GX FPGA pẹlu kaadi ọmọbinrin HMC.
• Onibara kannaa ti o ipoidojuko siseto ti IP mojuto, ati soso iran ati yiyewo.
• JTAG oludari ti o ibasọrọ pẹlu Altera System Console. O ṣe ibasọrọ pẹlu ọgbọn alabara nipasẹ ẹrọ Console System.

Awọn akojọ bọtini files ti o muse example testbench.

/src/hmcc_example.sv	Oke-ipele hardware oniru example file.
/sim/hmcc_tb.sv	Ipele oke file fun kikopa.
Awọn iwe afọwọkọ Testbench Akiyesi: Lo Ṣiṣe ti a pesefile lati ṣe ina awọn iwe afọwọkọ wọnyi.
/sim/run_vsim.do	Iwe afọwọkọ ModelSim lati ṣiṣe testbench.
/sim/run_vcs.sh	Awọn Synopsys VCS iwe afọwọkọ lati ṣiṣe awọn testbench.
/sim/run_ncsim.sh	Iwe afọwọkọ Cadence NCSim lati ṣiṣẹ testbench.

Ti o npese awọn Design Example

Nọmba 1-5: Example Design Tab ni arabara Memory kuubu Adarí paramita Olootu

Tẹle awọn igbesẹ wọnyi lati ṣe agbejade apẹrẹ ohun elo Arria 10 example ati testbench:

1. Ninu Katalogi IP (Awọn irinṣẹ> Katalogi IP), yan idile ẹrọ afojusun Arria 10.
2. Ninu Katalogi IP, wa ko si yan Adarí Arabara Memory Cube. Ferese Iyipada IP Tuntun yoo han.
3. Pato orukọ ipele-oke fun iyatọ IP aṣa rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .qsys.
4. O gbọdọ yan ohun elo Arria 10 kan pato ni aaye Ẹrọ, tabi tọju ẹrọ aiyipada ti Quartus Prime sọfitiwia yan.
5. Tẹ O DARA. Olootu paramita IP yoo han.
6. Lori IP taabu, pato awọn paramita fun iyatọ ipilẹ IP rẹ.
7. Lori Examptaabu Oniru, yan awọn eto wọnyi fun apẹrẹ example:
   1. Fun Yan Oniru, yan aṣayan Igbimọ Ọmọbinrin HMCC.
   2. Fun Example Apẹrẹ Files, yan aṣayan Simulation lati ṣe ina testbench, ki o yan aṣayan Synthesis lati ṣe ipilẹṣẹ apẹrẹ ohun elo example.
   3. Fun Ọna kika HDL ti ipilẹṣẹ, Verilog nikan wa.
   4. Fun Apo Idagbasoke Àkọlé yan Arria 10 GX FPGA Apo Idagbasoke (Silicon Production).
      Akiyesi: Nigbati o ba yan yi kit, awọn hardware oniru example ìkọlélórí rẹ ti tẹlẹ ẹrọ aṣayan pẹlu awọn ẹrọ lori afojusun ọkọ. Nigbati o ba ṣe ina apẹrẹ example, Intel Quartus Prime software ṣẹda Intel
      Iṣẹ akanṣe Quartus Prime, eto, ati awọn iṣẹ iyansilẹ pin fun igbimọ ti o yan. Ti o ko ba fẹ ki sọfitiwia naa fojusi igbimọ kan pato, yan Ko si.
8. Tẹ Ina Example Design bọtini

Agbọye Testbench

Altera pese ohun oniru Mofiample pẹlu HMC Adarí IP mojuto. Apẹrẹ example wa mejeeji fun kikopa ti ipilẹ IP rẹ ati fun akopọ. Apẹrẹ example ni awọn iṣẹ kikopa bi HMC Adarí IP mojuto testbench.
Ti o ba tẹ ina ExampApẹrẹ ninu oluṣakoso paramita HMC Adarí, sọfitiwia Quartus Prime ṣe ipilẹṣẹ testbench ifihan kan. Olootu paramita ta ọ fun ipo ti o fẹ ti testbench.
Lati ṣe simulate testbench, o gbọdọ pese awoṣe iṣẹ-ọkọ akero HMC tirẹ (BFM). Altera ṣe idanwo apẹrẹ example testbench pẹlu Micron arabara Memory kuubu BFM. Testbench ko pẹlu ohun I2C titunto si module, nitori Micron HMC BFM ko ni atilẹyin ati ki o ko nilo iṣeto ni nipa ohun I2C module.
Ni iṣeṣiro, testbench n ṣakoso TX PLL kan ati awọn atọkun ọna data lati ṣe awọn iṣe atẹle wọnyi:

1. Ṣe atunto HMC BFM pẹlu HMC Adarí IP mojuto oṣuwọn data ati iwọn ikanni, ni Idahun Ṣiṣii Ipo Idahun.
2. Ṣeto ọna asopọ laarin BFM ati IP mojuto.
3. Ṣe itọsọna ọkọọkan awọn ebute oko oju omi mẹrin IP mojuto lati kọ awọn apo-iwe mẹrin ti data si BFM.
4. Dari awọn IP mojuto lati ka pada awọn data lati BFM.
5. Ṣayẹwo pe data kika ni ibamu pẹlu data kikọ.
6. Ti data ba baamu, ṣafihan TEST_PASSED.

Simulating awọn Oniru Example Testbench
Nọmba 1-6: Ilana

Tẹle awọn igbesẹ wọnyi lati ṣe adaṣe testbench:

1. Ni laini aṣẹ, yipada siample>/ SIM liana.
2. Tẹ awọn iwe afọwọkọ.
3. Tẹ ọkan ninu awọn aṣẹ wọnyi, da lori ẹrọ simulator rẹ:
4. Si view esi simulation:
   1. Nigbati o ba ṣiṣẹ testbench ni eyikeyi awọn simulators mẹta ti o ni atilẹyin, iwe afọwọkọ naa ṣe ilana ti testbench ati ṣe igbasilẹ iṣẹ simulator niample liana>/ example_ design/sim/ .log. jẹ "vsim", "ncsim", tabi "vcs".
   2. Nigbati o ba ṣiṣe awọn testbench ni eyikeyi ninu awọn mẹta atilẹyin simulators, awọn iwe afọwọkọ ina kan waveform file. O le ṣiṣe aṣẹ ṣiṣe _gui lati gbe fọọmu igbi ni fọọmu igbi kan pato simulator viewer.
      Si view awọn igbi fọọmu file ninu ẹrọ simulator rẹ, tẹ ọkan ninu awọn aṣẹ wọnyi:

      Simulator License Mentor Graphics ModelSim	Laini aṣẹ ṣe vsim_gui	Fọọmu igbi File <design example liana>/ Example_design / SIM / olutojueni / hmcc_wf.wlf
      Synopsys Awari Visual Ayika	ṣe vcs_gui	<design example liana>/ Example_design / SIM / hmcc_wf.vpd
      Cadence SimVision Waveform	ṣe ncsim_gui	<design example liana>/ Example_design / SIM / cadence / hmcc_wf.shm
5. Ṣe itupalẹ awọn abajade. Aṣeyọri testbench firanṣẹ ati gba awọn apo-iwe mẹwa fun ibudo kan, ati ṣafihan Test_PASSED”

Eto soke Board

Ṣeto awọn ọkọ lati ṣiṣe awọn hardware oniru example.
Akiyesi: Rii daju pe agbara wa ni pipa ṣaaju ki o to yi eto eyikeyi pada.

1. Ṣeto awọn iyipada DIP lori kaadi ọmọbirin bi atẹle:
2. Ṣeto DIP yipada SW1 lati tọka ID cube 0:
   

   Yipada	Išẹ	Eto
   1	CUB[0]	Ṣii
   2	CUB[1]	Ṣii
   3	CUB[2]	Ṣii
   4	—	Maṣe Ṣọra

Ṣeto DIP yipada SW2 lati pato awọn eto aago:

Yipada	Išẹ	Eto
1	CLK1_FSEL0	Ṣii (125 MHz)
2	CLK1_FSEL1	Ṣii (125 MHz)
3	CLK1_SEL	Ṣii (Crystal)
4	—	Maṣe Ṣọra

• So kaadi ọmọbinrin HMC pọ si Arria 10 FPGA Development Kit nipa lilo awọn asopọ J8 ati J10 kaadi ọmọbinrin.
• Ṣeto awọn jumpers lori Arria 10 GX FPGA Apo Idagbasoke:
• Ṣafikun awọn shunts si J8 jumper lati yan 1.5 V gẹgẹbi eto VCCIO fun asopo FMC B.
• Ṣafikun awọn shunts si jumper J11 lati yan 1.8 V gẹgẹbi eto VCCIO fun asopo FMC A.

Iṣakojọpọ ati Idanwo Oniru Example ni Hardware

Lati ṣajọ ati ṣiṣe idanwo ifihan kan lori apẹrẹ hardware example, tẹle awọn igbesẹ

1. Rii daju hardware oniru example iran jẹ pari.
2. Ninu sọfitiwia Quartus Prime, ṣii iṣẹ akanṣe Quartus Primeample_design_install_dir> / example_design/par/hmcc_example.qpf.
3. Ninu Dasibodu Iṣakojọpọ, tẹ Apẹrẹ Iṣakojọ (Intel Quartus Prime Pro Edition) tabi yan Ṣiṣe> Ibẹrẹ Iṣakojọpọ (Intel Quartus Prime Standard Edition).
4. Lẹhin ti o ṣe ina .sof, tẹle awọn igbesẹ wọnyi lati ṣe eto apẹrẹ ohun elo example lori ẹrọ Arria 10:
   1. Yan Awọn irinṣẹ> Oluṣeto ẹrọ.
   2. Ni awọn Programmer, tẹ Hardware Setup.
   3. Yan ẹrọ siseto.
   4. Yan ati ṣafikun Apo Idagbasoke Arria 10 GX FPGA si eyiti igba Quartus Prime le sopọ si.
   5. Rii daju pe Ipo ti ṣeto si JTAG.
   6. Tẹ Ṣawari Aifọwọyi ki o yan ẹrọ eyikeyi.
   7. Tẹ lẹẹmeji ẹrọ Arria 10.
   8. Ṣii .sof inample_design_install_dir>/ example_design/par/jade_ files,
      Akiyesi: Sọfitiwia Quartus Prime yi ẹrọ pada si ọkan ninu .sof.
   9. Ni ila pẹlu .sof rẹ, ṣayẹwo apoti ti o wa ninu iwe Eto / Tunto.
   10. Tẹ Bẹrẹ.
   11. Lẹhin ti awọn software tunto awọn ẹrọ pẹlu hardware oniru example, ṣe akiyesi awọn LED ọkọ:
       1. LED pupa ti n paju n tọka si apẹrẹ ti nṣiṣẹ.
       2. Awọn LED alawọ ewe meji nitosi LED ti n paju pupa n tọka si pe ọna asopọ HMC ti wa ni ibẹrẹ ati idanwo naa kọja.
       3. LED pupa kan nitosi LED pawalara pupa n tọka si pe idanwo naa kuna.
   12. iyan. Lo aaye testbench Console System lati ṣakiyesi iṣẹjade idanwo afikun.
       Akiyesi: Lo Console System lati ṣe atẹle awọn ifihan agbara ipo ninu apẹrẹ apẹẹrẹample nigbati awọn ọkọ ti wa ni ti sopọ si kọmputa rẹ nipasẹ awọn JTAG ni wiwo. Console System n ṣe afihan ipo LED ti igbimọ fun ibojuwo latọna jijin, ipo ibẹrẹ fun igbesẹ kọọkan, ati ipo ti olupilẹṣẹ ibeere ibudo kọọkan ati oluyẹwo esi. Console System tun pese wiwo lati bẹrẹ tabi tun bẹrẹ idanwo naa.
       1. Yan Awọn irin-iṣẹ> Awọn irinṣẹ N ṣatunṣe aṣiṣe Eto> Console Eto.
       2. Ninu Console System, yan File > Ṣiṣẹ iwe afọwọkọ.
       3. Ṣii awọn file <example_design_install_dir>/ example_design/par/sysconsole_ testbench.tcl.
       4. Sọfitiwia naa n gbejade abajade idanwo ayaworan. Yan Tun-bẹrẹ lati ṣiṣe idanwo naa lẹẹkansi.

Iṣakojọpọ ati Idanwo Oniru Example ni Hardware

Arabara Memory kuubu Adarí Design

Apẹrẹ Example Apejuwe

Apẹrẹ example ṣe afihan iṣẹ ṣiṣe ti arabara Memory Cube Adarí IP mojuto. O le ṣe ina apẹrẹ lati Example Design taabu ti arabara Memory Cube Adarí ayaworan ni wiwo olumulo (GUI) ni IP paramita olootu.

Awọn ẹya ara ẹrọ

• I2C titunto si ati I2C ibẹrẹ ipinle ẹrọ fun HMC ọmọbinrin kaadi ati HMC iṣeto ni
• ATX PLL ati transceiver recalibration ipinle ẹrọ
• Beere monomono
• Beere atẹle
• System console ni wiwo

Hardware ati Software Awọn ibeere
Altera nlo ohun elo atẹle ati sọfitiwia lati ṣe idanwo apẹrẹ tẹlẹample:

• Intel Quartus NOMBA software
• Console System
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL nikan), tabi VCS simulator
• Arria 10 GX FPGA Development Apo
• HMC ọmọbinrin kaadi

Apejuwe iṣẹ-ṣiṣe

Altera pese akopọ-setan oniru example pẹlu HMC Adarí IP mojuto. Apẹrẹ yii example fojusi Arria 10 GX FPGA Idagbasoke Apo pẹlu kaadi ọmọbinrin HMC ti a ti sopọ nipasẹ awọn asopọ FMC.
O le lo apẹrẹ bi example fun asopọ deede ti ipilẹ IP rẹ si apẹrẹ rẹ, tabi bi apẹrẹ ibẹrẹ o le ṣe akanṣe fun awọn ibeere apẹrẹ tirẹ. Apẹrẹ example pẹlu module titunto si I2C, module recalibration PLL/CDR, transceiver ita PLL IP mojuto, ati kannaa lati ṣe ina ati ṣayẹwo awọn iṣowo. Apẹrẹ example dawọle a Micron HMC 15G-SR HMC ẹrọ, eyi ti o jẹ a fourlinki ẹrọ, lori kaadi ọmọbinrin. Apẹrẹ example pẹlu apẹẹrẹ kan ti ipilẹ IP ati sopọ si ọna asopọ kan lori ẹrọ HMC. olusin 2-1: HMC Adarí Design Example Àkọsílẹ aworan atọka

Lẹhin ti o tunto Arria 10 FPGA pẹlu apẹrẹ example, awọn I2C oludari configures awọn on-ọkọ aago Generators ati HMC ẹrọ. Nigbati odiwọn ba pari, apẹrẹ example calibrates awọn ATX PLL. Lakoko iṣẹ, olupilẹṣẹ ibeere ṣe ipilẹṣẹ kika ati kikọ awọn aṣẹ ti HMC Adarí IP mojuto lẹhinna ṣe ilana. Atẹle ibeere gba awọn idahun lati inu ipilẹ IP ati ṣayẹwo wọn fun titọ.

Awọn ifihan agbara wiwo
Table 2-1: HMC Adarí IP mojuto Design Eksample Awọn ifihan agbara

Orukọ ifihan agbara clk_50	Itọsọna Iṣawọle	Ìbú (Bits) 1	Apejuwe 50 MHz input aago.
hssi_refclk	Iṣawọle	1	Aago itọkasi CDR fun HMC ati HMCC IP mojuto.

Orukọ ifihan agbara hmc_lxrx	Itọsọna Iṣawọle	Ìbú (Bits) Nọmba ikanni (16 tabi 8)	Apejuwe FPGA transceiver gba awọn pinni.
hmc_lxtx	Abajade	Nọmba ikanni (16 tabi 8)	FPGA transceiver atagba pinni.
hmc_ctrl_lxrxps	Iṣawọle	1	FPGA transceiver agbara ipamọ Iṣakoso.
hmc_ctrl_lxtxps	Abajade	1	HMC transceiver agbara ipamọ Iṣakoso.
hmc_ctrl_ferr_n	Iṣawọle	1	HMC FERR_N igbejade.
hmc_ctrl_p_rst_n	Abajade	1	HMC P_RST_N igbewọle.
hmc_ctrl_scl	Bi-itọnisọna	1	HMC I2C iṣeto ni aago.
hmc_ctrl_sda	Bi-itọnisọna	1	HMC I2C data iṣeto ni.
fmc0_scl	Abajade	1	Ti ko lo. Iwakọ kekere lati daabobo awọn pinni I / O FPGA lati fifa 3.3 V lori kaadi ọmọbirin naa.
fmc0_sda	Abajade	1	Ti ko lo. Iwakọ kekere lati daabobo awọn pinni I / O FPGA lati fifa 3.3 V lori kaadi ọmọbirin naa.
push_bọtini	Iṣawọle	1	Titari bọtini titẹ sii ti a lo fun atunto.
okan_lu_n	Abajade	1	Heartbeat LED o wu.
link_init_complete_n	Abajade	1	Bibẹrẹ ọna asopọ pari iṣelọpọ LED.
idanwo_kọja_n	Abajade	1	Igbeyewo koja LED o wu.
idanwo_failed_n	Abajade	1	Idanwo kuna LED o wu.

Apẹrẹ Example Forukọsilẹ Map
Table 2-2: HMC Adarí IP mojuto Design Eksample Forukọsilẹ Map

Kikọ si awọn iforukọsilẹ wọnyi tun ṣe apẹrẹ naa.

Awọn die-die 1:0	Orukọ aaye Nọmba Port	Iru RO	Iye lori Tunto O yatọ	Apejuwe Nọmba awọn ebute oko oju omi fun apẹẹrẹ ipilẹ IP.
7:2	Ni ipamọ	RO	0x00

Table 2-4: BOARD_LEDs Forukọsilẹ
Iforukọsilẹ yii ṣe afihan ipo ti awọn LED ti igbimọ naa

Awọn die-die 0	Orukọ aaye Idanwo kuna	Iru RO	Iye lori Tunto 0x00	Apejuwe Idanwo kuna.
1	Idanwo Ti kọja	RO	0x00	Idanwo ti kọja.
2	HMCC Link Initialization Pari	RO	0x00	Ibẹrẹ ọna asopọ HMC pari ati ṣetan fun ijabọ.
3	Okan lu	RO	0x00	Yipada nigbati apẹrẹ nṣiṣẹ.
7:4	Ni ipamọ	RO	0x00

Table 2-5: TEST_INITIALIZATION_STATUS Forukọsilẹ

Awọn die-die 0	Orukọ aaye I2C Aago monomono Ṣeto	Iru RO	Iye lori Tunto 0x00	Apejuwe Awọn olupilẹṣẹ aago ori ọkọ ni tunto.
1	ATX PLL ati Transceiver Recalibration Pari	RO	0x00	ATX PLL ati transceivers tun calibrated si aago igbewọle.
2	I2C HMC Iṣeto ni Pari	RO	0x00	HMC ẹrọ iṣeto ni lori I2C pipe.
3	HMC Link Initialization Pari	RO	0x00	Ibẹrẹ ọna asopọ HMC pari ati ṣetan fun ijabọ.
7:4	Ni ipamọ	RO	0x00

Table 2-6: PORT_STATUS Forukọsilẹ

Awọn die-die 0	Orukọ aaye Port 0 Awọn ibeere O dara	Iru RO	Iye lori Tunto 0x00	Apejuwe Port 0 ìbéèrè iran pari.
1	Port 0 Awọn idahun O dara	RO	0x00	Ṣiṣayẹwo idahun Port 0 kọja.
2	Port 1 Awọn ibeere O dara	RO	0x00	Port 1 ìbéèrè iran pari.
3	Port 1 Awọn idahun O dara	RO	0x00	Ṣiṣayẹwo idahun Port 1 kọja.

Awọn die-die 4	Orukọ aaye Port 2 Awọn ibeere O dara	Iru RO	Iye lori Tunto 0x00	Apejuwe Port 2 ìbéèrè iran pari.
5	Port 2 Awọn idahun O dara	RO	0x00	Ṣiṣayẹwo idahun Port 2 kọja.
6	Port 3 Awọn ibeere O dara	RO	0x00	Port 3 ìbéèrè iran pari.
7	Port 4 Awọn idahun O dara	RO	0x00	Ṣiṣayẹwo idahun Port 3 kọja.

Alaye ni Afikun

HMC Adarí Design Example User Itọsọna Àtúnyẹwò History
Table A-1: ​​Iwe Itan Àtúnyẹwò
Akopọ titun awọn ẹya ara ẹrọ ati awọn ayipada ninu awọn oniru example olumulo itọsọna fun HMC Adarí IP mojuto.

Ọjọ	Ẹya ACDS	Awọn iyipada
2016.05.02	16.0	Itusilẹ akọkọ.

Bii o ṣe le kan si Intel
Table A-2: Bawo ni lati Kan si Intel
Lati wa alaye imudojuiwọn julọ julọ nipa awọn ọja Intel, tọka si tabili yii. O tun le kan si ọfiisi tita Intel ti agbegbe rẹ tabi aṣoju tita.

Olubasọrọ	Kan si Ọna	Adirẹsi
Oluranlowo lati tun nkan se	Webojula	www.altera.com/support
Ikẹkọ imọ-ẹrọ	Webojula	www.altera.com/training
	Imeeli	FPGATraining@intel.com
Ọja litireso	Webojula	www.altera.com/literature
Nontechnical support: gbogboogbo	Imeeli	nacomp@altera.com

Olubasọrọ   Atilẹyin ti kii ṣe imọ-ẹrọ: iwe-aṣẹ sọfitiwia

Kan si Ọna   Imeeli

Adirẹsi   aṣẹ@altera.com

Alaye ti o jọmọ

• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• aṣẹ@altera.com

Awọn Apejọ Atẹwe

Table A-3: Typographic Conventions
Ṣe atokọ awọn apejọ iwe-kikọ ti iwe yii nlo

Aami Idahun gba ọ laaye lati fi esi si Altera nipa iwe-ipamọ naa. Awọn ọna fun gbigba esi yatọ bi o ṣe yẹ fun iwe-ipamọ kọọkan

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, Altera, Arria, Cyclone, Enpion, MAX, Nios, Quartus ati Stratix ọrọ ati awọn aami jẹ aami-iṣowo ti Intel Corporation tabi awọn ẹka rẹ ni AMẸRIKA ati/tabi awọn orilẹ-ede miiran. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran
101 Innovation wakọ, San Jose, CA 95134

Imudojuiwọn to kẹhin fun Quartus Prime Design Suite: 16.0
UG-20027
2016.05.02
101 Innovation wakọ
San Jose, CA 95134
www.altera.com

Awọn iwe aṣẹ / Awọn orisun

ALTERA Arria 10 Arabara Memory Cube Adarí Design Eksample [pdf] Itọsọna olumulo Arria 10 Arabara Memory Cube Adarí Design Eksample, Arria 10, Arabara Memory kuubu Adarí Design Eksample, Adarí Design Eksample, Apẹrẹ Example

Awọn itọkasi

• Itọsọna olumulo