ALTERA Arria 10 Hybrid Memory Cube Controller Dhizaini Example

Iyo Hybrid Memory Cube Controller Dhizaini Example User Guide inopa ruzivo nezve dhizaini uye mashandisiro eiyo HMC Controller hardware dhizaini example. Nhungamiro inogadziridzwa yeQuartus Prime Design Suite 16.0 uye yakapedzisira kugadziridzwa muna Chivabvu 2, 2016.
Iyo Dhizaini ExampLe Quick Start Guide inopa nhanho-ne-nhanho mirairo yekunyora, kutevedzera, kugadzira, uye kuyedza iyo HMC Controller dhizaini ex.ample. Tarisa mufananidzo 1-1 kuti uwedzereview yematanho ebudiriro.

Design Example Description

Iyo HMC Controller hardware dhizaini example inosanganisira zvakasiyana-siyana zvakadai seBhodhi Arria 10 Chidimbu, HMC Controller IP Core, Mawachi & Reset TX PLLs, Data Path Chikumbiro Generator uye Response Monitor, TX/TX FIFO MAC, RX MAC, Test Avalon-MM Control uye LEDs, Controller Status Interface. , Avalon-MM I 2C Master, Initialization State Machine, TX Lane Swapper, Transceiver x16, RX Lane Swapper, Arria 10 Transceiver Reconfiguration Interface, uye HMC Device. The example dhizaini inoda marongero chaiwo kuti ashande nemazvo paArria 10 GX FPGA Development Kit ine HMC mwanasikana kadhi.

Mamwe Mashoko

Iyo Yekuwedzera Ruzivo chikamu chinopa ruzivo nezve dhairekitori chimiro cheyakagadzirwa dhizaini example, nhoroondo yekudzokorora yegwaro remushandisi, typographic makongisheni anoshandiswa mugwaro, uye maitiro ekubata Intel kuti atsigire.

Mirayiridzo Yekushandiswa Kwechigadzirwa

Tevedza iri pazasi mirairo yekushandisa HMC Controller hardware dhizaini example:

1. Gadzira iyo dhizaini exampndinoshandisa simulator
2. Ita simulation inoshanda
3. Gadzira iyo dhizaini example
4. Gadzira iyo dhizaini exampuye kushandisa Quartus Prime
5. Edza dhizaini yehardware

Ziva kuti iyo hardware kumisikidza uye bvunzo files yekugadzira example vari mu/example_design/par, nepo simulation files dziri mukati / example_design/sim.

Kuti ikubatsire kunzwisisa mashandisiro eHybrid Memory Cube Controller IP musimboti, iyo musimboti ine simulatable testbench uye hardware dhizaini ex.ample iyo inotsigira kuunganidza uye kuyedza hardware. Paunogadzira iyo dhizaini example, iyo parameter editor inogadzira iyo fileinodiwa kutevedzera, kuunganidza, uye kuyedza dhizaini muhardware. Unogona kudhawunirodha dhizaini yakaunganidzwa kuIntel® Arria® 10 GX FPGA Development Kit.

Related Information
Hybrid Memory Cube Controller IP Core User Guide

Design Example Directory Structure

Iyo hardware kumisikidza uye bvunzo files (iyo hardware dhizaini example) vari mukatiample_ design_install_dir>/example_design/par. The simulation files (testbench yekufananidza chete) iri mukatiample_design_install_dir>/example_design/sim.

Design Example Components

Iyo HMC Controller hardware dhizaini example inosanganisira zvinotevera zvikamu:

• HMC Controller IP musimboti ine CDR referensi wachi yakaiswa ku125 MHz uye ine default RX mepu uye TX mepu marongero.
  Cherechedza: Iyo yakagadzirwa example inoda kuti zvigadziriso izvi zvishande nemazvo paArria 10 GX FPGA Development Kit ine HMC mwanasikana kadhi.
• Mutengi logic inoronga hurongwa hweiyo IP musimboti, uye kugadzirwa kwepaketi uye kutarisa.
• JTAG controller inotaurirana neAltera System Console. Iwe unotaurirana nemutengi logic kuburikidza neSystem Console.

Anonyora kiyi files iyo inoshandisa example testbench.

/src/hmcc_example.sv	Yepamusoro-nhanho hardware dhizaini example file.
/sim/hmcc_tb.sv	Top-level file yekufananidza.
Testbench Scripts Cherechedza: Shandisa iyo yakapihwa Makefile kugadzira zvinyorwa izvi.
/sim/run_vsim.do	Iyo ModelSim script yekumhanyisa testbench.
/sim/run_vcs.sh	Iyo Synopsys VCS script yekumhanyisa testbench.
/sim/run_ncsim.sh	Iyo cadence NCSim script yekumhanyisa testbench.

Kugadzira iyo Dhizaini Example

Mufananidzo 1-5: Eksampuye Dhizaini Tab muHybrid Memory Cube Controller Parameter Mharidzo

Tevedza nhanho idzi kugadzira iyo Arria 10 hardware dhizaini example uye testbench:

1. Mune IP Catalog (Zvishandiso> IP Catalog), sarudza iyo Arria 10 yakananga mudziyo mhuri.
2. Mune IP Catalog, tsvaga uye sarudza Hybrid Memory Cube Controller. The New IP Variation hwindo rinoonekwa.
3. Rondedzera zita repamusoro-soro kune yako tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .qsys.
4. Iwe unofanirwa kusarudza chaiyo Arria 10 mudziyo mumudziyo weChishandiso, kana chengetedza iyo default mudziyo iyo Quartus Prime software inosarudza.
5. Dzvanya OK. IP parameter editor inooneka.
6. PaI IP tab, tsanangura maparamita eiyo IP yako musimboti musiyano.
7. Pamusoro peExample Dhizaini tab, sarudza anotevera marongero eiyo dhizaini example:
   1. Kuti Sarudza Dhizaini, sarudza iyo HMCC Mwanasikana Bhodhi sarudzo.
   2. For Example Dhizaini Files, sarudza iyo Simulation sarudzo yekugadzira testbench, uye sarudza iyo Synthesis sarudzo yekugadzira iyo hardware dhizaini ex.ample.
   3. Kune Yakagadzirwa HDL Format, Verilog chete ndiyo inowanikwa.
   4. YeTarget Development Kit sarudza iyo Arria 10 GX FPGA Development Kit (Silicon Yekugadzira).
      Cherechedza: Paunosarudza kit iyi, iyo hardware dhizaini example inonyora yako yapfuura mudziyo sarudzo nemudziyo uri pabhodhi rinotarirwa. Paunogadzira iyo dhizaini exampuye, iyo Intel Quartus Prime software inogadzira Intel
      Quartus Prime project, kuseta, uye pini mabasa ebhodhi rawakasarudza. Kana iwe usingade software kunanga bhodhi chairo, sarudza Hapana.
8. Dzvanya iyo Gadzira Example Dhizaini bhatani

Kunzwisisa Testbench

Altera inopa dhizaini example neHMC Controller IP musimboti. Iyo yakagadzirwa example inowanikwa zvese zvekuteedzera yako IP musimboti uye yekubatanidza. Iyo yakagadzirwa example mukuenzanisa mabasa seHMC Controller IP musimboti testbench.
Kana ukadzvanya Gadzira Example Dhizaini muHMC Controller parameter mupepeti, iyo Quartus Prime software inogadzira yekuratidzira testbench. Iyo parameter mupepeti inokukurudzira iwe kune yaunoda nzvimbo ye testbench.
Kutevedzera testbench, unofanirwa kupa yako HMC bhazi inoshanda modhi (BFM). Altera anoedza dhizaini exampuye testbench ine Micron Hybrid Memory Cube BFM. Iyo testbench haisanganisi I2C master module, nekuti iyo Micron HMC BFM haitsigire uye haidi kugadziridzwa neI2C module.
Mukufananidza, testbench inodzora TX PLL uye nzira yedata nzira kuti iite zvinotevera kutevedzana kwezviito:

1. Inogadzirisa HMC BFM neHMC Controller IP core data rate uye upamhi hwechiteshi, muResponse Open Loop Mode.
2. Inogadza chinongedzo pakati peBFM neiyo IP musimboti.
3. Inotungamira imwe neimwe yeIP core's mana ports kuti inyore mana mapaketi edata kuBFM.
4. Inotungamira iyo IP musimboti kuti uverenge kumashure data kubva kuBFM.
5. Inotarisa kuti data yakaverengwa inoenderana neinyorwa data.
6. Kana data richienderana, rinoratidza TEST_PASSED.

Kutevedzera Dhizaini Example Testbench
Mufananidzo 1-6: Maitiro

Tevera matanho aya kutevedzera testbench:

1. Pamutsetse wekuraira, chinja kune iyoample>/sim directory.
2. Nyora kugadzira zvinyorwa.
3. Nyora imwe yeinotevera mirairo, zvichienderana nesimulator yako:
4. To view simulation results:
   1. Paunomhanyisa testbench mune chero matatu matatu anotsigirwa simulators, script inoita testbench kutevedzana uye inoisa iyo simulator chiitiko mukati.ample directory>/example_ dhizaini/sim/ .log. iri “vsim”, “ncsim”, kana “vcs”.
   2. Paunomhanyisa testbench mune chero matatu matatu anotsigirwa simulators, iyo script inogadzira waveform file. Unogona kumhanya command make _gui kurodha waveform mune simulator-chaiyo waveform viewer.
      To view waveform file mune yako simulator, nyora mumwe weinotevera mirairo:

      Simulator License Mentor Graphics ModelSim	Command Line ita vsim_gui	Waveform File <design example directory>/example_design/sim/ mentor/hmcc_wf.wlf
      Synopsys Discovery Visual Environment	ita vcs_gui	<design example directory>/example_design/sim/ hmcc_wf.vpd
      Kadence SimVision Waveform	make ncsim_gui	<design example directory>/example_design/sim/ cadence/hmcc_wf.shm
5. Ongorora zvabuda. Testbench yakabudirira inotumira uye inogamuchira mapaketi gumi pachiteshi, uye inoratidza Test_PASSED”

Kugadzira Bhodhi

Gadzirisa bhodhi kuti imhanye iyo hardware dhizaini example.
Cherechedza: Ita shuwa kuti simba rakadzimwa usati wachinja chero marongero.

1. Seta maswichi eDIP pakadhi remwanasikana sezvinotevera:
2. Seta DIP switch SW1 kuratidza cube ID 0:
   

   Switch	Function	Setting
   1	CUB[0]	Vhura
   2	CUB[1]	Vhura
   3	CUB[2]	Vhura
   4	—	Usaita Hanya

Seta DIP switch SW2 kuti utaure marongero ewachi:

Switch	Function	Setting
1	CLK1_FSEL0	Vhura (125 MHz)
2	CLK1_FSEL1	Vhura (125 MHz)
3	CLK1_SEL	Vhura (Crystal)
4	—	Usaita Hanya

• Batanidza iyo HMC mwanasikana kadhi kuArria 10 FPGA Development Kit uchishandisa kadhi remwanasikana's J8 uye J10 zvibatanidza.
• Seta vanosvetuka paArria 10 GX FPGA Development Kit:
• Wedzera shunts kune J8 jumper kuti usarudze 1.5 V seVCCIO yekumisikidza yeFMC yekubatanidza B.
• Wedzera shunts kune J11 jumper kuti usarudze 1.8 V seVCCIO yekumisikidza yeFMC yekubatanidza A.

Kunyora uye Kuedza Dhizaini Example mu Hardware

Kuunganidza uye kumhanyisa bvunzo yekuratidzira pane Hardware dhizaini example, tevera matanho aya

1. Ita shuwa kuti hardware dhizaini example generation yapera.
2. Mune iyo Quartus Prime software, vhura iyo Quartus Prime chirongwaample_design_install_dir> /example_design/par/hmcc_example.qpf.
3. MuCompilation Dashboard, tinya Gadzira Dhizaini (Intel Quartus Prime Pro Edition) kana sarudza Kugadzirisa> Kutanga Kuunganidza (Intel Quartus Prime Standard Edition).
4. Mushure mekugadzira .sof, tevera matanho aya kuronga hardware design examppane iyo Arria 10 mudziyo:
   1. Sarudza Zvishandiso> Programmer.
   2. MuPurogiramu, tinya Hardware Setup.
   3. Sarudza chigadzirwa chepurogiramu.
   4. Sarudza uye wedzera iyo Arria 10 GX FPGA Development Kit iyo yako Quartus Prime chikamu inogona kubatana.
   5. Ita shuwa kuti Mode yakaiswa kuna JTAG.
   6. Dzvanya Auto Detect uye sarudza chero mudziyo.
   7. Tinya kaviri mudziyo weArria 10.
   8. Vhura iyo .sof inample_design_install_dir>/example_design/par/output_ files,
      Cherechedza: Iyo Quartus Prime software inoshandura mudziyo kune iri mu.sof.
   9. Mumutsara ne .sof yako, tarisa bhokisi muPurogiramu/Gadzirisa column.
   10. Click Start.
   11. Mushure mekunge software yagadzirisa mudziyo neiyo hardware dhizaini exampLe, cherechedza ma LEDs ebhodhi:
       1. Kupenya kwe LED kunoratidza kuti dhizaini iri kushanda.
       2. Ma LED maviri egirinhi padyo neiyo tsvuku inopenya LED inoratidza kuti HMC link inotangwa uye bvunzo dzakapfuura.
       3. Imwe LED tsvuku padhuze neiyo tsvuku inopenya LED inoratidza kuti bvunzo yakundikana.
   12. Optional. Shandisa iyo System Console testbench kuona yakawedzera bvunzo kubuda.
       Cherechedza: Shandisa iyo System Console kutarisa masiginecha echimiro mudhizaini example kana bhodhi rakabatana pakombuta yako kuburikidza neJTAG interface. Iyo System Console inoratidza bhodhi re LED mamiriro ekutarisisa kure, mamiriro ekutanga ega ega nhanho, uye chimiro chegwaro rekukumbira jenareta uye cheki chemhinduro. Iyo System Console inopawo chimiro chekutanga kana kutangazve bvunzo.
       1. Sarudza Zvishandiso> System Debugging Zvishandiso> System Console.
       2. MuSystem Console, sarudza File > Ita Script.
       3. Vhura iyo file <example_design_install_dir>/example_design/par/sysconsole_ testbench.tcl.
       4. Iyo software inoremedza graphical bvunzo kubuda. Sarudza Re-start kuti umhanye bvunzo zvakare.

Kunyora uye Kuedza Dhizaini Example mu Hardware

Hybrid Memory Cube Controller Dhizaini

Design Example Description

Iyo yakagadzirwa example inoratidza kushanda kweHybrid Memory Cube Controller IP musimboti. Iwe unogona kugadzira dhizaini kubva kuExample Dhizaini tebhu yeHybrid Memory Cube Controller graphical mushandisi interface (GUI) muIP parameter mupepeti.

Features

• I2C tenzi uye I2C yekutanga mamiriro muchina weHMC mwanasikana kadhi uye HMC kumisikidzwa
• ATX PLL uye transceiver recalibration state muchina
• Kumbira jenareta
• Kumbira monitor
• System Console interface

Hardware uye Software Zvinodiwa
Altera inoshandisa iyi inotevera Hardware uye software kuyedza iyo dhizaini example:

• Intel Quartus Prime software
• System Console
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL chete), kana VCS simulator
• Arria 10 GX FPGA Development Kit
• HMC mwanasikana kadhi

Tsanangudzo Yekushanda

Altera inopa kuunganidza-yakagadzirira dhizaini example neHMC Controller IP musimboti. Iyi dhizaini example inonangana neArria 10 GX FPGA Development Kit ine HMC mwanasikana kadhi yakabatana kuburikidza neFMC zvinongedzo.
Iwe unogona kushandisa dhizaini seye example yekubatanidza kwakaringana kweIP yako musimboti kune dhizaini yako, kana seyekutanga dhizaini iwe unogona kugadzirisa kune yako wega dhizaini zvinodiwa. Iyo yakagadzirwa example inosanganisira I2C master module, PLL/CDR recalibration module, imwe yekunze transceiver PLL IP musimboti, uye pfungwa kugadzira uye kutarisa kutengeserana. Iyo yakagadzirwa example inotora Micron HMC 15G-SR HMC mudziyo, iri fourlmudziyo weinki, pakadhi remwanasikana. Iyo yakagadzirwa example inosanganisira imwe muenzaniso yeIP musimboti uye inobatanidza kune imwechete link pane HMC mudziyo. Mufananidzo 2-1: HMC Controller Design Exampuye Block Diagram

Mushure mekugadzirisa iyo Arria 10 FPGA ine dhizaini example, iyo I2C controller inogadzirisa pane-bhodhi wachi jenareta uye HMC mudziyo. Kana calibration yapera, dhizaini exampuye inogadzirisa iyo ATX PLL. Panguva yekushanda, jenareta rekukumbira rinogadzira kuverenga nekunyora mirairo iyo HMC Controller IP musimboti wobva waita. Iyo yekukumbira yekutarisisa inotora mhinduro kubva kuIP musimboti uye inotarisa kuti ndeyechokwadi.

Interface Signals
Tafura 2-1: HMC Controller IP Core Dhizaini Example Signals

Zita rechiratidzo clk_50	Direction Input	Upamhi (Bits) 1	Tsanangudzo 50 MHz yekuisa wachi.
hssi_refclk	Input	1	CDR referensi wachi yeHMC uye HMCC IP musimboti.

Zita rechiratidzo hmc_lxrx	Direction Input	Upamhi (Bits) Channel Count (16 kana 8)	Tsanangudzo FPGA transceiver inogamuchira mapini.
hmc_lxtx	Output	Channel Count (16 kana 8)	FPGA transceiver transmit pini.
hmc_ctrl_lxrxps	Input	1	FPGA transceiver simba kuchengetedza kutonga.
hmc_ctrl_lxtxps	Output	1	HMC transceiver simba kuchengetedza kutonga.
hmc_ctrl_ferr_n	Input	1	HMC FERR_N kubuda.
hmc_ctrl_p_rst_n	Output	1	HMC P_RST_N kuisa.
hmc_ctrl_scl	Bi-Directional	1	HMC I2C yekumisikidza wachi.
hmc_ctrl_sda	Bi-Directional	1	HMC I2C yekumisikidza data.
fmc0_scl	Output	1	Zvisina kushandiswa. Inotyairwa yakaderera kuchengetedza iyo FPGA I/O mapini kubva ku3.3 V kudhonza pane mwanasikana kadhi.
fmc0_sda	Output	1	Zvisina kushandiswa. Inotyairwa yakaderera kuchengetedza iyo FPGA I/O mapini kubva ku3.3 V kudhonza pane mwanasikana kadhi.
push_button	Input	1	Push bhatani rekuisa rakashandiswa kuseta patsva.
mwoyo_kurova_n	Output	1	Heartbeat LED kubuda.
link_init_complete_n	Output	1	Link yekutanga kuzadzisa LED kubuda.
test_passed_n	Output	1	Muedzo wakapfuura kubuda kwe LED.
test_foiled_n	Output	1	Muedzo watadza kubuda neLED.

Design Example Register Mepu
Tafura 2-2: HMC Controller IP Core Dhizaini Example Register Mepu

Kunyorera kumarejista aya kunogadzirisa dhizaini.

Bits 1:0	Zita remunda Port Count	Type RO	Kukosha paReset Inosiyana	Tsanangudzo Nhamba yezviteshi zveiyo IP musimboti muenzaniso.
7:2	Reserved	RO	0x00

Tafura 2-4: BOARD_LEDs Register
Iri rejisita rinoratidza mamiriro emaLED ebhodhi

Bits 0	Zita remunda Muedzo Wakundikana	Type RO	Kukosha paReset 0x00	Tsanangudzo Muedzo wakundikana.
1	Bvunzo rakapasa	RO	0x00	Muedzo wakapasa.
2	HMCC Link Initialization Yakakwana	RO	0x00	HMC yekubatanidza yekutanga yakwana uye yakagadzirira traffic.
3	Kurova kwemoyo	RO	0x00	Toggles kana dhizaini iri kushanda.
7:4	Reserved	RO	0x00

Tafura 2-5: TEST_INITIALIZATION_STATUS Register

Bits 0	Zita remunda I2C Clock jenareta Seti	Type RO	Kukosha paReset 0x00	Tsanangudzo Pa-board wachi jenareta akagadziridzwa.
1	ATX PLL uye Transceiver Recalibration Yakazara	RO	0x00	ATX PLL uye matransceivers akadzokororwa kune wachi yekuisa.
2	I2C HMC Kugadzirisa Kwapera	RO	0x00	HMC mudziyo kumisikidzwa pamusoro peI2C yakakwana.
3	HMC Link Initialization Yakwana	RO	0x00	HMC yekubatanidza yekutanga yakwana uye yakagadzirira traffic.
7:4	Reserved	RO	0x00

Tafura 2-6: PORT_STATUS Register

Bits 0	Zita remunda Port 0 Inokumbira OK	Type RO	Kukosha paReset 0x00	Tsanangudzo Port 0 chikumbiro kugadzirwa kwapera.
1	Port 0 Responses OK	RO	0x00	Port 0 mhinduro yekutarisa yakapfuura.
2	Port 1 Inokumbira OK	RO	0x00	Port 1 chikumbiro kugadzirwa kwapera.
3	Port 1 Responses OK	RO	0x00	Port 1 mhinduro yekutarisa yakapfuura.

Bits 4	Zita remunda Port 2 Inokumbira OK	Type RO	Kukosha paReset 0x00	Tsanangudzo Port 2 chikumbiro kugadzirwa kwapera.
5	Port 2 Responses OK	RO	0x00	Port 2 mhinduro yekutarisa yakapfuura.
6	Port 3 Inokumbira OK	RO	0x00	Port 3 chikumbiro kugadzirwa kwapera.
7	Port 4 Responses OK	RO	0x00	Port 3 mhinduro yekutarisa yakapfuura.

Mamwe Mashoko

HMC Controller Dhizaini Example User Guide Revision History
Tafura A-1: ​​Document Revision History
Inopfupikisa maficha matsva uye shanduko mudhizaini example mushandisi gwara reiyo HMC Controller IP musimboti.

Date	ACDS Shanduro	Kuchinja
2016.05.02	16.0	Kusunungurwa kwekutanga.

Maitiro ekubata Intel
Tafura A-2: Maitiro ekubata Intel
Kuti uwane ruzivo rwakanyanya-kusvika-zuva nezveIntel zvigadzirwa, tarisa kune iyi tafura. Iwe unogona zvakare kubata yako yemuno Intel yekutengesa hofisi kana mumiriri wekutengesa.

Contact	Contact Method	Kero
Tsigiro yehunyanzvi	Website	www.altera.com/support
Kudzidziswa kwehunyanzvi	Website	www.altera.com/training
	Email	FPGATraining@intel.com
Zvinyorwa zvinyorwa	Website	www.altera.com/literature
Nontechnical support: general	Email	nacomp@altera.com

Contact   Nontechnical rutsigiro: software rezenisi

Contact Method   Email

Kero   authorization@altera.com

Related Information

• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• authorization@altera.com

Typographic Kokorodzano

Tafura A-3: Typographic Kokorodzano
Inodonongodza zvibvumirano zvekutaipa zvinoshandiswa negwaro iri

Iyo Feedback icon inokutendera iwe kuendesa mhinduro kuAltera nezve gwaro. Nzira dzekuunganidza mhinduro dzinosiyana zvichienderana negwaro rega rega

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus uye Stratix mazwi uye logos zviratidzo zveIntel Corporation kana masangano ayo muUS uye/kana dzimwe nyika. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
Mamwe mazita nemhando anogona kunzi zvinhu zvevamwe
101 Innovation Drive, San Jose, CA 95134

Yekupedzisira yakagadziridzwa yeQuartus Prime Design Suite: 16.0
UG-20027
2016.05.02
101 Kugadzira Dhiraivha
San Jose, CA 95134
www.altera.com

Zvinyorwa / Zvishandiso

ALTERA Arria 10 Hybrid Memory Cube Controller Dhizaini Example [pdf] Bhuku reMushandisi Arria 10 Hybrid Memory Cube Controller Dhizaini Example, Arria 10, Hybrid Memory Cube Controller Dhizaini Example, Controller Dhizaini Example, Dhizaini Example

References

• User Manual