ALTERA Arria 10 Ngwakọta ebe nchekwa Cube chepụta Example

Ngwakọta nchekwa Cube Controller Design Example User Guide na-enye ozi gbasara imewe na ojiji nke HMC Controller design hardware example. Emelitere ntuziaka maka Quartus Prime Design Suite 16.0 ma emelitere ikpeazụ na Mee 2, 2016.
The Design Example Quick Start Guide na-enye ntuziaka nzọụkwụ site n'usoro maka ịchịkọta, ịme anwansị, imepụta, na ịnwale nhazi HMC Controller ex.ample. Rụtụ aka na eserese 1-1 maka njedebeview nke usoro mmepe.

Imepụta Example Nkọwa

Ihe nhazi ngwaike HMC Controller example na-agụnye ihe dị iche iche dị ka Board Arria 10 Device, HMC Controller IP Core, Clocks & Reset TX PLLs, Data Path Request Generator and Response Monitor, TX/TX FIFO MAC, RX MAC, Test Avalon-MM Control and LEDs, Controller Status Interface, Avalon-MM I 2C Master, Initialization State Machine, TransXne RX, LapperXne 16. Swapper, Arria 10 Transceiver Reconfiguration Interface, na ngwaọrụ HMC. The example imewe chọrọ ntọala pụrụ iche iji rụọ ọrụ nke ọma na Arria 10 GX FPGA Development Kit nwere kaadị ada HMC.

Ozi Mgbakwunye

Ngalaba ozi agbakwunyere na-enye nkọwapụta na nhazi ndekọ aha maka imewe emepụtara example, akụkọ nlegharị anya nke ntuziaka onye ọrụ, mgbakọ ederede ejiri na ntuziaka, yana otu esi akpọtụrụ Intel maka nkwado.

Ntuziaka ojiji ngwaahịa

Soro ntuziaka dị n'okpuru ka iji HMC Controller design hardware exampLe:

1. Chịkọta imewe exampiji simulator
2. Mee ịme anwansị arụ ọrụ
3. Mepụta imewe example
4. Chịkọta imewe exampna-eji Quartus Prime
5. Nwalee imewe ngwaike

Rịba ama na nhazi ngwaike na ule files maka imewe example dị na /example_design/par, mgbe ịme anwansị files dị na /example_design/sim.

Iji nyere gị aka ịghọta otu esi eji Hybrid Memory Cube Controller IP core, isi ya nwere testbench simulatable yana ngwa ihe eji arụ ọrụ.ample nke na-akwado mkpokọta na nyocha ngwaike. Mgbe ị na-emepụta imewe example, paramita nchịkọta akụkọ na-akpaghị aka na-emepụta files necessary to simulate, compile, and test the design in hardware. You can download the compiled design to the Intel® Arria® 10 GX FPGA Development Kit.

Ozi metụtara
Ngwakọ nchekwa Cube njikwa IP isi ntuziaka onye ọrụ

Imepụta Exampn'akwụkwọ ndekọ aha Structure

Nhazi ngwaike na ule files (ihe nhazi ngwaike example) dị naample_ design_install_dir>/example_design/par. The ịme anwansị files (testbench maka ịme anwansị naanị) dị naample_design_install_dir>/ example_design/sim.

Imepụta Exampna akụrụngwa

Ihe nhazi ngwaike HMC Controller example gụnyere ihe ndị a:

• HMC Controller IP core nwere elekere ntụaka CDR ka edobere na 125 MHz yana yana maapụ RX ndabara yana ntọala maapụ TX.
  Rịba ama: Imewe example chọrọ ka ntọala ndị a rụọ ọrụ nke ọma na Arria 10 GX FPGA Development Kit nwere kaadị ada HMC.
• Echiche ndị ahịa nke na-ahazi mmemme nke isi IP, yana ọgbọ na nlele.
• JTAG njikwa na-ekwurịta okwu na Altera System Console. Ị na-ekwurịta okwu na mgbagha onye ahịa site na Sistemu Console.

Na-edepụta igodo files na mejuputa example testbench.

/src/hmcc_example.sv	Nhazi ngwaike dị elu example file.
/sim/hmcc_tb.sv	Ọkwa kacha file maka ịme anwansị.
Ederede Testbench Mara: Jiri Mee ka enyerefile iji mepụta edemede ndị a.
/sim/run_vsim.do	Ederede ModelSim ka ọ na-agba testbench.
/sim/run_vcs.sh	Edemede Synopsys VCS iji mee testbench.
/sim/run_ncsim.sh	Edemede Cadence NCsim iji mee testbench.

Na-emepụta ihe osise Example

Ọgụgụ 1-5: ỌpụampMepụta Tab na Ngwakọ Nchekwa Cube Controller Parameter Editor

Soro usoro ndị a ka ịmepụta Arria 10 hardware design example na testbench:

1. In the IP Catalog (Tools > IP Catalog), select the Arria 10 target device family.
2. Na katalọgụ IP, chọta ma họrọ Ngwakọ ebe nchekwa Cube Controller. Window mgbanwe IP ọhụrụ na-egosi.
3. Ezipụta aha ọkwa dị elu maka ụdị IP gị nkeonwe. Onye ndezi paramita na-echekwa ntọala IP dị iche na a file aha ya .qsys.
4. Ị ga-ahọrọ otu ngwaọrụ Arria 10 n'ọhịa ngwaọrụ, ma ọ bụ dobe ngwaọrụ ndabara nke Quartus Prime software na-ahọrọ.
5. Pịa OK. Ihe ndezi paramita IP na-egosi.
6. Na taabụ IP, ezipụta paramita maka mgbanwe isi IP gị.
7. Na Exampsite Design tab, họrọ ndị a ntọala maka imewe exampLe:
   1. Maka Họrọ imewe, họrọ HMCC Daughter Board nhọrọ.
   2. Maka Example Design Files, họrọ nhọrọ Simulation iji mepụta testbench, wee họrọ nhọrọ Synthesis iji mepụta ngwaike imewe ex.ample.
   3. Maka Ụdị HDL emepụtara, naanị Verilog dị.
   4. Maka ngwa mmepe Target họrọ Arria 10 GX FPGA Development Kit (Silicon Mmepụta).
      Rịba ama: Mgbe ị na-ahọrọ ngwa a, ngwaike imewe example overwrites gị gara aga ngwaọrụ nhọrọ na ngwaọrụ na iche osisi. Mgbe ị na-emepụta imewe example, the Intel Quartus Prime software creates Intel
      Ọrụ Quartus Prime, ntọala na ntụtụ maka bọọdụ ị họọrọ. Ọ bụrụ na ịchọghị ka ngwanro ahụ lekwasịrị anya otu bọọdụ, họrọ Ọ nweghị.
8. Pịa n'ịwa Example Design bọtịnụ

Ịghọta Testbench

Altera na-enye imewe exampya na HMC Controller IP core. Imewe example is available both for simulation of your IP core and for compilation. The design exampna-arụ ọrụ ịme anwansị dị ka HMC Controller IP core testbench.
Ọ bụrụ na ị pịa n'ịwa Example Design in the HMC Controller parameter editor, the Quartus Prime software generates a demonstration testbench. The parameter editor prompts you for the desired location of the testbench.
Iji mee ka testbench, ị ga-enwerịrị ụdị ọrụ ụgbọ ala HMC nke gị (BFM). Altera nwale imewe example testbench na Micron Hybrid Memory Cube BFM. The testbench adịghị agụnye I2C master modul, n'ihi na Micron HMC BFM anaghị akwado na ọ dịghị achọ nhazi site I2C modul.
Na ịme anwansị, testbench na-ejikwa TX PLL na oghere ụzọ data iji mee usoro omume ndị a:

1. Na-ahazi HMC BFM na HMC Controller IP isi data ọnụego yana obosara ọwa, na Nzaghachi Mepee Loop Mode.
2. Na-ewepụta njikọ n'etiti BFM na isi IP.
3. Na-eduzi ọdụ ụgbọ mmiri anọ nke isi IP nke ọ bụla ka ọ dee ngwugwu data anọ na BFM.
4. Na-eduzi isi IP ka ọ gụghachi data sitere na BFM.
5. Na-enyocha na data ọgụgụ ahụ dabara na data ederede.
6. Ọ bụrụ na data ahụ dabara, na-egosi TEST_PASSED.

Ịmepụta atụmatụ Exampna Testbench
Ọgụgụ 1-6: Usoro

Soro usoro ndị a ka ịmee testbench:

1. N'ahịrị iwu, gbanwee gaa naample>/ SIM ndekọ.
2. Pịnye ederede eme.
3. Pịnye otu n'ime iwu ndị a, dabere na simulator gị:
4. Iji view nsonaazụ ịme anwansị:
   1. Mgbe ị na-agba testbench na nke ọ bụla n'ime simulator atọ akwadoro, edemede ahụ na-eme usoro testbench wee deba ọrụ simulator na ya.ample ndekọ>/example_ design/sim/ .log. bụ "vsim", "ncsim", ma ọ bụ "vcs".
   2. Mgbe ị na-agba testbench na nke ọ bụla n'ime simulators atọ akwadoro, edemede ahụ na-ewepụta ụdị ebili mmiri file. Ị nwere ike ịme ihe iwu _gui iji buo ụdị ebili mmiri n'ụdị ebili mmiri nke simulator akọwapụtara viewee.
      Iji view ụdị ifegharị file na simulator gị, pịnye otu n'ime iwu ndị a:

      Ikikere Simulator Ihe eserese nke Mentor Sim	Ahịrị iwu mee vsim_gui	Waveform File <design example directory>/ example_design/sim/ mentor/hmcc_wf.wlf
      Synopsys Discovery Visual Environment	mee vcs_gui	<design example directory>/ example_design/sim/ hmcc_wf.vpd
      Cadence SimVision Waveform	mee ncsim_gui	<design example directory>/ example_design/sim/ cadence/hmcc_wf.shm
5. Nyochaa nsonaazụ ya. Testbench na-aga nke ọma na-eziga ma nata ngwugwu iri n'otu ọdụ ụgbọ mmiri, ma gosipụta Test_PASSED"

Ịtọlite ​​​​bọọdụ ahụ

Hazie bọọdụ ka ọ rụọ ọrụ nhazi ngwaike example.
Rịba ama: Gbaa mbọ hụ na agbanyụrụ ọkụ tupu ịgbanwee ntọala ọ bụla.

1. Tọọ mgba ọkụ DIP na kaadị nwa nwanyị dịka ndị a:
2. Tọọ mgbanwe DIP SW1 iji gosi cube ID 0:
   

   Gbanwee	Ọrụ	Ịtọ ntọala
   1	CUB[0]	Mepee
   2	CUB[1]	Mepee
   3	CUB[2]	Mepee
   4	-	Echegbula

Tọọ mgbanwe DIP SW2 iji kọwaa ntọala elekere:

Gbanwee	Ọrụ	Ịtọ ntọala
1	CLK1_FSEL0	Mepee (125 MHz)
2	CLK1_FSEL1	Mepee (125 MHz)
3	CLK1_SEL	Mepee (Crystal)
4	-	Echegbula

• Jikọọ kaadị ada HMC na Arria 10 FPGA Development Kit site na iji njikọ J8 na J10 nke nwa nwanyị kaadị.
• Tọọ ndị jumpers na Arria 10 GX FPGA Development Kit:
• Tinye shunts na J8 jumper ka ịhọrọ 1.5 V dị ka ntọala VCCIO maka njikọ FMC B.
• Tinye shunts na J11 jumper ka ịhọrọ 1.8 V dị ka ntọala VCCIO maka njikọ FMC A.

Compiling and Testing the Design Exampna Hardware

Iji chịkọta ma mee nnwale ngosi na nhazi ngwaike example, soro usoro ndị a

1. Gbaa mbọ hụ na imepụta ngwaike example ọgbọ agwụla.
2. Na ngwa Quartus Prime, mepee ọrụ Quartus Primeample_design_install_dir>/example_design/par/hmcc_example.qpf.
3. Na mkpokọta Dashboard, pịa Compile Design (Intel Quartus Prime Pro Edition) ma ọ bụ họrọ Nhazi> Malite Nchịkọta (Intel Quartus Prime Standard Edition).
4. Mgbe ịmepụtachara .sof, soro usoro ndị a ka ị hazie ngwaike nhazi ihe mbụample na ngwaọrụ Arria 10:
   1. Họrọ Ngwa> Onye mmemme.
   2. Na Programmer, pịa Hardware Mbido.
   3. Họrọ ngwaọrụ mmemme.
   4. Họrọ ma tinye Arria 10 GX FPGA Development Kit nke nnọkọ Quartus Prime gị nwere ike jikọọ na ya.
   5. Gbaa mbọ hụ na edobere ọnọdụ na JTAG.
   6. Pịa Chọpụta akpaaka wee họrọ ngwaọrụ ọ bụla.
   7. Pịa ngwaọrụ Arria 10 ugboro abụọ.
   8. Mepee .sof inample_design_install_dir>/ example_design/nha/ mmepụta_ files,
      Rịba ama: Ngwa Quartus Prime na-agbanwe ngwaọrụ ahụ ka ọ bụrụ nke dị na .sof.
   9. N'ahịrị na .sof gị, lelee igbe dị na kọlụm Mmemme/Hazie.
   10. Pịa Malite.
   11. Mgbe software configures ngwaọrụ na ngwaike imewe example, leba anya na osisi LEDs:
       1. Igwe ọkụ na-acha uhie uhie na-egbuke egbuke na-egosi na imewe na-agba ọsọ.
       2. Igwe ọkụ abụọ na-acha akwụkwọ ndụ akwụkwọ ndụ dị nso na-acha uhie uhie na-egbuke egbuke LED na-egosi na etinyere njikọ HMC na ule ahụ gafere.
       3. Otu ọkụ ọkụ na-acha uhie uhie dị nso na ọkụ ọkụ na-acha uhie uhie na-egosi na ule ahụ dara.
   12. Nhọrọ. Jiri testbench kọnsụl sistemu ka ịhụ mmepụta ule agbakwunyere.
       Mara: Jiri Sistemụ njikwa ka nyochaa ọkwa ọkwa na imewe example mgbe ejikọrọ osisi na kọmputa gị site na JTAG interface. Ihe njikwa Sistemu na-egosi ọkwa LED nke bọọdụ maka nleba anya n'ime ime, ọkwa mmalite maka nzọụkwụ ọ bụla, yana ọkwa nke ihe nrụpụta arịrịọ ọdụ ụgbọ mmiri ọ bụla na nlele nzaghachi. Sistemụ njikwa na-enyekwa interface ịmalite ma ọ bụ malitegharịa ule ahụ.
       1. Họrọ Ngwa> Ngwa nbipu sistemu> njikwa sistemụ.
       2. Na Sistemụ njikwa, họrọ File > Mepụta edemede.
       3. Mepee file <example_design_install_dir>/ example_design/par/sysconsole_ testbench.tcl.
       4. The software loads graphical test output. Choose Re-start to run the test again.

Compiling and Testing the Design Exampna Hardware

Ngwakọ Nchekwa Cube njikwa imewe

Imepụta Example Nkọwa

Imewe example na-egosipụta ọrụ nke ngwakọ ebe nchekwa Cube Controller IP isi. Ị nwere ike ịmepụta imewe site na ExampLe Kere taabụ nke ngwakọ ebe nchekwa Cube Controller graphical user interface (GUI) na IP parameter editọ.

Atụmatụ

• I2C master na igwe mmalite steeti I2C maka kaadị nwa nwanyị HMC na nhazi HMC
• ATX PLL na transceiver recalibration steeti igwe
• Rịọ generator
• Rịọ onye nleba anya
• Sistemụ njikwa njikwa

Achọrọ ngwaike na ngwanrọ
Altera na-eji ngwaike na ngwanrọ na-esonụ iji nwalee imewe exampLe:

• Intel Quartus Prime software
• Sistemụ njikwa
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL naanị), ma ọ bụ simulator VCS
• Aria 10 GX FPGA Development Kit
• HMC ada kaadị

Nkọwa ọrụ

Altera na-enye mwepụta-njikere exampya na HMC Controller IP core. Nke a imewe examplekwasịrị anya Arria 10 GX FPGA Development Kit nwere kaadị ada HMC ejikọrọ site na njikọ FMC.
Ị nwere ike iji imewe dị ka exampmaka njikọ ziri ezi nke isi IP gị na imewe gị, ma ọ bụ dị ka ihe mmalite ị nwere ike hazie maka ihe ị chọrọ ime. Imewe example na-agụnye modul master I2C, modul recalibration PLL/CDR, otu transceiver PLL IP isi, na mgbagha ịmepụta na ịlele azụmahịa. Imewe example were Micron HMC 15G-SR HMC ngwaọrụ, nke bụ fourlngwaọrụ ink, na kaadị nwa nwanyị. Imewe example gụnyere otu ihe atụ nke isi IP wee jikọọ na otu njikọ na ngwaọrụ HMC. Ọgụgụ 2-1: HMC Controller Design Example Block eserese

Mgbe ị haziela Arria 10 FPGA na imewe example, the I2C controller configures the on-board clock generators and the HMC device. When calibration completes, the design exampna-edozi ATX PLL. N'oge a na-arụ ọrụ, onye na-emepụta arịrịọ na-ewepụta iwu ịgụ na ide nke HMC Controller IP core na-ahazi. Onye nleba anya arịrịọ na-ewepụta nzaghachi sitere na isi IP wee lelee ha maka izi ezi.

Ihe nrịbama ihu
Tebụl 2-1: Onye njikwa HMC IP Core Design Example Signals

Aha mgbaàmà clk_50	Ntuziaka Ntinye	Obosara (Bits) 1	Nkọwa Elekere ntinye 50 MHz.
hssi_refclk	Ntinye	1	Elekere CDR maka HMC na HMCC IP core.

Aha mgbaàmà hmc_lxrx	Ntuziaka Ntinye	Obosara (Bits) Ọnụọgụ ọwa (16 ma ọ bụ 8)	Nkọwa FPGA transceiver receive pins.
hmc_lxtx	Mpụta	Ọnụọgụ ọwa (16 ma ọ bụ 8)	FPGA transceiver na-ebunye atụdo.
hmc_ctrl_lxrxps	Ntinye	1	Njikwa nchekwa transceiver FPGA.
hmc_ctrl_lxtxps	Mpụta	1	HMC transceiver ike nchekwa njikwa.
hmc_ctrl_ferr_n	Ntinye	1	Mmepụta HMC FERR_N.
hmc_ctrl_p_rst_n	Mpụta	1	Ntinye HMC P_RST_N.
hmc_ctrl_scl	Akụkụ abụọ	1	HMC I2C nhazi elekere.
hmc_ctrl_sda	Akụkụ abụọ	1	HMC I2C data nhazi.
fmc0_scl	Mpụta	1	Ejighi ya. Achụpụrụ ala iji chebe atụdo FPGA I/O site na mwepu 3.3 V na kaadị nwa nwanyị.
fmc0_sda	Mpụta	1	Ejighi ya. Achụpụrụ ala iji chebe atụdo FPGA I/O site na mwepu 3.3 V na kaadị nwa nwanyị.
bọtịnụ bọtịnụ	Ntinye	1	Ntinye bọtịnụ ịpị ejiri maka nrụpụta.
obi_eti_n	Mpụta	1	Mmepụta ọkụ ọkụ obi.
njikọ_init_complete_n	Mpụta	1	Mmalite njikọ zuru oke mmepụta ikanam.
ule_gafere_n	Mpụta	1	Test passed LED output.
ule_failed_n	Mpụta	1	Nwalee mmepụta ikanam dara.

Imepụta Exampna Deba aha Map
Tebụl 2-2: Onye njikwa HMC IP Core Design Exampna Deba aha Map

Idere akwụkwọ ndekọ aha ndị a na-emezigharị nhazi ahụ.

Iberibe 1:0	Aha ubi Ọnụọgụ Port	Ụdị RO	Uru na Tọgharia Na-adịgasị iche	Nkọwa Ọnụọgụ ọdụ ụgbọ mmiri maka atụ isi IP.
7:2	Echekwara	RO	0x00

Tebụl 2-4: Ndebanye aha BOARD_LED
Ndebanye aha a na-egosipụta ọkwa nke LEDs nke bọọdụ

Iberibe 0	Aha ubi Nnwale emezughị	Ụdị RO	Uru na Tọgharia 0x00	Nkọwa Nnwale dara.
1	Ule gafere	RO	0x00	Ule gafere.
2	Mmalite njikọ HMCC zuru ezu	RO	0x00	Nbido njikọ njikọ HMC zuru ezu ma dị njikere maka okporo ụzọ.
3	Obi mgbawa	RO	0x00	Na-atụgharị mgbe imewe na-agba ọsọ.
7:4	Echekwara	RO	0x00

Tebụl 2-5: Ndebanye aha TEST_INITIALIZATION_STATUS

Iberibe 0	Aha ubi Ntọala igwe elekere I2C	Ụdị RO	Uru na Tọgharia 0x00	Nkọwa Haziri ndị na-emepụta elekere n'ụgbọ.
1	ATX PLL na Transceiver Recalibration zuru ezu	RO	0x00	ATX PLL na transceivers emegharịrị na elekere ntinye.
2	I2C HMC Nhazi zuru ezu	RO	0x00	Nhazi ngwaọrụ HMC karịrị I2C zuru ezu.
3	Mmalite njikọ HMC zuru ezu	RO	0x00	Nbido njikọ njikọ HMC zuru ezu ma dị njikere maka okporo ụzọ.
7:4	Echekwara	RO	0x00

Tebụl 2-6: Ndebanye aha PORT_STATUS

Iberibe 0	Aha ubi Port 0 Arịrịọ OK	Ụdị RO	Uru na Tọgharia 0x00	Nkọwa Ọgbọ arịrịọ Port 0 zuru ezu.
1	Port 0 Azịza ya dị mma	RO	0x00	Nleba nzaghachi Port 0 gafere.
2	Port 1 Arịrịọ OK	RO	0x00	Ọgbọ arịrịọ Port 1 zuru ezu.
3	Port 1 Azịza ya dị mma	RO	0x00	Nleba nzaghachi Port 1 gafere.

Iberibe 4	Aha ubi Port 2 Arịrịọ OK	Ụdị RO	Uru na Tọgharia 0x00	Nkọwa Ọgbọ arịrịọ Port 2 zuru ezu.
5	Port 2 Azịza ya dị mma	RO	0x00	Nleba nzaghachi Port 2 gafere.
6	Port 3 Arịrịọ OK	RO	0x00	Ọgbọ arịrịọ Port 3 zuru ezu.
7	Port 4 Azịza ya dị mma	RO	0x00	Nleba nzaghachi Port 3 gafere.

Ozi Mgbakwunye

Ihe njikwa HMC ExampAkụkọ Nduzi Nduzi
Tebụl A-1: ​​Akụkọ Ndozigharị akwụkwọ
Na-achịkọta atụmatụ ọhụrụ na mgbanwe na imewe exampntuziaka onye ọrụ maka HMC Controller IP core.

Ụbọchị	Ụdị ACDS	Mgbanwe
2016.05.02	16.0	Ntọhapụ mbụ.

Otu esi akpọtụrụ Intel
Isiokwu A-2: Otu esi akpọtụrụ Intel
Iji chọta ozi kachasị ọhụrụ gbasara ngwaahịa Intel, rụtụ aka na tebụl a. Ị nwekwara ike ịkpọtụrụ ụlọ ọrụ ịre ahịa Intel ma ọ bụ onye nnọchi anya ahịa.

Kpọtụrụ	Kpọtụrụ .zọ	Adreesị
Nkwado ndị teknuzu	Websaịtị	www.altera.com/support
Ọzụzụ nka	Websaịtị	www.altera.com/training
	Email	FPGATraining@intel.com
Ngwaahịa akwụkwọ	Websaịtị	www.altera.com/literature
Nkwado na-abụghị teknụzụ: izugbe	Email	nacomp@altera.com

Kpọtụrụ   Nkwado anaghị arụ ọrụ: ikikere ngwanrọ

Kpọtụrụ .zọ   Email

Adreesị   ikike@altera.com

Ozi metụtara

• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• ikike@altera.com

Mgbakọ ụdịdị

Tebụl A-3: Mgbakọ ederede
Na-edepụta mgbakọ ederede akwụkwọ a na-eji

Akara ngosi nzaghachi na-enye gị ohere ịnye nzaghachi na Altera gbasara akwụkwọ ahụ. Ụzọ maka ịnakọta nzaghachi dịgasị iche dịka o kwesịrị ekwesị maka akwụkwọ ọ bụla

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus na Stratix okwu na akara bụ ụghalaahịa nke ụlọ ọrụ Intel ma ọ bụ ndị enyemaka ya na US na/ma ọ bụ obodo ndị ọzọ. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ
101 Innovation Drive, San Jose, CA 95134

Emelitere ikpeazụ maka Quartus Prime Design Suite: 16.0
UG-20027
2016.05.02
101 Innovation Mbanye
San Jose, CA 95134
www.altera.com

Akwụkwọ / akụrụngwa

ALTERA Arria 10 Ngwakọta ebe nchekwa Cube chepụta Example [pdf] Ntuziaka onye ọrụ Arria 10 Ngwakọ Nchekwa Cube Controller Example, Arria 10, Ngwakọ ebe nchekwa Cube njikwa imewe Example, Onye njikwa imewe Example, Imepụta Example

Ntụaka

• Akwụkwọ ntuziaka onye ọrụ