ALTERA Arria 10 Ngwakọta ebe nchekwa Cube chepụta Example

The Hybrid Memory Cube Controller Design Example User Guide provides information on the design and usage of the HMC Controller hardware design example. The guide is updated for Quartus Prime Design Suite 16.0 and was last updated on May 2, 2016.
The Design Example Quick Start Guide provides step-by-step instructions for compiling, simulating, generating, and testing the HMC Controller design example. Refer to Figure 1-1 for an overview of the development steps.

Imepụta Example Nkọwa

The HMC Controller hardware design example includes various components such as Board Arria 10 Device, HMC Controller IP Core, Clocks & Reset TX PLLs, Data Path Request Generator and Response Monitor, TX/TX FIFO MAC, RX MAC, Test Avalon-MM Control and LEDs, Controller Status Interface, Avalon-MM I 2C Master, Initialization State Machine, TX Lane Swapper, Transceiver x16, RX Lane Swapper, Arria 10 Transceiver Reconfiguration Interface, and HMC Device. The example design requires specific settings to operate properly on the Arria 10 GX FPGA Development Kit with the HMC daughter card.

Ozi Mgbakwunye

The Additional Information section provides details on the directory structure for the generated design example, the revision history of the user guide, typographic conventions used in the guide, and how to contact Intel for support.

Ntuziaka ojiji ngwaahịa

Follow the below instructions to use the HMC Controller hardware design exampLe:

1. Chịkọta imewe example using a simulator
2. Perform functional simulation
3. Mepụta imewe example
4. Chịkọta imewe example using Quartus Prime
5. Test the hardware design

Note that the hardware configuration and test files maka imewe example are located in /example_design/par, while the simulation files are located in /example_design/sim.

To help you understand how to use the Hybrid Memory Cube Controller IP core, the core features a simulatable testbench and a hardware design example nke na-akwado mkpokọta na nyocha ngwaike. Mgbe ị na-emepụta imewe example, paramita nchịkọta akụkọ na-akpaghị aka na-emepụta files necessary to simulate, compile, and test the design in hardware. You can download the compiled design to the Intel® Arria® 10 GX FPGA Development Kit.

Ozi metụtara
Hybrid Memory Cube Controller IP Core User Guide

Imepụta Exampn'akwụkwọ ndekọ aha Structure

Nhazi ngwaike na ule files (ihe nhazi ngwaike example) are located in <example_ design_install_dir>/example_design/par. The simulation files (testbench for simulation only) are located in <example_design_install_dir>/ example_design/sim.

Imepụta Exampna akụrụngwa

The HMC Controller hardware design example gụnyere ihe ndị a:

• HMC Controller IP core with CDR reference clock set to 125 MHz and with default RX mapping and TX mapping settings.
  Rịba ama: Imewe example requires these settings to operate properly on the Arria 10 GX FPGA Development Kit with the HMC daughter card.
• Echiche ndị ahịa nke na-ahazi mmemme nke isi IP, yana ọgbọ na nlele.
• JTAG controller that communicates with the Altera System Console. You communicate with the client logic through the System Console.

Lists the key files that implement the example testbench.

/src/hmcc_example.sv	Top-level hardware design example file.
/sim/hmcc_tb.sv	Ọkwa kacha file for simulation.
Ederede Testbench Mara: Use the provided Makefile to generate these scripts.
/sim/run_vsim.do	Ederede ModelSim ka ọ na-agba testbench.
/sim/run_vcs.sh	Edemede Synopsys VCS iji mee testbench.
/sim/run_ncsim.sh	Edemede Cadence NCsim iji mee testbench.

Na-emepụta ihe osise Example

Ọgụgụ 1-5: Ọpụample Design Tab in Hybrid Memory Cube Controller Parameter Editor

Follow these steps to generate the Arria 10 hardware design example na testbench:

1. In the IP Catalog (Tools > IP Catalog), select the Arria 10 target device family.
2. In the IP Catalog, locate and select Hybrid Memory Cube Controller. The New IP Variation window appears.
3. Ezipụta aha ọkwa dị elu maka ụdị IP gị nkeonwe. Onye ndezi paramita na-echekwa ntọala IP dị iche na a file aha ya .qsys.
4. You must select a specific Arria 10 device in the Device field, or keep the default device the Quartus Prime software selects.
5. Pịa OK. Ihe ndezi paramita IP na-egosi.
6. Na taabụ IP, ezipụta paramita maka mgbanwe isi IP gị.
7. Na Example Design tab, choose the following settings for the design exampLe:
   1. For Select Design, select the HMCC Daughter Board option.
   2. Maka Example Design Files, họrọ nhọrọ Simulation iji mepụta testbench, wee họrọ nhọrọ Synthesis iji mepụta ngwaike imewe ex.ample.
   3. Maka Ụdị HDL emepụtara, naanị Verilog dị.
   4. For Target Development Kit select the Arria 10 GX FPGA Development Kit (Production Silicon).
      Rịba ama: When you choose this kit, the hardware design example overwrites your previous device selection with the device on the target board. When you generate the design example, the Intel Quartus Prime software creates Intel
      Quartus Prime project, setting, and pin assignments for the board you selected. If you do not want the software to target a specific board, select None.
8. Pịa n'ịwa Example Design button

Understanding the Testbench

Altera provides an design example with the HMC Controller IP core. The design example is available both for simulation of your IP core and for compilation. The design example in simulation functions as the HMC Controller IP core testbench.
If you click Generate Example Design in the HMC Controller parameter editor, the Quartus Prime software generates a demonstration testbench. The parameter editor prompts you for the desired location of the testbench.
To simulate the testbench, you must provide your own HMC bus functional model (BFM). Altera tests the design example testbench with the Micron Hybrid Memory Cube BFM. The testbench does not include an I2C master module, because the Micron HMC BFM does not support and does not require configuration by an I2C module.
In simulation, the testbench controls a TX PLL and the data path interfaces to perform the following sequence of actions:

1. Configures the HMC BFM with the HMC Controller IP core data rate and channel width, in Response Open Loop Mode.
2. Establishes the link between the BFM and the IP core.
3. Directs each of the IP core’s four ports to write four packets of data to the BFM.
4. Directs the IP core to read back the data from the BFM.
5. Checks that the read data matches the write data.
6. If the data matches, displays TEST_PASSED.

Ịmepụta atụmatụ Exampna Testbench
Ọgụgụ 1-6: Usoro

Soro usoro ndị a ka ịmee testbench:

1. At the command line, change to the <design example>/sim directory.
2. Type make scripts.
3. Type one of the following commands, depending on your simulator:
4. Iji view simulation results:
   1. When you run the testbench in any of the three supported simulators, the script executes the testbench sequence and logs the simulator activity in <design example directory>/example_ design/sim/<simulator>.log. <simulator> is “vsim”, “ncsim”, or “vcs”.
   2. When you run the testbench in any of the three supported simulators, the script generates a waveform file. You can run the command make <simulator>_gui to load the waveform in the simulator-specific waveform viewee.
      Iji view ụdị ifegharị file in your simulator, type one of the following commands:

      Simulator License Mentor Graphics ModelSim	Ahịrị iwu make vsim_gui	Waveform File <design example directory>/example_design/sim/ mentor/hmcc_wf.wlf
      Synopsys Discovery Visual Environment	make vcs_gui	<design example directory>/example_design/sim/ hmcc_wf.vpd
      Cadence SimVision Waveform	make ncsim_gui	<design example directory>/example_design/sim/ cadence/hmcc_wf.shm
5. Analyze the results. The successful testbench sends and receives ten packets per port, and displays Test_PASSED”

Ịtọlite ​​​​bọọdụ ahụ

Set up the board to run the hardware design example.
Rịba ama: Ensure that power is turned off before you change any settings.

1. Set the DIP switches on the daughter card as follows:
2. Set DIP switch SW1 to indicate cube ID 0:
   

   Gbanwee	Ọrụ	Ịtọ ntọala
   1	CUB[0]	Mepee
   2	CUB[1]	Mepee
   3	CUB[2]	Mepee
   4	—	Echegbula

Set DIP switch SW2 to specify clock settings:

Gbanwee	Ọrụ	Ịtọ ntọala
1	CLK1_FSEL0	Open (125 MHz)
2	CLK1_FSEL1	Open (125 MHz)
3	CLK1_SEL	Open (Crystal)
4	—	Echegbula

• Connect the HMC daughter card to the Arria 10 FPGA Development Kit using the daughter card’s J8 and J10 connectors.
• Set the jumpers on the Arria 10 GX FPGA Development Kit:
• Add shunts to the J8 jumper to select 1.5 V as the VCCIO setting for FMC connector B.
• Add shunts to the J11 jumper to select 1.8 V as the VCCIO setting for FMC connector A.

Compiling and Testing the Design Exampna Hardware

To compile and run a demonstration test on the hardware design example, follow these steps

1. Gbaa mbọ hụ na imepụta ngwaike example ọgbọ agwụla.
2. In the Quartus Prime software, open the Quartus Prime project <example_design_install_dir> /example_design/par/hmcc_example.qpf.
3. In the Compilation Dashboard, click Compile Design (Intel Quartus Prime Pro Edition) or choose Processing > Start Compilation (Intel Quartus Prime Standard Edition).
4. After you generate a .sof, follow these steps to program the hardware design example na ngwaọrụ Arria 10:
   1. Choose Tools > Programmer.
   2. Na Programmer, pịa Hardware Mbido.
   3. Họrọ ngwaọrụ mmemme.
   4. Select and add the Arria 10 GX FPGA Development Kit to which your Quartus Prime session can connect.
   5. Gbaa mbọ hụ na edobere ọnọdụ na JTAG.
   6. Click Auto Detect and choose any device.
   7. Double-click the Arria 10 device.
   8. Open the .sof in <example_design_install_dir>/ example_design/par/output_ files,
      Rịba ama: The Quartus Prime software changes the device to the one in the .sof.
   9. In the row with your .sof, check the box in the Program/Configure column.
   10. Pịa Malite.
   11. After the software configures the device with the hardware design example, observe the board LEDs:
       1. A blinking red LED signifies the design is running.
       2. Two green LEDs near the red blinking LED signifies that the HMC link is initialized and the test passed.
       3. One red LED near the red blinking LED signifies that the test failed.
   12. Optional. Use the System Console testbench to observe additional test output.
       Mara: Use the System Console to monitor status signals in the design example when the board is connected to your computer via the JTAG interface. The System Console shows the board’s LED status for remote monitoring, the initialization status for each step, and the status of each port’s request generator and response checker. The System Console also provides an interface to start or re-start the test.
       1. Choose Tools > System Debugging Tools > System Console.
       2. In the System Console, choose File > Execute Script.
       3. Mepee file <example_design_install_dir>/ example_design/par/sysconsole_ testbench.tcl.
       4. The software loads graphical test output. Choose Re-start to run the test again.

Compiling and Testing the Design Exampna Hardware

Hybrid Memory Cube Controller Design

Imepụta Example Nkọwa

Imewe example demonstrates the functionality of the Hybrid Memory Cube Controller IP core. You can generate the design from the Example Design tab of the Hybrid Memory Cube Controller graphical user interface (GUI) in the IP parameter editor.

Atụmatụ

• I2C master and I2C initialization state machine for HMC daughter card and HMC configuration
• ATX PLL and transceiver recalibration state machine
• Request generator
• Request monitor
• System Console interface

Achọrọ ngwaike na ngwanrọ
Altera uses the following hardware and software to test the design exampLe:

• Intel Quartus Prime software
• Sistemụ njikwa
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL only), or VCS simulator
• Aria 10 GX FPGA Development Kit
• HMC daughter card

Nkọwa ọrụ

Altera provides a compilation-ready design example with the HMC Controller IP core. This design example targets the Arria 10 GX FPGA Development Kit with an HMC daughter card connected through the FMC connectors.
You can use the design as an example for correct connection of your IP core to your design, or as a starter design you can customize for your own design requirements. The design example includes an I2C master module, a PLL/CDR recalibration module, one external transceiver PLL IP core, and logic to generate and check transactions. The design example assumes a Micron HMC 15G-SR HMC device, which is a fourlink device, on the daughter card. The design example includes one instance of the IP core and connects to a single link on the HMC device. Figure 2-1: HMC Controller Design Example Block eserese

After you configure the Arria 10 FPGA with the design example, the I2C controller configures the on-board clock generators and the HMC device. When calibration completes, the design example calibrates the ATX PLL. During operation, the request generator generates read and write commands that the HMC Controller IP core then processes. The request monitor captures the responses from the IP core and checks them for correctness.

Ihe nrịbama ihu
Table 2-1: HMC Controller IP Core Design Example Signals

Aha mgbaàmà clk_50	Ntuziaka Ntinye	Obosara (Bits) 1	Nkọwa 50 MHz input clock.
hssi_refclk	Ntinye	1	CDR reference clock for HMC and HMCC IP core.

Aha mgbaàmà hmc_lxrx	Ntuziaka Ntinye	Obosara (Bits) Channel Count (16 ma ọ bụ 8)	Nkọwa FPGA transceiver receive pins.
hmc_lxtx	Mpụta	Channel Count (16 ma ọ bụ 8)	FPGA transceiver transmit pins.
hmc_ctrl_lxrxps	Ntinye	1	FPGA transceiver power save control.
hmc_ctrl_lxtxps	Mpụta	1	HMC transceiver power save control.
hmc_ctrl_ferr_n	Ntinye	1	HMC FERR_N output.
hmc_ctrl_p_rst_n	Mpụta	1	HMC P_RST_N input.
hmc_ctrl_scl	Akụkụ abụọ	1	HMC I2C configuration clock.
hmc_ctrl_sda	Akụkụ abụọ	1	HMC I2C configuration data.
fmc0_scl	Mpụta	1	Unused. Driven low to protect the FPGA I/O pins from the 3.3 V pullup on the daughter card.
fmc0_sda	Mpụta	1	Unused. Driven low to protect the FPGA I/O pins from the 3.3 V pullup on the daughter card.
push_button	Ntinye	1	Push button input used for reset.
heart_beat_n	Mpụta	1	Heartbeat LED output.
link_init_complete_n	Mpụta	1	Link initialization complete LED output.
test_passed_n	Mpụta	1	Test passed LED output.
test_failed_n	Mpụta	1	Test failed LED output.

Imepụta Exampna Deba aha Map
Table 2-2: HMC Controller IP Core Design Exampna Deba aha Map

Writing to these registers resets the design.

Iberibe 1:0	Aha ubi Port Count	Ụdị RO	Value on Reset Na-adịgasị iche	Nkọwa Number of ports for the IP core instance.
7:2	Echekwara	RO	0x00

Table 2-4: BOARD_LEDs Register
This register reflects the status of the board’s LEDs

Iberibe 0	Aha ubi Nnwale emezughị	Ụdị RO	Value on Reset 0x00	Nkọwa Nnwale dara.
1	Ule gafere	RO	0x00	Ule gafere.
2	HMCC Link Initialization Complete	RO	0x00	HMC link initialization complete and ready for traffic.
3	Obi mgbawa	RO	0x00	Toggles when the design is running.
7:4	Echekwara	RO	0x00

Table 2-5: TEST_INITIALIZATION_STATUS Register

Iberibe 0	Aha ubi I2C Clock Generator Set	Ụdị RO	Value on Reset 0x00	Nkọwa On- board    clock   generators configured.
1	ATX PLL and Transceiver Recalibration Complete	RO	0x00	ATX PLL and transceivers re- calibrated to the input clock.
2	I2C HMC Nhazi zuru ezu	RO	0x00	HMC device configuration over I2C complete.
3	HMC Link Initialization Complete	RO	0x00	HMC link initialization complete and ready for traffic.
7:4	Echekwara	RO	0x00

Table 2-6: PORT_STATUS Register

Iberibe 0	Aha ubi Port 0 Requests OK	Ụdị RO	Value on Reset 0x00	Nkọwa Port 0 request generation complete.
1	Port 0 Responses OK	RO	0x00	Port 0 response checking passed.
2	Port 1 Requests OK	RO	0x00	Port 1 request generation complete.
3	Port 1 Responses OK	RO	0x00	Port 1 response checking passed.

Iberibe 4	Aha ubi Port 2 Requests OK	Ụdị RO	Value on Reset 0x00	Nkọwa Port 2 request generation complete.
5	Port 2 Responses OK	RO	0x00	Port 2 response checking passed.
6	Port 3 Requests OK	RO	0x00	Port 3 request generation complete.
7	Port 4 Responses OK	RO	0x00	Port 3 response checking passed.

Ozi Mgbakwunye

HMC Controller Design ExampAkụkọ Nduzi Nduzi
Table A-1: Document Revision History
Summarizes the new features and changes in the design example user guide for the HMC Controller IP core.

Ụbọchị	ACDS Version	Mgbanwe
2016.05.02	16.0	Ntọhapụ mbụ.

How to Contact Intel
Table A-2: How to Contact Intel
To locate the most up-to-date information about Intel products, refer to this table. You can also contact your local Intel sales office or sales representative.

Kpọtụrụ	Kpọtụrụ .zọ	Adreesị
Nkwado ndị teknuzu	Websaịtị	www.altera.com/support
Ọzụzụ nka	Websaịtị	www.altera.com/training
	Email	FPGATraining@intel.com
Ngwaahịa akwụkwọ	Websaịtị	www.altera.com/literature
Nontechnical support: general	Email	nacomp@altera.com

Kpọtụrụ   Nontechnical support: software licensing

Kpọtụrụ .zọ   Email

Adreesị   authorization@altera.com

Ozi metụtara

• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• authorization@altera.com

Mgbakọ ụdịdị

Table A-3: Typographic Conventions
Lists the typographic conventions this document uses

The Feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus na Stratix okwu na akara bụ ụghalaahịa nke ụlọ ọrụ Intel ma ọ bụ ndị enyemaka ya na US na/ma ọ bụ obodo ndị ọzọ. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.
Other names and brands may be claimed as the property of others
101 Innovation Drive, San Jose, CA 95134

Emelitere ikpeazụ maka Quartus Prime Design Suite: 16.0
UG-20027
2016.05.02
101 Innovation Mbanye
San Jose, CA 95134
www.altera.com

Akwụkwọ / akụrụngwa

ALTERA Arria 10 Ngwakọta ebe nchekwa Cube chepụta Example [pdf] Ntuziaka onye ọrụ Arria 10 Ngwakọ Nchekwa Cube Controller Example, Arria 10, Hybrid Memory Cube Controller Design Example, Controller Design Example, Imepụta Example

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