ALTERA Arria 10 Hybrid Memory Cube Controller Design Example

The Hybrid Memory Cube Controller Design Example User Guide imapereka chidziwitso pamapangidwe ndi kagwiritsidwe ntchito ka HMC Controller hardware design example. Bukuli lasinthidwa ku Quartus Prime Design Suite 16.0 ndipo lidasinthidwa komaliza pa Meyi 2, 2016.
The Design Example Quick Start Guide imapereka malangizo a pang'onopang'ono pakupanga, kuyerekezera, kupanga, ndi kuyesa mawonekedwe a HMC Controller ex.ample. Onani Chithunzi 1-1 kuti mutheview za masitepe a chitukuko.

Design Example Kufotokozera

The HMC Controller hardware design example imaphatikizapo zigawo zosiyanasiyana monga Board Arria 10 Device, HMC Controller IP Core, Clocks & Reset TX PLLs, Data Path Request Generator and Response Monitor, TX/TX FIFO MAC, RX MAC, Test Avalon-MM Control ndi LEDs, Controller Status Interface , Avalon-MM I 2C Master, Initialization State Machine, TX Lane Swapper, Transceiver x16, RX Lane Swapper, Arria 10 Transceiver Reconfiguration Interface, ndi HMC Chipangizo. Exampkamangidwe kake kumafuna zoikamo kuti zizigwira bwino ntchito pa Arria 10 GX FPGA Development Kit yokhala ndi khadi yamwana wamkazi ya HMC.

Zina Zowonjezera

Gawo la Zowonjezera Zowonjezera limapereka tsatanetsatane wa dongosolo lachikwatu cha mapangidwe opangidwa kaleample, mbiri yosinthidwanso ya kalozera wogwiritsa ntchito, zolembera zomwe zimagwiritsidwa ntchito mu bukhuli, ndi momwe mungalumikizire Intel kuti akuthandizeni.

Malangizo Ogwiritsira Ntchito Zogulitsa

Tsatirani malangizo omwe ali pansipa kuti mugwiritse ntchito mawonekedwe a HMC Controller hardware exampLe:

1. Konzani zojambulazo exampndikugwiritsa ntchito simulator
2. Pangani kayeseleledwe ka ntchito
3. Pangani ex designample
4. Konzani zojambulazo exampndikugwiritsa ntchito Quartus Prime
5. Yesani kapangidwe ka zida

Dziwani kuti kasinthidwe ka hardware ndi kuyesa files kwa kapangidwe example zili mu /example_design/par, pamene kuyerekezera files zili mu /example_design/sim.

Kukuthandizani kumvetsetsa momwe mungagwiritsire ntchito Hybrid Memory Cube Controller IP pachimake, pachimake chimakhala ndi testbench yoyeserera komanso mawonekedwe a hardware.ample yomwe imathandizira kusonkhanitsa ndi kuyesa kwa hardware. Mukapanga zojambula zakaleampndi, mkonzi wa parameter amangopanga files zofunika kuyerekezera, kusonkhanitsa, ndi kuyesa mapangidwe mu hardware. Mutha kutsitsa mapangidwe omwe adapangidwa ku Intel® Arria® 10 GX FPGA Development Kit.

Zambiri Zogwirizana
Hybrid Memory Cube Controller IP Core User Guide

Design Exampndi Kapangidwe ka Directory

Kukonzekera kwa hardware ndi kuyesa files (kapangidwe ka hardware example) zili muample_ design_install_dir>/example_design/par. Kayeseleledwe files (testbench for simulation only) ali mkatiample_design_install_dir>/example_design/sim.

Design Exampndi Components

The HMC Controller hardware design example ili ndi zigawo zotsatirazi:

• HMC Controller IP core yokhala ndi wotchi ya CDR yokhazikitsidwa ku 125 MHz komanso yokhala ndi mapu a RX osasintha komanso zoikamo za mapu a TX.
  Zindikirani: Mapangidwe example imafuna kuti zosinthazi zizigwira ntchito bwino pa Arria 10 GX FPGA Development Kit yokhala ndi khadi yamwana wamkazi ya HMC.
• Lingaliro la kasitomala lomwe limagwirizanitsa mapulogalamu a IP core, ndi kupanga mapaketi ndikuwunika.
• JTAG wolamulira yemwe amalumikizana ndi Altera System Console. Mumalumikizana ndi malingaliro a kasitomala kudzera mu System Console.

Imatchula fungulo files zomwe zimagwiritsa ntchito exampndi testbench.

/src/hmcc_exampndi.sv	Mapangidwe apamwamba a hardware example file.
/sim/hmcc_tb.sv	Pamwambamwamba file kwa kayeseleledwe.
Zolemba za Testbench Zindikirani: Gwiritsani ntchito Make yoperekedwafile kupanga zolemba izi.
/sim/run_vsim.do	The ModelSim script kuyendetsa testbench.
/sim/run_vcs.sh	Synopsys VCS script yoyendetsa testbench.
/sim/run_ncsim.sh	The Cadence NCSim script kuyendetsa testbench.

Kupanga Design Example

Chithunzi 1-5: Eksampndi Design Tab mu Hybrid Memory Cube Controller Parameter Editor

Tsatirani izi kuti mupange Arria 10 hardware design example ndi testbench:

1. Mu IP Catalog (Zida> IP Catalog), sankhani banja la chipangizo chandamale cha Arria 10.
2. Mu IP Catalog, pezani ndikusankha Hybrid Memory Cube Controller. Zenera la New IP Variation likuwonekera.
3. Tchulani dzina lapamwamba lamitundu yanu ya IP. Mkonzi wa parameter amasunga zosintha za IP mu a file dzina .qsys.
4. Muyenera kusankha chipangizo china cha Arria 10 pagawo la Chipangizo, kapena sungani chipangizo chokhazikika chomwe pulogalamu ya Quartus Prime imasankha.
5. Dinani Chabwino. IP parameter editor ikuwonekera.
6. Pa tabu ya IP, tchulani magawo akusintha kwanu kwa IP.
7. Pa Eksample Design tabu, sankhani makonda otsatirawa a kapangidwe kakaleampLe:
   1. Pakuti Sankhani Design, kusankha HMCC Daughter Board mwina.
   2. Za Eksampndi Design Files, sankhani njira yoyeserera kuti mupange testbench, ndikusankha njira ya kaphatikizidwe kuti mupange kapangidwe ka Hardware ex.ample.
   3. Kwa Mtundu Wopangidwa wa HDL, Verilog yokha ndiyomwe ikupezeka.
   4. Kwa Target Development Kit sankhani Arria 10 GX FPGA Development Kit (Silicon Yopanga).
      Zindikirani: Mukasankha zida izi, kapangidwe ka hardware kaleample imalembanso zomwe mwasankha m'mbuyomu ndi chipangizo chomwe chili pagulu lomwe mukufuna. Mukapanga zojambula zakaleampndi, pulogalamu ya Intel Quartus Prime imapanga Intel
      Pulojekiti ya Quartus Prime, kukhazikitsa, ndi mapini magawo a bolodi yomwe mwasankha. Ngati simukufuna kuti pulogalamuyo igwirizane ndi bolodi inayake, sankhani Palibe.
8. Dinani Pangani Exampndi Design batani

Kumvetsetsa Testbench

Altera imapereka chithunzithunzi choyambiriraampndi HMC Controller IP pachimake. Mapangidwe example likupezeka poyerekezera ndi IP core yanu komanso kuphatikiza. Mapangidwe example mu kayeseleledwe ntchito monga HMC Controller IP core testbench.
Mukadina Pangani Exampndi Design mu HMC Controller parameter editor, pulogalamu ya Quartus Prime imapanga testbench yowonetsera. Mkonzi wa parameter amakupangitsani malo omwe mukufuna testbench.
Kuti muyesere testbench, muyenera kupereka mtundu wanu wa HMC bus functional model (BFM). Altera amayesa kapangidwe kakaleampndi testbench ndi Micron Hybrid Memory Cube BFM. Testbench sichimaphatikizapo I2C master module, chifukwa Micron HMC BFM sichirikiza ndipo sichifuna kusinthidwa ndi gawo la I2C.
Poyerekeza, testbench imayang'anira TX PLL ndi njira yolumikizira data kuti ichite zotsatirazi:

1. Imakonza HMC BFM ndi HMC Controller IP core data rate ndi makulidwe a tchanelo, mu Response Open Loop Mode.
2. Imakhazikitsa ulalo pakati pa BFM ndi IP core.
3. Imawongolera madoko anayi aliwonse a IP kuti alembe mapaketi anayi a data ku BFM.
4. Imawongolera IP core kuti iwerengenso zomwe zachokera ku BFM.
5. Imawunika ngati data yowerengedwa ikufanana ndi zomwe zalembedwa.
6. data ikafanana, imawonetsa TEST_PASSED.

Kutsanzira Design Exampndi Testbench
Chithunzi 1-6: Ndondomeko

Tsatirani izi kuti muyesere testbench:

1. Pa mzere wolamula, sinthani ku fayilo yaample>/sim directory.
2. Lembani make scripts.
3. Lembani limodzi mwamalamulo awa, kutengera simulator yanu:
4. Ku view zotsatira zoyerekeza:
   1. Mukayendetsa testbench muzoyeseza zitatu zomwe zimathandizidwa, script imachita mndandanda wa testbench ndikulowetsa ntchito yoyeserera mu.ample directory>/example_ design/sim/ .logi. ndi “vsim”, “ncsim”, kapena “vcs”.
   2. Mukayendetsa testbench muzoyimira zitatu zomwe zimathandizidwa, script imapanga mawonekedwe file. Mutha kuyendetsa command make _gui kukweza mawonekedwe a waveform mu mawonekedwe a simulator-enieni viewer.
      Ku view mawonekedwe a waveform file mu simulator yanu, lembani limodzi mwa malamulo awa:

      License ya Simulator Mentor Graphics ModelSim	Command Line kupanga vsim_gui	Waveform File <design exampndi directory>/example_design/sim/ mentor/hmcc_wf.wlf
      Synopsys Discovery Visual Environment	kupanga vcs_gui	<design exampndi directory>/example_design/sim/ hmcc_wf.vpd
      Cadence SimVision Waveform	kupanga ncsim_gui	<design exampndi directory>/example_design/sim/cadence/hmcc_wf.shm
5. Unikani zotsatira. Testbench yopambana imatumiza ndikulandila mapaketi khumi padoko, ndikuwonetsa Test_PASSED ”

Kupanga Bungwe

Khazikitsani bolodi kuti mugwiritse ntchito mawonekedwe a hardware example.
Zindikirani: Onetsetsani kuti mphamvu yazimitsidwa musanasinthe makonda aliwonse.

1. Khazikitsani masiwichi a DIP pa khadi la mwana wamkazi motere:
2. Khazikitsani kusintha kwa DIP SW1 kuti muwonetse ID ya cube 0:
   

   Sinthani	Ntchito	Kukhazikitsa
   1	CUB[0]	Tsegulani
   2	CUB[1]	Tsegulani
   3	CUB[2]	Tsegulani
   4	—	Osasamala

Khazikitsani masinthidwe a DIP SW2 kuti mutchule makonda a wotchi:

Sinthani	Ntchito	Kukhazikitsa
1	CLK1_FSEL0	Yotsegula (125 MHz)
2	CLK1_FSEL1	Yotsegula (125 MHz)
3	CLK1_SEL	Tsegulani (Crystal)
4	—	Osasamala

• Lumikizani khadi la mwana wamkazi la HMC ku Arria 10 FPGA Development Kit pogwiritsa ntchito zolumikizira za J8 ndi J10 za khadilo.
• Khazikitsani zodumphira pa Arria 10 GX FPGA Development Kit:
• Onjezani ma shunts ku J8 jumper kuti musankhe 1.5 V ngati VCCIO cholumikizira cha FMC B.
• Onjezani ma shunts ku J11 jumper kuti musankhe 1.8 V ngati VCCIO makonda a FMC cholumikizira A.

Kulemba ndi Kuyesa Design Exampndi mu Hardware

Kupanga ndikuyesa mayeso owonetsa pamapangidwe a Hardware example, tsatirani izi

1. Onetsetsani kuti hardware kapangidwe example generation yatha.
2. Mu pulogalamu ya Quartus Prime, tsegulani polojekiti ya Quartus Primeample_design_install_dir> /example_design/par/hmcc_exampndi.qpf.
3. Mu Commilation Dashboard, dinani Compile Design (Intel Quartus Prime Pro Edition) kapena sankhani Kukonzekera> Yambani Kuphatikiza (Intel Quartus Prime Standard Edition).
4. Mukapanga a .sof, tsatirani izi kuti mukonze mawonekedwe a hardware example pa chipangizo cha Arria 10:
   1. Sankhani Zida> Wopanga mapulogalamu.
   2. Mu Programmer, dinani Hardware Setup.
   3. Sankhani chipangizo chokonzera.
   4. Sankhani ndikuwonjezera Arria 10 GX FPGA Development Kit komwe gawo lanu la Quartus Prime lingalumikizidwe.
   5. Onetsetsani kuti Mode yakhazikitsidwa ku JTAG.
   6. Dinani Auto Detect ndikusankha chipangizo chilichonse.
   7. Dinani kawiri chipangizo cha Arria 10.
   8. Tsegulani .sof mkatiample_design_install_dir>/example_design/par/output_ files,
      Zindikirani: Pulogalamu ya Quartus Prime imasintha chipangizochi kukhala chomwe chili mu .sof.
   9. Mumzere ndi .sof yanu, fufuzani bokosi mu gawo la Pulogalamu/Sinthani.
   10. Dinani Yambani.
   11. Pambuyo mapulogalamu configures chipangizo ndi hardware kapangidwe exampLero, onani ma LED a board:
       1. Kuthwanima kofiira kwa LED kumatanthawuza kuti mapangidwe akuyenda.
       2. Ma LED awiri obiriwira pafupi ndi kuwala kofiyira kwa LED akuwonetsa kuti ulalo wa HMC umayambika ndipo mayeso adadutsa.
       3. LED imodzi yofiyira pafupi ndi kuwala kofiyira kwa LED ikuwonetsa kuti kuyesa kwalephera.
   12. Zosankha. Gwiritsani ntchito testbench ya System Console kuti muwone zotulukapo zowonjezera.
       Zindikirani: Gwiritsani ntchito System Console kuti muyang'anire ma siginali mu kapangidwe kakaleample pamene bolodi yolumikizidwa ndi kompyuta yanu kudzera pa JTAG mawonekedwe. The System Console ikuwonetsa mawonekedwe a board a LED pakuwunika kwakutali, momwe amayambira pa sitepe iliyonse, komanso momwe jenereta yofunsira padoko lililonse ndi chowunikira mayankho. The System Console imaperekanso mawonekedwe oyambira kapena kuyambitsanso mayeso.
       1. Sankhani Zida> Zida Zowonongeka Zowonongeka> System Console.
       2. Mu System Console, sankhani File > Pangani Script.
       3. Tsegulani file <example_design_install_dir>/example_design/par/sysconsole_ testbench.tcl.
       4. Pulogalamuyi imadzaza zotuluka zoyeserera. Sankhani Yambitsaninso kuti muyesenso.

Kulemba ndi Kuyesa Design Exampndi mu Hardware

Mapangidwe a Hybrid Memory Cube Controller

Design Example Kufotokozera

Mapangidwe example akuwonetsa magwiridwe antchito a Hybrid Memory Cube Controller IP pachimake. Mutha kupanga mapangidwe kuchokera ku Example Design tabu ya Hybrid Memory Cube Controller graphical user interface (GUI) mu IP parameter editor.

Mawonekedwe

• I2C master ndi I2C makina oyambitsa boma a HMC khadi ya mwana wamkazi ndi kasinthidwe ka HMC
• ATX PLL ndi makina a transceiver recalibration state
• Pemphani jenereta
• Pemphani polojekiti
• Mawonekedwe a System Console

Zofunikira pa Hardware ndi Mapulogalamu
Altera amagwiritsa ntchito zida ndi mapulogalamu otsatirawa kuyesa kapangidwe kakaleampLe:

• Intel Quartus Prime software
• System Console
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL yokha), kapena simulator ya VCS
• Arria 10 GX FPGA Development Kit
• Khadi la mwana wamkazi wa HMC

Kufotokozera Kwantchito

Altera imapereka mawonekedwe okonzeka kupanga kaleampndi HMC Controller IP pachimake. Mapangidwe awa example imayang'ana Arria 10 GX FPGA Development Kit yokhala ndi khadi yamwana wamkazi ya HMC yolumikizidwa kudzera pa zolumikizira za FMC.
Mutha kugwiritsa ntchito kapangidwe kake ngati example kuti mulumikizane bwino ndi IP core yanu pamapangidwe anu, kapena ngati choyambira mutha kusintha makonda anu kuti agwirizane ndi kapangidwe kanu. Mapangidwe example ikuphatikizapo I2C master module, PLL/CDR recalibration module, transceiver imodzi yakunja ya PLL IP core, ndi malingaliro opanga ndi kufufuza zochitika. Mapangidwe example amatenga chipangizo cha Micron HMC 15G-SR HMC, chomwe ndi fourlchipangizo cha inki, pa khadi la mwana wamkazi. Mapangidwe example imaphatikizapo chitsanzo chimodzi cha IP core ndikugwirizanitsa ndi ulalo umodzi pa chipangizo cha HMC. Chithunzi 2-1: HMC Controller Design Exampndi Block Diagram

Mukakonza Arria 10 FPGA ndi kapangidwe kakaleample, wolamulira wa I2C amakonza ma jenereta a wotchi pa bolodi ndi chipangizo cha HMC. Kukonzekera kukamaliza, mapangidwe a exampndi kuwerengera ATX PLL. Panthawi yogwira ntchito, jenereta yopemphayo imapanga malamulo owerengera ndi kulemba omwe HMC Controller IP core ndiye amachititsa. Woyang'anira zopempha amatenga mayankho kuchokera pachimake cha IP ndikuwunika kuti ndiwolondola.

Zizindikiro za Interface
Table 2-1: HMC Controller IP Core Design Exampndi Signals

Dzina la Signal clk_50	Mayendedwe Zolowetsa	M'lifupi (Bits) 1	Kufotokozera 50 MHz wotchi yolowera.
hssi_refclk	Zolowetsa	1	CDR yolozera wotchi ya HMC ndi HMCC IP pachimake.

Dzina la Signal hmc_lxrx	Mayendedwe Zolowetsa	M'lifupi (Bits) Chiwerengero cha Channel (16 kapena 8)	Kufotokozera FPGA transceiver amalandila zikhomo.
hmc_lxtx	Zotulutsa	Chiwerengero cha Channel (16 kapena 8)	FPGA transceiver transmit pins.
hmc_ctrl_lxrxps	Zolowetsa	1	FPGA transceiver power save control.
hmc_ctrl_lxtxps	Zotulutsa	1	HMC transceiver power save control.
hmc_ctrl_ferr_n	Zolowetsa	1	Kutulutsa kwa HMC FERR_N.
hmc_ctrl_p_rst_n	Zotulutsa	1	Kulowetsa kwa HMC P_RST_N.
hmc_ctrl_scl	Bi-Directional	1	Wotchi yosinthira ya HMC I2C.
hmc_ctrl_sda	Bi-Directional	1	Zosintha za HMC I2C.
fmc0_scl	Zotulutsa	1	Zosagwiritsidwa ntchito. Kuyendetsedwa motsika kuti muteteze zikhomo za FPGA I/O ku 3.3 V kukoka pa khadi la mwana wamkazi.
fmc0_sda	Zotulutsa	1	Zosagwiritsidwa ntchito. Kuyendetsedwa motsika kuti muteteze zikhomo za FPGA I/O ku 3.3 V kukoka pa khadi la mwana wamkazi.
kukankha_batani	Zolowetsa	1	Dinani batani lolowera lomwe likugwiritsidwa ntchito pokonzanso.
mtima_kugunda_n	Zotulutsa	1	Kutulutsa kwa LED kwa Heartbeat.
link_init_complete_n	Zotulutsa	1	Kukhazikitsa kwa ulalo kumamaliza kutulutsa kwa LED.
test_passd_n	Zotulutsa	1	Kuyesa kwadutsa kutulutsa kwa LED.
kuyesa_kulephera_n	Zotulutsa	1	Kuyesa kwalephera kutulutsa kwa LED.

Design Exampndi Register Mapu
Table 2-2: HMC Controller IP Core Design Exampndi Register Mapu

Kulembera ku zolembera izi kukonzanso mapangidwe.

Bits 1:0	Dzina lamunda Port Count	Mtundu RO	Mtengo pa Reset Zimasiyana	Kufotokozera Chiwerengero cha madoko amtundu wa IP core.
7:2	Zosungidwa	RO	0x00 pa

Gulu 2-4: Kulembetsa kwa BOARD_LED
Kaundulayu akuwonetsa momwe ma LED aku board

Bits 0	Dzina lamunda Mayeso Alephera	Mtundu RO	Mtengo pa Reset 0x00 pa	Kufotokozera Mayeso alephera.
1	Mayeso Adutsa	RO	0x00 pa	Mayeso adutsa.
2	HMCC Link Initialization Yamaliza	RO	0x00 pa	Kukhazikitsa kwa ulalo wa HMC kwatha ndipo kokonzekera kuchuluka kwa magalimoto.
3	Kugunda kwa mtima	RO	0x00 pa	Imasintha pamene mapangidwe akugwira ntchito.
7:4	Zosungidwa	RO	0x00 pa

Gulu 2-5: Lembani TEST_INITIALIZATION_STATUS

Bits 0	Dzina lamunda I2C Clock Generator Set	Mtundu RO	Mtengo pa Reset 0x00 pa	Kufotokozera Ma jenereta a wotchi akonzedwa.
1	ATX PLL ndi Transceiver Recalibration Complete	RO	0x00 pa	ATX PLL ndi ma transceivers adasinthidwanso ku wotchi yolowera.
2	I2C HMC Kukonza Kwatha	RO	0x00 pa	Kusintha kwa chipangizo cha HMC pa I2C kwatha.
3	HMC Link Initialization Yamaliza	RO	0x00 pa	Kukhazikitsa kwa ulalo wa HMC kwatha ndipo kokonzekera kuchuluka kwa magalimoto.
7:4	Zosungidwa	RO	0x00 pa

Gulu 2-6: PORT_STATUS Register

Bits 0	Dzina lamunda Port 0 Amapempha OK	Mtundu RO	Mtengo pa Reset 0x00 pa	Kufotokozera Port 0 pempho lamaliza.
1	Mayankho a Port 0 OK	RO	0x00 pa	Kuwunika kwa mayankho a Port 0 kwadutsa.
2	Port 1 Amapempha OK	RO	0x00 pa	Port 1 pempho lamaliza.
3	Mayankho a Port 1 OK	RO	0x00 pa	Kuwunika kwa mayankho a Port 1 kwadutsa.

Bits 4	Dzina lamunda Port 2 Amapempha OK	Mtundu RO	Mtengo pa Reset 0x00 pa	Kufotokozera Port 2 pempho lamaliza.
5	Mayankho a Port 2 OK	RO	0x00 pa	Kuwunika kwa mayankho a Port 2 kwadutsa.
6	Port 3 Amapempha OK	RO	0x00 pa	Port 3 pempho lamaliza.
7	Mayankho a Port 4 OK	RO	0x00 pa	Kuwunika kwa mayankho a Port 3 kwadutsa.

Zina Zowonjezera

HMC Controller Design Exampndi Mbiri Yokonzanso Buku Logwiritsa Ntchito
Gulu A-1: ​​Mbiri Yokonzanso Zolemba
Imafotokozera mwachidule za zatsopano ndi kusintha kwa kapangidwe kakaleampkalozera wogwiritsa ntchito pa HMC Controller IP core.

Tsiku	Chithunzi cha ACDS	Zosintha
2016.05.02	16.0	Kutulutsidwa koyamba.

Momwe mungalumikizire Intel
Table A-2: Momwe mungalumikizire Intel
Kuti mupeze zambiri zaposachedwa kwambiri zazinthu za Intel, onani tebulo ili. Mutha kulumikizananso ndi ofesi ya Intel yogulitsa kwanuko kapena woyimira malonda.

Contact	Njira Yothandizira	Adilesi
Othandizira ukadaulo	Webmalo	www.altera.com/support
Maphunziro aukadaulo	Webmalo	www.altera.com/training
	Imelo	FPGATraining@intel.com
Zolemba zamalonda	Webmalo	www.altera.com/literature
Thandizo lopanda luso: zonse	Imelo	nacomp@altera.com

Contact   Thandizo lopanda ukadaulo: chilolezo cha pulogalamu

Njira Yothandizira   Imelo

Adilesi   authorization@altera.com

Zambiri Zogwirizana

• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• authorization@altera.com

Misonkhano Yakulembera

Table A-3: Misonkhano Yachilembedwe
Imatchula za kalembedwe kalembedwe kachikalatachi

Chizindikiro cha Feedback chimakupatsani mwayi wotumiza ndemanga ku Altera za chikalatacho. Njira zosonkhanitsira ndemanga zimasiyanasiyana malinga ndi chikalata chilichonse

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus ndi Stratix mawu ndi logo ndi zizindikiro za Intel Corporation kapena mabungwe ake ku US ndi/kapena mayiko ena. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.
Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena
101 Innovation Drive, San Jose, CA 95134

Kusinthidwa komaliza kwa Quartus Prime Design Suite: 16.0
UG-20027
2016.05.02
101 Drive Drive
San Jose, CA 95134
www.altera.com

Zolemba / Zothandizira

ALTERA Arria 10 Hybrid Memory Cube Controller Design Example [pdf] Buku Logwiritsa Ntchito Arria 10 Hybrid Memory Cube Controller Design Example, Arria 10, Hybrid Memory Cube Controller Design Exampndi, Controller Design Exampndi, Design Example

Maumboni

• Buku Logwiritsa Ntchito