ALTERA Arria 10 Hybrid Memory Cube Controller Design Example

Moralo oa Hybrid Memory Cube Controller Example Bukana ea Mosebelisi e fana ka leseli mabapi le moralo le ts'ebeliso ea moralo oa lisebelisoa tsa HMC Controller example. Tataiso e nchafalitsoe bakeng sa Quartus Prime Design Suite 16.0 mme e qetetse ho ntlafatsoa ka la 2 Mots'eanong 2016.
Moqapi ExampLe Quick Start Guide e fana ka litaelo tsa mohato ka mohato bakeng sa ho bokella, ho etsisa, ho hlahisa, le ho lekola moralo oa HMC Controller ex.ample. Sheba setšoantšo sa 1-1 bakeng sa ho fetaview ea mehato ea ntlafatso.

Moqapi Example Tlhaloso

The HMC Controller hardware design example e kenyelletsa likarolo tse fapaneng tse kang Board Arria 10 Device, HMC Controller IP Core, Clocks & Reset TX PLLs, Data Path Request Generator le Response Monitor, TX/TX FIFO MAC, RX MAC, Test Avalon-MM Control le LEDs, Controller Status Interface. , Avalon-MM I 2C Master, Initialization State Machine, TX Lane Swapper, Transceiver x16, RX Lane Swapper, Arria 10 Transceiver Reconfiguration Interface, le HMC Device. Example moralo o hloka litlhophiso tse ikhethileng hore li sebetse hantle ho Arria 10 GX FPGA Development Kit ka karete ea morali ea HMC.

Tlhahisoleseling e 'Ngoe

Karolo ea Boitsebiso ba Tlatsetso e fana ka lintlha tse mabapi le sebopeho sa directory bakeng sa moralo o hlahisitsoeng example, nalane ea ntlafatso ea tataiso ea basebelisi, litumellano tsa typographic tse sebelisitsoeng ho tataiso, le mokhoa oa ho ikopanya le Intel bakeng sa ts'ehetso.

Litaelo tsa Tšebeliso ea Sehlahisoa

Latela litaelo tse ka tlase ho sebelisa HMC Controller hardware design exampLe:

1. Kopanya moralo exampke sebelisa simulator
2. Etsa ketsiso e sebetsang
3. Hlahisa sebopeho sa mohlalaample
4. Kopanya moralo example sebelisa Quartus Prime
5. Lekola moralo oa lisebelisoa

Hlokomela hore tlhophiso ea hardware le teko files bakeng sa moralo example li fumaneha ho /example_design/par, ha ketsiso files li fumaneha ho /example_design/sim.

Ho u thusa ho utloisisa mokhoa oa ho sebelisa Hybrid Memory Cube Controller IP core, mantlha e na le testbench e ts'oanang le moralo oa lisebelisoa tsa khale.ample e tšehetsang ho bokella le ho hlahloba hardware. Ha o hlahisa moqapi example, mohlophisi oa parameter o iketsetsa faele ea files bohlokoa ho etsisa, ho bokella, le ho leka moralo ho hardware. U ka khoasolla moralo o hlophisitsoeng ho Intel® Arria® 10 GX FPGA Development Kit.

Lintlha Tse Amanang
Hybrid Memory Cube Controller IP Core User Guide

Moqapi Example Sebopeho sa Directory

Sebopeho sa hardware le teko files (moralo oa hardware example) li fumaneha hoample_ design_install_dir>/example_design/par. Ketsiso files (testbench bakeng sa ketsiso feela) li tengample_design_install_dir>/example_design/sim.

Moqapi Example Likarolo

The HMC Controller hardware design example kenyeletsa likarolo tse latelang:

• HMC Controller IP core e nang le oache ea litšupiso ea CDR e behiloeng ho 125 MHz le ka 'mapa oa kamehla oa RX le litlhophiso tsa 'mapa tsa TX.
  Hlokomela: Moqapi oa mohlalaample hloka hore litlhophiso tsena li sebetse hantle ho Arria 10 GX FPGA Development Kit ka karete ea morali ea HMC.
• Monahano oa bareki o hokahanyang mananeo a mantlha a IP, le tlhahiso ea lipakete le ho hlahloba.
• JTAG molaoli ea buisanang le Altera System Console. U buisana le logic ea bareki ka System Console.

E thathamisa senotlolo files tse phethahatsang example testbench.

/src/hmcc_example.sv	Moqapi oa lisebelisoa tsa boemo bo holimo example file.
/sim/hmcc_tb.sv	Boemo bo holimo file bakeng sa ketsiso.
Litemana tsa Testbench Hlokomela: Sebelisa Makeke e fanoengfile ho hlahisa mangolo ana.
/sim/run_vsim.do	Sengoloa sa ModelSim ho tsamaisa testbench.
/sim/run_vcs.sh	Mongolo oa Synopsys VCS ho tsamaisa testbench.
/sim/run_ncsim.sh	Sengoloa sa Cadence NCSim ho tsamaisa testbench.

Ho Hlahisa Moqapi Example

Setšoantšo sa 1-5: Example Design Tab ho Hybrid Memory Cube Controller Parameter Editor

Latela mehato ena ho hlahisa Arria 10 hardware design example le testbench:

1. Ka IP Catalog (Lisebelisoa> IP Catalog), khetha lelapa la sesebelisoa sa sepheo sa Arria 10.
2. Ho IP Catalog, fumana 'me u khethe Hybrid Memory Cube Controller. Ho hlaha fensetere e ncha ea IP Variation.
3. Hlalosa lebitso la boemo bo holimo bakeng sa IP ea hau ea tloaelo. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .qsys.
4. U tlameha ho khetha sesebelisoa se itseng sa Arria 10 tšimong ea Sesebelisoa, kapa u boloke sesebelisoa sa kamehla seo software ea Quartus Prime e se khethang.
5. Tobetsa OK. IP parameter editor ea hlaha.
6. Ho tab ea IP, hlakisa li-parameter tsa IP ea hau ea mantlha.
7. Ho Example Design tab, khetha li-setting tse latelang bakeng sa mohlala oa moraloampLe:
   1. Bakeng sa Khetha Design, khetha HMCC Daughter Board kgetho.
   2. Bakeng sa Example Design Files, khetha Simulation kgetho ho hlahisa testbench, 'me khetha Synthesis kgetho ho hlahisa hardware moralo ex.ample.
   3. Bakeng sa Format ea HDL e hlahisitsoeng, ke Verilog feela e fumanehang.
   4. Bakeng sa Target Development Kit khetha Arria 10 GX FPGA Development Kit (Production Silicon).
      Hlokomela: Ha u khetha kit ena, moralo oa hardware example overwrites sesebediswa hao fetileng kgetho le sesebediswa ka shebiloeng boto. Ha o hlahisa moqapi example, software ea Intel Quartus Prime e theha Intel
      Quartus Prime projeke, tlhophiso, le likabelo tsa phini bakeng sa boto eo u e khethileng. Haeba u sa batle hore software e shebane le boto e itseng, khetha None.
8. Tobetsa Hlahisa Example konopo ea Design

Ho utloisisa Testbench

Altera e fana ka mohlala oa moraloample HMC Controller IP konokono. Moqapi example e fumaneha ka bobeli bakeng sa papiso ea mantlha ea hau ea IP le ho e bokella. Moqapi example mesebetsing ea ketsiso e le HMC Controller IP core testbench.
Haeba u tobetsa Hlahisa Example Design ho HMC Controller parameter editor, software ea Quartus Prime e hlahisa pontšo ea testbench. Mohlophisi oa parameter o u khothalletsa hore u fumane sebaka se lakatsehang sa testbench.
Ho etsisa testbench, o tlameha ho fana ka mohlala oa hau o sebetsang oa libese oa HMC (BFM). Altera e leka mohlala oa moraloample testbench e nang le Micron Hybrid Memory Cube BFM. Testbench ha e kenye module ea master ea I2C, hobane Micron HMC BFM ha e tšehetse ebile ha e hloke ho hlophisoa ke module ea I2C.
Ka papiso, testbench e laola TX PLL le marang-rang a tsela ea data ho etsa tatellano e latelang ea liketso:

1. E lokisa HMC BFM ka HMC Controller IP sekgahla sa data le bophara ba kanale, ho Response Open Loop Mode.
2. E theha khokahano lipakeng tsa BFM le IP core.
3. E laela e 'ngoe le e 'ngoe ea likou tse 'ne tsa IP ho ngola lipakete tse nne tsa data ho BFM.
4. E tsamaisa setsi sa IP ho bala lintlha tse tsoang ho BFM.
5. E hlahloba hore na data e baliloeng e lumellana le data e ngoloang.
6. Haeba data e lumellana, e hlahisa TEST_PASSED.

Ho Etsisa Moralo Example Testbench
Setšoantšo sa 1-6: Mokhoa

Latela mehato ena ho etsisa testbench:

1. Moleng oa taelo, fetola hoample>/sim directory.
2. Tlanya ho etsa script.
3. Ngola e 'ngoe ea litaelo tse latelang, ho latela simulator ea hau:
4. Ho view liphetho tsa ketsiso:
   1. Ha o tsamaisa testbench ho e 'ngoe ea li-simulator tse tharo tse tšehetsoeng, sengoloa se etsa tatellano ea liteko ebe se kenya tšebetsong ea simulator ho.ample directory>/example_ design/sim/ .log. ke “vsim”, “ncsim”, kapa “vcs”.
   2. Ha o tsamaisa testbench ho leha e le efe ea li-simulator tse tharo tse tšehetsoeng, script e hlahisa waveform file. U ka tsamaisa taelo etsa _gui ho kenya waveform ka har'a sebopeho se ikhethileng sa simulator viewer.
      Ho view sebopeho sa maqhubu file ho simulator ea hau, ngola e 'ngoe ea litaelo tse latelang:

      License ea Simulator Mentor Graphics ModelSim	Mola oa Taelo etsa vsim_gui	Sebopeho sa maqhubu File <design example directory>/mohlample_design/sim/ mentor/hmcc_wf.wlf
      Synopsys Discovery Tikoloho ea Pono	etsa vcs_gui	<design example directory>/mohlample_design/sim/ hmcc_wf.vpd
      Cadence SimVision Waveform	etsa ncsim_gui	<design example directory>/mohlample_design/sim/ cadence/hmcc_wf.shm
5. Sekaseka liphello. Testbench e atlehileng e romela le ho amohela lipakete tse leshome ka koung, 'me e bonts'a Test_PASSED”

Ho theha Boto

Beha boto ho tsamaisa moralo oa hardware example.
Hlokomela: Netefatsa hore motlakase o timiloe pele o fetola litlhophiso life kapa life.

1. Beha li-switches tsa DIP kareteng ea morali ka tsela e latelang:
2. Seta switjha ya DIP SW1 ho bontsha cube ID 0:
   

   Fetoha	Mosebetsi	Tlhophiso
   1	KUB[0]	Bula
   2	KUB[1]	Bula
   3	KUB[2]	Bula
   4	—	Se tsotelle

Beha switjha ea DIP SW2 ho hlakisa litlhophiso tsa oache:

Fetoha	Mosebetsi	Tlhophiso
1	CLK1_FSEL0	Bula (125 MHz)
2	CLK1_FSEL1	Bula (125 MHz)
3	CLK1_SEL	Bula (Crystal)
4	—	Se tsotelle

• Hokela karete ea morali ea HMC ho Arria 10 FPGA Development Kit u sebelisa lihokelo tsa J8 le J10 tsa karete ea morali.
• Beha li-jumpers ho Arria 10 GX FPGA Development Kit:
• Kenya li-shunts ho jumper ea J8 ho khetha 1.5 V e le boemo ba VCCIO bakeng sa sehokelo sa FMC B.
• Kenya li-shunts ho jumper ea J11 ho khetha 1.8 V e le boemo ba VCCIO bakeng sa sehokelo sa FMC A.

Ho Kopanya le ho Leka Moralo Example ho Hardware

Ho bokella le ho etsa tlhahlobo ea pontšo mabapi le moralo oa hardware example, latela mehato ena

1. Netefatsa moralo oa hardware example moloko o felile.
2. Ho software ea Quartus Prime, bula morero oa Quartus Primeample_design_install_dir> /example_design/par/hmcc_example.qpf.
3. Ka har'a Dashboard ea Kopano, tlanya Moqapi oa Kopanya (Intel Quartus Prime Pro Edition) kapa khetha Ho sebetsa> Qala ho Kopanya (Intel Quartus Prime Standard Edition).
4. Ka mor'a hore u hlahise .sof, latela mehato ena ho hlophisa moralo oa hardware example sesebelisoa sa Arria 10:
   1. Khetha Lisebelisoa> Lenaneo.
   2. Ho "Programmer", tobetsa "Hardware Setup".
   3. Khetha sesebelisoa sa ho etsa mananeo.
   4. Khetha 'me u kenye Arria 10 GX FPGA Development Kit eo karolo ea hau ea Quartus Prime e ka hokelang ho eona.
   5. Netefatsa hore Mode e setetsoe ho JTAG.
   6. Tobetsa Auto Detect ebe u khetha sesebelisoa leha e le sefe.
   7. Tobetsa habeli sesebelisoa sa Arria 10.
   8. Bula .sof inample_design_install_dir>/example_design/par/output_ files,
      Hlokomela: Software ea Quartus Prime e fetola sesebelisoa ho ea ho .sof.
   9. Moleng o nang le .sof ea hau, hlahloba lebokose ho Lenaneo/Configure kholomo.
   10. Tobetsa Qala.
   11. Kamora hore software e hlophise sesebelisoa se nang le moralo oa hardware example, hlokomela li-LED tsa boto:
       1. LED e khubelu e benyang e bolela hore moralo oa sebetsa.
       2. Li-LED tse peli tse tala haufi le LED e benyang e khubelu li bontša hore sehokelo sa HMC se qalisoa mme tlhahlobo e fetile.
       3. LED e le 'ngoe e khubelu haufi le LED e benyang e khubelu e bontša hore tlhahlobo e hlōlehile.
   12. Taba ea boikhethelo. Sebelisa testbench ea System Console ho bona tlhahiso e eketsehileng ea tlhahlobo.
       Hlokomela: Sebelisa System Console ho beha leihlo matšoao a boemo moetsong oa example ha boto e hokahane le komporo ea hau ka sesebelisoa sa JTAG segokahanyi. The System Console e bonts'a boemo ba boto ea LED bakeng sa tlhahlobo e hole, boemo ba ho qala mohatong o mong le o mong, le boemo ba jenereithara ea kopo ea boema-kepe le tlhahlobo ea likarabo. System Console e fana ka sebopeho sa ho qala kapa ho qala tlhahlobo hape.
       1. Khetha Lisebelisoa> Lisebelisoa tsa ho lokisa Sisteme> Console Console.
       2. Ho System Console, khetha File > Phetha Script.
       3. Bula the file <example_design_install_dir>/example_design/par/sysconsole_ testbench.tcl.
       4. Software e kenya tlhahiso ea tlhahlobo ea graphical. Khetha Qala hape ho etsa tlhahlobo hape.

Ho Kopanya le ho Leka Moralo Example ho Hardware

Moralo oa Hybrid Memory Cube Controller

Moqapi Example Tlhaloso

Moqapi example e bonts'a ts'ebetso ea Hybrid Memory Cube Controller IP core. O ka hlahisa moralo ho tsoa ho Example Design tab ea Hybrid Memory Cube Controller graphical user interface (GUI) ho IP parameter editor.

Likaroloana

• I2C master le mochini oa ho qala oa I2C bakeng sa karete ea morali oa HMC le tlhophiso ea HMC
• Mochini oa ATX PLL le mochine oa boemo ba transceiver recalibration
• Kopa jenereithara
• Kopa leihlo
• Khokahano ea Console ea Sisteme

Litlhoko tsa Hardware le Software
Altera e sebelisa lisebelisoa tse latelang le software ho lekola moralo oa exampLe:

• Intel Quartus Prime software
• Console ea tsamaiso
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL feela), kapa simulator ea VCS
• Arria 10 GX FPGA Development Kit
• HMC karete ea morali

Tlhaloso ea Ts'ebetso

Altera e fana ka moralo o lokiselitsoeng ho kopanya example HMC Controller IP konokono. Moqapi ona exampe habile Arria 10 GX FPGA Development Kit e nang le karete ea morali ea HMC e hoketsoeng ka likhokahanyo tsa FMC.
U ka sebelisa moralo joalo ka example bakeng sa khokahano e nepahetseng ea mantlha ea hau ea IP ho moralo oa hau, kapa joalo ka moralo oa ho qala o ka o etsa ho latela litlhoko tsa hau tsa moralo. Moqapi example kenyeletsa I2C master module, PLL/CDR recalibration module, e le 'ngoe ea ka ntle ea transceiver PLL IP core, le logic ea ho hlahisa le ho hlahloba litšebelisano. Moqapi example nka sesebelisoa sa Micron HMC 15G-SR HMC, e leng fourlsesebelisoa sa enke, kareteng ea morali. Moqapi example e kenyelletsa mohlala o le mong oa IP core mme e hokela sehokelo se le seng ho sesebelisoa sa HMC. Setšoantšo sa 2-1: HMC Controller Design Example Block Diagram

Kamora hore o hlophise Arria 10 FPGA ka sebopeho sa example, molaoli oa I2C o lokisa lijenereithara tsa oache tse ka botong le sesebelisoa sa HMC. Ha calibration e phetheloa, moqapi exampe lekanya ATX PLL. Nakong ea ts'ebetso, jenereithara ea kopo e hlahisa litaelo tsa ho bala le ho ngola tseo HMC Controller IP core e li sebetsang. Mohlokomeli oa kopo o hapa likarabo ho tsoa ho IP core ebe o li hlahloba hore na li nepahetse.

Lipontšo tsa Interface
Lethathamo la 2-1: HMC Controller IP Core Design Example Lipontšo

Lebitso la Letshwao clk_50	Tataiso Kenyeletso	Bophara (Bits) 1	Tlhaloso 50 MHz ho kenya oache.
hssi_refclk	Kenyeletso	1	CDR oache bakeng sa HMC le HMCC IP core.

Lebitso la Letshwao hmc_lxrx	Tataiso Kenyeletso	Bophara (Bits) Palo ea Channel (16 kapa 8)	Tlhaloso Transceiver ea FPGA e amohela lithakhisa.
hmc_lxtx	Sephetho	Palo ea Channel (16 kapa 8)	FPGA transceiver transmit pins.
hmc_ctrl_lxrxps	Kenyeletso	1	Taolo ea ho boloka matla a transceiver ea FPGA.
hmc_ctrl_lxtxps	Sephetho	1	Taolo ea ho boloka matla a HMC transceiver.
hmc_ctrl_ferr_n	Kenyeletso	1	HMC FERR_N tlhahiso.
hmc_ctrl_p_rst_n	Sephetho	1	Tlhahiso ea HMC P_RST_N.
hmc_ctrl_scl	Litsela tse peli	1	Oache ea tlhophiso ea HMC I2C.
hmc_ctrl_sda	Litsela tse peli	1	Lintlha tsa tlhophiso ea HMC I2C.
fmc0_scl	Sephetho	1	E sa sebelisoeng. E tsamaisoa ka tlase ho sireletsa lithakhisa tsa FPGA I/O ho tloha ho 3.3 V pullup ho karete ea morali.
fmc0_sda	Sephetho	1	E sa sebelisoeng. E tsamaisoa ka tlase ho sireletsa lithakhisa tsa FPGA I/O ho tloha ho 3.3 V pullup ho karete ea morali.
push_button	Kenyeletso	1	Konopo ea ho tobetsa e sebelisitsoeng ho seta bocha.
pelo_ho otla_n	Sephetho	1	Heartbeat LED tlhahiso.
link_init_complete_n	Sephetho	1	Ho qala lihokelo ho felletse tlhahiso ea LED.
teko_patsitswe_n	Sephetho	1	Teko e fetile tlhahiso ea LED.
test_failed_n	Sephetho	1	Teko ea LED e hlolehile.

Moqapi Example Register Map
Lethathamo la 2-2: HMC Controller IP Core Design Example Register Map

Ho ngolla lirejisete tsena ho tsosolosa moralo.

Bits 1:0	Lebitso la Tšimo Palo ea Boema-kepe	Mofuta RO	Boleng ba ho Reset E fapana	Tlhaloso Palo ea likou bakeng sa mohlala oa mantlha oa IP.
7:2	Reserved	RO	0x00

Lethathamo la 2-4: Ngoliso ea BOARD_LED
Rejisetara ena e bonts'a boemo ba li-LED tsa boto

Bits 0	Lebitso la Tšimo Teko e Hlolehile	Mofuta RO	Boleng ba ho Reset 0x00	Tlhaloso Teko e hlotsoe.
1	Teko e Fetile	RO	0x00	Teko e fetile.
2	HMCC Ho qala ho Felletse	RO	0x00	Ho qala sehokelo sa HMC ho felletse ebile ho loketse sephethephethe.
3	Ho otla ha pelo	RO	0x00	E fetoha ha moralo o sebetsa.
7:4	Reserved	RO	0x00

Lethathamo la 2-5: Ngolisa TEST_INITIALIZATION_STATUS

Bits 0	Lebitso la Tšimo Sete ea jenereithara ea oache ea I2C	Mofuta RO	Boleng ba ho Reset 0x00	Tlhaloso Lijenereithara tsa oache li lokiselitsoe.
1	ATX PLL le Transceiver Recalibration e Felletse	RO	0x00	ATX PLL le li-transceivers li hlophisitsoe bocha ho oache e kenang.
2	I2C HMC Tlhophiso e Felletse	RO	0x00	Tokiso ea sesebelisoa sa HMC holim'a I2C e felile.
3	HMC Link Initialization E Felletse	RO	0x00	Ho qala sehokelo sa HMC ho felletse ebile ho loketse sephethephethe.
7:4	Reserved	RO	0x00

Lethathamo la 2-6: Ngoliso ea PORT_STATUS

Bits 0	Lebitso la Tšimo Boema-kepe ba 0 bo Kopa OK	Mofuta RO	Boleng ba ho Reset 0x00	Tlhaloso Kopo ea 0 kopo e phethiloe.
1	Port 0 Responses OK	RO	0x00	Boema-kepe 0 tlhahlobo ea karabo e fetile.
2	Boema-kepe ba 1 bo Kopa OK	RO	0x00	Kopo ea 1 kopo e phethiloe.
3	Port 1 Responses OK	RO	0x00	Boema-kepe 1 tlhahlobo ea karabo e fetile.

Bits 4	Lebitso la Tšimo Boema-kepe ba 2 bo Kopa OK	Mofuta RO	Boleng ba ho Reset 0x00	Tlhaloso Kopo ea 2 kopo e phethiloe.
5	Port 2 Responses OK	RO	0x00	Boema-kepe 2 tlhahlobo ea karabo e fetile.
6	Boema-kepe ba 3 bo Kopa OK	RO	0x00	Kopo ea 3 kopo e phethiloe.
7	Port 4 Responses OK	RO	0x00	Boema-kepe 3 tlhahlobo ea karabo e fetile.

Tlhahisoleseling e 'Ngoe

HMC Controller Design Example Nalane ea Phetoho ea Bukana ea Basebelisi
Lethathamo la A-1: ​​Nalane ea Phetoho ea Litokomane
E akaretsa likarolo tse ncha le liphetoho ho sebopeho sa example tataiso ea mosebedisi bakeng sa HMC Controller IP core.

Letsatsi	Phetolelo ea ACDS	Liphetoho
2016.05.02	16.0	Tokollo ea pele.

Mokhoa oa ho ikopanya le Intel
Lethathamo la A-2: Mokhoa oa ho ikopanya le Intel
Ho fumana tlhaiso-leseling ea morao-rao mabapi le lihlahisoa tsa Intel, sheba tafole ena. U ka ikopanya le ofisi ea hau ea thekiso ea Intel ea lehae kapa moemeli oa thekiso.

Ikopanye	Mokhoa oa ho ikopanya	Aterese
Tšehetso ea tekheniki	Websebaka	www.altera.com/support
Koetliso ea botekgeniki	Websebaka	www.altera.com/training
	Email	FPGATraining@intel.com
Lingoliloeng tsa lihlahisoa	Websebaka	www.altera.com/literature
Tšehetso e seng ea theknoloji: kakaretso	Email	nacomp@altera.com

Ikopanye   Tšehetso e seng ea theknoloji: laesense ea software

Mokhoa oa ho ikopanya   Email

Aterese   authorization@altera.com

Lintlha Tse Amanang

• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• authorization@altera.com

Likopano tsa Typographic

Lethathamo la A-3: Likopano tsa ho ngola
E thathamisa mekhoa ea typographic e sebelisoang ke tokomane ena

Letšoao la Feedback le u lumella ho romella maikutlo ho Altera mabapi le tokomane. Mekhoa ea ho bokella maikutlo e fapana ho latela tokomane ka 'ngoe

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus le Stratix mantsoe le li-logo ke matšoao a khoebo a Intel Corporation kapa litšehetso tsa eona tsa US le/kapa linaheng tse ling. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba beha litaelo tsa lihlahisoa kapa lits'ebeletso.
Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang
101 Innovation Drive, San Jose, CA 95134

E qetetse ho ntlafatsoa bakeng sa Quartus Prime Design Suite: 16.0
UG-20027
2016.05.02
101 Boqapi ba popontshwa
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ALTERA Arria 10 Hybrid Memory Cube Controller Design Example [pdf] Bukana ea Mosebelisi Arria 10 Hybrid Memory Cube Controller Design Design Example, Arria 10, Hybrid Memory Cube Controller Design Example, Moqapi oa Molaoli Example, Moqapi Example

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