ALTERA Arria 10 Hybrid Memory Cube Controller Design Example

Le Fuafuaga Pulea Fa'amaufa'ailoga Fa'amafaufau Fa'amafaufau Fa'atasiample User Guide o loʻo tuʻuina atu faʻamatalaga i le mamanu ma le faʻaogaina o le HMC Controller hardware design example. O lo'o fa'afou le ta'iala mo le Quartus Prime Design Suite 16.0 ma fa'afou mulimuli ia Me 2, 2016.
O le Design Example Quick Start Guide o loʻo tuʻuina atu ai taʻiala taʻitasi mo le tuʻufaʻatasia, faʻataʻitaʻiina, gaosia, ma le suʻeina o le HMC Controller design example. Va'ai le Ata 1-1 mo le fa'asiliview o laasaga tau atinae.

Design Example Faʻamatalaga

Le mamanu meafaigaluega a le HMC Controller exampe aofia ai vaega eseese e pei o le Board Arria 10 Device, HMC Pule IP Core, Uati & Toe Seti TX PLLs, Faʻamatalaga Talosaga Talosaga Generator ma Tali Mataʻituina, TX / TX FIFO MAC, RX MAC, Suʻega Avalon-MM Pulea ma LEDs, Pule Tulaga Interface , Avalon-MM I 2C Master, Initialization State Machine, TX Lane Swapper, Transceiver x16, RX Lane Swapper, Arria 10 Transceiver Reconfiguration Interface, ma HMC Device. O le exampO le mamanu e manaʻomia ni faʻatulagaga faʻapitoa e faʻaogaina lelei i luga o le Arria 10 GX FPGA Development Kit ma le kata tama teine ​​a le HMC.

Fa'amatalaga Faaopoopo

O le vaega o Fa'amatalaga Faaopoopo o lo'o tu'uina atu ai fa'amatalaga i le fa'atulagaina o fa'atonuga mo le fa'ata'ita'iga na faiaample, le tala fa'asolopito o le ta'iala fa'aoga, faiga fa'akomipiuta o lo'o fa'aogaina i le ta'iala, ma le fa'afeso'ota'i le Intel mo se lagolago.

Fa'atonuga o le Fa'aaogaina o Mea

Mulimuli i fa'atonuga o lo'o i lalo e fa'aoga ai le HMC Controller hardware design exampLe:

1. Tuufaatasia le mamanu example faʻaaogaina o se simulator
2. Fa'atino fa'ata'ita'iga fa'atino
3. Fausia le mamanu example
4. Tuufaatasia le mamanu example faʻaaogaina o Quartus Prime
5. Su'e le mamanu o meafaigaluega

Manatua o le seti meafaigaluega ma suʻega files mo le mamanu example o lo'o i totonu /example_design/par, ae o le simulation files o lo'o i totonu /example_design/sim.

Ina ia fesoasoani ia te oe ia malamalama pe faʻapefea ona faʻaogaina le Hybrid Memory Cube Controller IP core, o le autu o loʻo faʻaalia ai se suʻega faʻataʻitaʻi faʻataʻitaʻiga ma se faʻataʻitaʻiga meafaigaluega.ampe lagolagoina le tu'ufa'atasiga ma su'ega meafaigaluega. A e gaosia le mamanu example, e otometi lava ona fatuina e le faatonu parameter le files e manaʻomia e faʻataʻitaʻi, faʻapipiʻi, ma suʻe le mamanu i meafaigaluega. E mafai ona e sii maia le mamanu tuufaatasia i le Intel® Arria® 10 GX FPGA Development Kit.

Fa'amatalaga Fa'atatau
Hybrid Memory Cube Controller IP Core User Guide

Design Example Fa'atonuga Fa'atonu

Le faʻatulagaina o meafaigaluega ma suʻega files (le mamanu meafaigaluega example) o loʻo i totonuample_ design_install_dir>/example_design/par. Le fa'ata'ita'iga files (testbench mo na o faʻataʻitaʻiga) o loʻo i totonuample_design_install_dir>/example_design/sim.

Design Example Vaega

Le mamanu meafaigaluega a le HMC Controller example aofia ai vaega nei:

• HMC Pule IP autu ma le CDR faasinoupu uati seti i le 125 MHz ma le faaletonu RX mapping ma TX mapping faatulagaga.
  Manatua: O le mamanu exampE mana'omia nei fa'atonuga ina ia fa'agaioi lelei i le Arria 10 GX FPGA Development Kit fa'atasi ai ma le kata tama teine ​​a le HMC.
• Fa'amatalaga a le aufaipisinisi e fa'amaopoopoina le polokalame o le IP core, ma le fa'atupuina o pusa ma le siakiina.
• JTAG pule e feso'ota'i ma le Altera System Console. E te fa'afeso'ota'i ma le tagata o tausia e ala i le System Console.

Lisi le ki files e faatino le example testbench.

/src/hmcc_example.sv	Fuafuaga masini tulaga maualuga eample file.
/sim/hmcc_tb.sv	Tulaga maualuga file mo fa'ata'ita'iga.
Testbench Scripts Fa'aaliga: Fa'aaoga le Makefile e fatu ai nei tusitusiga.
/sim/run_vsim.do	O le ModelSim script e faʻatautaia le suʻega suʻega.
/sim/run_vcs.sh	Le Synopsys VCS script e faʻatautaia le suʻega suʻega.
/sim/run_ncsim.sh	Le Cadence NCSim script e faʻatautaia le suʻega suʻega.

Fausiaina o le Design Example

Ata 1-5: Esoample Design Tab i Hybrid Memory Cube Controller Parameter Editor

Mulimuli i laasaga nei e fa'atupu ai le Arria 10 hardware design example ma le testbench:

1. I totonu o le IP Catalog (Meafaigaluega> IP Catalog), filifili le Arria 10 faʻatonuga masini aiga.
2. I le IP Catalog, su'e ma filifili Hybrid Memory Cube Controller. Ua aliali mai le fa'amalama New IP Variation.
3. Fa'ailoa se igoa pito i luga mo lau suiga masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .qsys.
4. E tatau ona e filifilia se masini Arria 10 faʻapitoa i totonu o le masini masini, poʻo le tausia o le masini le lelei e filifilia e le Quartus Prime software.
5. Kiliki OK. Ua aliali mai le fa'atonu o le IP.
6. I luga o le IP tab, faʻamaonia le faʻasologa mo lau fesuiaiga autu IP.
7. I le Example Design tab, filifili tulaga nei mo le mamanu exampLe:
   1. Mo Filifiliga Design, filifili le filifiliga a le HMCC Daughter Board.
   2. Mo Example Lisiina Files, filifili le filifiliga Fa'ata'ita'iga e fa'atupu ai le su'ega, ma filifili le filifiliga Fa'aopoopo e fa'atupuina ai le fa'asologa o meafaigaluegaample.
   3. Mo Fuafuaina HDL, na'o Verilog o lo'o avanoa.
   4. Mo Atina'e Atina'e Pusa filifili le Arria 10 GX FPGA Atina'e Kit (Production Silicon).
      Manatua: A e filifilia lenei pusa, o le meafaigaluega mamanu example overwrites lau filifiliga masini muamua ma le masini i luga o le laupapa sini. A e gaosia le mamanu example, o le Intel Quartus Prime polokalama faakomepiuta Intel
      Poloketi a Quartus Prime, seti, ma pine o tofiga mo le laupapa na e filifilia. Afai e te le mana'o i le polokalama e fa'atatau i se laupapa fa'apitoa, filifili Leai.
8. Kiliki le Generate Example fa'amau Fa'ailoga

Malamalama i le Testbench

Altera e maua ai se fa'ata'ita'iga fa'atusaample faʻatasi ma le HMC Pule IP autu. Le mamanu exampo lo'o avanoa uma mo fa'ata'ita'iga o lau 'autu IP ma mo le tu'ufa'atasiga. Le mamanu example i le simulation galuega tauave e pei o le HMC Pule IP testbench autu.
Afai e te kiliki Fausia Example Design i le HMC Controller parameter faatonu, o le polokalama Quartus Prime fa'atupuina se su'ega fa'ata'ita'iga. O le fa'atonu fa'ata'ita'i e fa'atonuina oe mo le nofoaga mana'omia o le su'ega.
Ina ia fa'ata'ita'i le su'ega, e tatau ona e tu'uina atu lau lava HMC bus functional model (BFM). Altera su'e le mamanu example su'ega fa'atasi ma le Micron Hybrid Memory Cube BFM. O le suʻega suʻega e le aofia ai se I2C matai module, aua o le Micron HMC BFM e le lagolagoina ma e le manaʻomia le faʻatulagaina e se I2C module.
I le faʻataʻitaʻiga, o le suʻega suʻega e pulea se TX PLL ma fesoʻotaʻiga auala faʻamatalaga e faʻatino ai le faasologa o gaioiga:

1. Fa'atulaga le HMC BFM ma le HMC Controller IP fa'amaumauga autu ma le lautele o alalaupapa, i le Tali Tatala Tatala Faiga.
2. Faʻavaeina le fesoʻotaʻiga i le va o le BFM ma le IP autu.
3. Fa'atonu ports e fa a le IP core e tusi ai fa'amatalaga fa'amaumauga i le BFM.
4. Fa'atonu le IP core e toe faitau i tua fa'amaumauga mai le BFM.
5. Siaki pe o fa'amaumauga faitau e fetaui ma fa'amaumauga tusitusi.
6. Afai e fetaui fa'amaumauga, fa'aalia TEST_PASSED.

Fa'ata'ita'iina o le Fa'ata'ita'iga Example Testbench
Ata 1-6: Taualumaga

Mulimuli i laasaga nei e faʻataʻitaʻi ai le suʻega:

1. I le laina o le poloaiga, sui i leample>/sim directory.
2. Ituaiga fai tusitusiga.
3. Tusi se tasi o poloaiga nei, e faalagolago i lau simulator:
4. I view i'uga fa'atusa:
   1. A e faʻataʻitaʻiina le suʻega suʻega i soʻo se tasi o faʻataʻitaʻiga lagolago e tolu, o le tusitusiga e faʻatino le faasologa o suʻega ma faʻamauina le gaioiga simulator i totonu.ample directory>/example_ design/sim/ .log. o le "vsim", "ncsim", poʻo le "vcs".
   2. A e tamoe i le suʻega suʻega i soʻo se tasi o faʻataʻitaʻiga lagolago e tolu, o le tusitusiga e gaosia ai se galu file. E mafai ona e fa'atinoina le fa'atonuga fai _gui e utaina le galu i le faʻataʻitaʻiga faʻapitoa faʻapitoa viewer.
      I view o le galu file i lau simulator, lolomi se tasi o tulafono nei:

      Laisene Simulator Mentor Graphics ModelSim	Laina Poloaiga fai vsim_gui	Galu File <design example directory>/example_design/sim/mentor/hmcc_wf.wlf
      Synopsys Discovery Visual Environment	fai vcs_gui	<design example directory>/example_design/sim/ hmcc_wf.vpd
      Cadence SimVision Galue	fai ncsim_gui	<design example directory>/example_design/sim/ cadence/hmcc_wf.shm
5. Iloilo i'uga. O le suʻega suʻesuʻe manuia e auina atu ma maua le sefulu pepa i le taulaga, ma faʻaalia Test_PASSED"

Faatulagaina o le Komiti Faatino

Fa'atulaga le laupapa e fa'atino ai le fa'ata'ita'iga o meafaigaluega e iaiample.
Manatua: Ia mautinoa ua tape le paoa ae e te le'i suia soo se faatulagaga.

1. Seti ki DIP i luga o le kata tama teine ​​e pei ona taua i lalo:
2. Seti le DIP ki SW1 e fa'ailoa ai le ID 0:
   

   Suiga	Galuega	Faatulagaina
   1	CUB[0]	Tatala
   2	CUB[1]	Tatala
   3	CUB[2]	Tatala
   4	—	Aua le popole

Seti le DIP ki SW2 e fa'ailoa ai le fa'atulagaina o le uati:

Suiga	Galuega	Faatulagaina
1	CLK1_FSEL0	Tatala (125 MHz)
2	CLK1_FSEL1	Tatala (125 MHz)
3	CLK1_SEL	Tatala (Crystal)
4	—	Aua le popole

• Fa'afeso'ota'i le kata tama teine ​​a le HMC i le Arria 10 FPGA Development Kit e fa'aoga ai feso'ota'iga J8 ma le J10 a le tama teine.
• Seti osooso ile Arria 10 GX FPGA Development Kit:
• Fa'aopoopo shunts i le J8 osooso e filifili ai le 1.5 V e fai ma VCCIO fa'atulagaina mo FMC feso'ota'iga B.
• Fa'aopoopo shunts i le J11 osooso e filifili ai le 1.8 V e fai ma VCCIO fa'atulagaina mo FMC feso'ota'iga A.

Tu'ufa'atasia ma Fa'ata'ita'i le Fa'ailoga Fa'atusaample i Meafaigaluega

E fa'aputu ma fa'atino se su'ega fa'ata'ita'iga ile fa'ata'ita'iga o meafaigaluega e iaiample, mulimuli i laasaga nei

1. Fa'amautinoa le fa'atulagaina o meafaigaluega e iaiampua maea le tupulaga.
2. I le polokalama Quartus Prime, tatala le poloketi Quartus Primeample_design_install_dir> /example_design/par/hmcc_example.qpf.
3. I le Compilation Dashboard, kiliki Compile Design (Intel Quartus Prime Pro Edition) pe filifili Processing> Start Compilation (Intel Quartus Prime Standard Edition).
4. A mae'a ona e fa'atupuina se .sof, mulimuli i la'asaga nei e fa'apolokalame ai le fa'asologa o meafaigaluega e iaiampi luga ole Arria 10 masini:
   1. Filifili Tools> Programmer.
   2. I le Polokalama, kiliki Hardware Setup.
   3. Filifili se masini polokalame.
   4. Filifili ma fa'aopoopo le Arria 10 GX FPGA Development Kit e mafai ona fa'afeso'ota'i ai lau vasega Quartus Prime.
   5. Ia mautinoa ua setiina le Faiga i le JTAG.
   6. Kiliki Auto Su'esu'e ma filifili so'o se masini.
   7. Kiliki faalua le masini Arria 10.
   8. Tatala le .sof i totonuample_design_install_dir>/example_design/par/output_ files,
      Manatua: O le polokalama Quartus Prime e suia le masini i le tasi i le .sof.
   9. I le laina ma lau .sof, siaki le pusa i le Polokalama / Faʻatonu koluma.
   10. Kiliki Amata.
   11. A maeʻa ona faʻapipiʻi e le polokalama le masini ma le faʻataʻitaʻiga meafaigaluegaample, matau le laupapa LEDs:
       1. O le moli mumu e emoemo e fa'ailoa ai o lo'o fa'agasolo le mamanu.
       2. E lua moli lanumeamata e latalata i le moli mumu mumu e faʻaalia ai o le HMC soʻotaga ua amataina ma pasi le suʻega.
       3. E tasi le LED mumu i tafatafa o le moli mumu mumu e fa'ailoa mai ua le manuia le su'ega.
   12. Filifili. Fa'aoga le System Console testbench e mata'itu ai fa'aopoopo su'ega.
       Fa'aaliga: Fa'aoga le System Console e mata'itu ai fa'ailoga tulaga i le fa'ata'ita'igaamppe a fesoʻotaʻi le laupapa i lau komepiuta e ala i le JTAG feso'ota'iga. O le System Console o loʻo faʻaalia ai le tulaga o le LED o le laupapa mo le mataʻituina mamao, o le tulaga amata mo laasaga taʻitasi, ma le tulaga o le faʻatupu talosaga a le uafu taʻitasi ma le siaki tali. O lo'o tu'uina atu fo'i e le System Console se atina'e e amata pe toe amata ai le su'ega.
       1. Filifili Meafaigaluega > System Debugging Tools > System Console.
       2. I le System Console, filifili File > Fa'atino le Tusi.
       3. Tatala le file <example_design_install_dir>/example_design/par/sysconsole_ testbench.tcl.
       4. O lo'o fa'apipi'i e le polokalama fa'akomepiuta fua fa'ata'ita'iga. Filifili Toe amata e toe fai le su'ega.

Tu'ufa'atasia ma Fa'ata'ita'i le Fa'ailoga Fa'atusaample i Meafaigaluega

Fuafuaga Pule Fa'atonu Fa'amau Fa'amau Fa'aigoa

Design Example Faʻamatalaga

Le mamanu exampLe fa'aalia le fa'atinoga o le Hybrid Memory Cube Controller IP core. E mafai ona e fatuina le mamanu mai le Example Design tab o le Hybrid Memory Cube Controller graphical user interface (GUI) i le IP editor parameter.

Vaega

• I2C matai ma le I2C initialization masini setete mo HMC afafine pepa ma faatulagaga HMC
• ATX PLL ma transceiver recalibration masini setete
• Talosaga generator
• Talosaga mataitu
• System Console interface

Meafaigaluega ma Polokalama Manaoga
Altera fa'aoga meafaigaluega ma polokalama fa'akomepiuta nei e su'e ai le fa'ata'ita'igaampLe:

• Intel Quartus Prime polokalama
• System Console
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL naʻo), poʻo le VCS simulator
• Arria 10 GX FPGA Development Kit
• Kata tama teine ​​HMC

Fa'amatalaga Fa'atino

Altera e tu'uina atu se fa'asologa tu'ufa'atasiga fa'atusaample faʻatasi ma le HMC Pule IP autu. O lenei mamanu exampe fa'atatau i le Arria 10 GX FPGA Development Kit fa'atasi ma le HMC daughter card e feso'ota'i atu i feso'ota'iga FMC.
E mafai ona e faʻaogaina le mamanu e pei o se example mo fesoʻotaʻiga saʻo o lau IP autu i lau mamanu, poʻo le avea o se mamanu amata e mafai ona e faʻavasegaina mo au lava mamanu manaʻoga. Le mamanu exampe aofia ai se I2C matai module, se PLL/CDR recalibration module, tasi transceiver fafo PLL IP autu, ma le manatu e gaosia ma siaki fefaʻatauaiga. Le mamanu exampLe manatu o se masini Micron HMC 15G-SR HMC, o se fourlmasini vaitusi, i luga o le tama teine. Le mamanu exampe aofia ai le tasi faʻataʻitaʻiga o le IP autu ma faʻafesoʻotaʻi i se soʻotaga tasi i luga o le masini HMC. Ata 2-1: HMC Pule Fuafuaga Example Ata poloka

A maeʻa ona e faʻatulagaina le Arria 10 FPGA faʻatasi ma le mamanu example, le pule I2C configures le i luga o le laupapa uati generators ma le masini HMC. A maeʻa le faʻavasegaina, o le mamanu example fa'avasegaina le ATX PLL. I le taimi o le faʻagaioiga, e faʻatupuina e le generator talosaga le faitau ma le tusitusi o poloaiga e faʻatautaia e le HMC Controller IP core. O le mataʻituina o talosaga e puʻeina tali mai le IP autu ma siaki mo le saʻo.

Fa'ailoga Fa'afeso'ota'i
Laulau 2-1: HMC Pule IP Core Design Example Faailoga

Igoa Faailoga clk_50	Fa'atonuga Ulufale	Lautele (Piti) 1	Fa'amatalaga 50 MHz fa'aoga uati.
hssi_refclk	Ulufale	1	CDR fa'asino uati mo HMC ma HMCC IP autu.

Igoa Faailoga hmc_lxrx	Fa'atonuga Ulufale	Lautele (Piti) Faitauga Ala (16 po'o le 8)	Fa'amatalaga FPGA transceiver maua pine.
hmc_lxtx	Tuuina atu	Faitauga Ala (16 po'o le 8)	FPGA transceiver lafo pine.
hmc_ctrl_lxrxps	Ulufale	1	FPGA transceiver mana faasaoina pule.
hmc_ctrl_lxtxps	Tuuina atu	1	HMC transceiver mana faasaoina pule.
hmc_ctrl_ferr_n	Ulufale	1	HMC FERR_N galuega faatino.
hmc_ctrl_p_rst_n	Tuuina atu	1	HMC P_RST_N fa'aoga.
hmc_ctrl_scl	Ta'ilua	1	HMC I2C fetuutuunaiga uati.
hmc_ctrl_sda	Ta'ilua	1	HMC I2C faʻamaumauga faʻatulagaina.
fmc0_scl	Tuuina atu	1	Le fa'aaogaina. Tu'u maualalo e puipui ai pine FPGA I/O mai le toso 3.3 V i luga ole tama teine.
fmc0_sda	Tuuina atu	1	Le fa'aaogaina. Tu'u maualalo e puipui ai pine FPGA I/O mai le toso 3.3 V i luga ole tama teine.
tulei_faamau	Ulufale	1	Oomi le fa'aoga fa'aoga mo le toe setiina.
fatu_tātā.n	Tuuina atu	1	Fa'aita le fatu fatu.
link_init_complete_n	Tuuina atu	1	So'oga amata fa'ato'a fa'aulufalega o le LED.
pasi_su'ega	Tuuina atu	1	Ua pasia le su'ega o le fa'aogaina o le LED.
suega_fai_n	Tuuina atu	1	Le su'ega le fa'atinoina o le LED.

Design Example Resitala Faafanua
Laulau 2-2: HMC Pule IP Core Design Example Resitala Faafanua

O le tusitusi i nei tusi resitala e toe setiina ai le mamanu.

Pisi 1:0	Igoa fanua Taulaga Taulaga	Ituaiga RO	Taua ile Toe setiina Eseese	Fa'amatalaga Numera o ports mo le fa'ata'ita'iga autu IP.
7:2	Fa'apolopolo	RO	0x00

Laulau 2-4: Tusi Resitala BOARD_LEDs
O lenei tusi resitala e atagia ai le tulaga o LED a le laupapa

Pisi 0	Igoa fanua Su'e Su'ega	Ituaiga RO	Taua ile Toe setiina 0x00	Fa'amatalaga Ua le manuia le su'ega.
1	Pasia le Su'ega	RO	0x00	Na pasi le su'ega.
2	HMCC Link Initialization Maea	RO	0x00	Ua mae'a le amataina o feso'ota'iga a le HMC ma sauni mo feoaiga.
3	Tata o le fatu	RO	0x00	Togi pe a fa'agasolo le mamanu.
7:4	Fa'apolopolo	RO	0x00

Laulau 2-5: TEST_INITIALIZATION_STATUS Resitala

Pisi 0	Igoa fanua I2C Uati Generator Set	Ituaiga RO	Taua ile Toe setiina 0x00	Fa'amatalaga O lo'o fa'apipi'i afi uati i luga o le laupapa.
1	ATX PLL ma le Transceiver Toe fa'afouga Maea	RO	0x00	ATX PLL ma transceivers toe fa'avasega i le uati ulufale.
2	I2C HMC Fa'ato'a mae'a	RO	0x00	HMC fa'atulagaina masini i luga ole I2C mae'a.
3	HMC Link Initialization Maea	RO	0x00	Ua mae'a le amataina o feso'ota'iga a le HMC ma sauni mo feoaiga.
7:4	Fa'apolopolo	RO	0x00

Laulau 2-6: PORT_STATUS Resitala

Pisi 0	Igoa fanua Taulaga 0 Talosaga OK	Ituaiga RO	Taua ile Toe setiina 0x00	Fa'amatalaga Taulaga 0 talosaga fa'atupu ua mae'a.
1	Taulaga 0 Tali Lelei	RO	0x00	Ua pasia le siaki tali a le Port 0.
2	Taulaga 1 Talosaga OK	RO	0x00	Taulaga 1 talosaga fa'atupu ua mae'a.
3	Taulaga 1 Tali Lelei	RO	0x00	Ua pasia le siaki tali a le Port 1.

Pisi 4	Igoa fanua Taulaga 2 Talosaga OK	Ituaiga RO	Taua ile Toe setiina 0x00	Fa'amatalaga Taulaga 2 talosaga fa'atupu ua mae'a.
5	Taulaga 2 Tali Lelei	RO	0x00	Ua pasia le siaki tali a le Port 2.
6	Taulaga 3 Talosaga OK	RO	0x00	Taulaga 3 talosaga fa'atupu ua mae'a.
7	Taulaga 4 Tali Lelei	RO	0x00	Ua pasia le siaki tali a le Port 3.

Fa'amatalaga Faaopoopo

HMC Pule Fuafuaga Example User Guide Toe Iloilo Talafaasolopito
Laulau A-1: ​​Tala'aga Toe Iloiloga o Pepa
Aoteleina foliga fou ma suiga i le mamanu example fa'aoga taiala mo le HMC Pule IP autu.

Aso	ACDS Version	Suiga
2016.05.02	16.0	Fa'asalalauga muamua.

Faʻafefea ona faʻafesoʻotaʻi Intel
Laulau A-2: Fa'afefea ona Fa'afeso'ota'i Intel
Ina ia suʻe faʻamatalaga sili ona lata mai e uiga i oloa Intel, vaʻai i le laulau lenei. E mafai fo'i ona e fa'afeso'ota'i lou ofisa fa'atau Intel po'o sui fa'atau.

Fa'afeso'ota'i	Faʻafesoʻotaʻi Metotia	tuatusi
Fesoasoani fa'apitoa	Webnofoaga	www.altera.com/support
Toleniga faʻapitoa	Webnofoaga	www.altera.com/training
	imeli	FPGATraining@intel.com
tusi oloa	Webnofoaga	www.altera.com/literature
Lagolago e le fa'apitoa: lautele	imeli	nacomp@altera.com

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Fonotaga Tusitusi

Fuafuaga A-3: Fono Fa'asinotonu
Lisi tulafono fa'akomipiuta o lo'o fa'aogaina e lenei pepa

O le fa'ailoga Fa'amatalaga e mafai ai ona e tu'uina atu fa'amatalaga i Altera e uiga i le pepa. O auala mo le aoina mai o manatu faaalia e eseese pe a talafeagai mo pepa taitasi

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus ma Stratix upu ma logos o faʻailoga a le Intel Corporation poʻo ana lala i le US ma/poʻo isi atunuu. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.
O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi
101 Innovation Drive, San Jose, CA 95134

Fa'afouga mulimuli mo Quartus Prime Design Suite: 16.0
UG-20027
2016.05.02
101 Drive Faʻaleleia
San Jose, CA 95134
www.altera.com

Pepa / Punaoa

ALTERA Arria 10 Hybrid Memory Cube Controller Design Example [pdf] Taiala mo Tagata Fa'aoga Arria 10 Hybrid Memory Cube Controller Design Example, Arria 10, Hybrid Memory Cube Controller Design Example, Pule Design Example, Design Example

Fa'asinomaga

• Tusi Taiala