ALTERA Arria 10 Hybrid Memory Cube Controller Tsim Example

Hybrid Memory Cube Controller Tsim Example Daim Ntawv Qhia Tus Neeg Siv muab cov ntaub ntawv ntawm kev tsim thiab kev siv ntawm HMC Controller hardware design example. Cov lus qhia tau hloov kho rau Quartus Prime Design Suite 16.0 thiab tau hloov kho zaum kawg rau lub Tsib Hlis 2, 2016.
Design Example Quick Start Guide muab cov lus qhia ua ntu zus rau kev sau, simulating, tsim, thiab sim HMC Controller tsim example. Saib daim duab 1-1 rau ib qho dhauview ntawm cov theem kev txhim kho.

Tsim Examplus piav qhia

HMC Controller kho vajtse tsim example suav nrog ntau yam khoom xws li Board Arria 10 Device, HMC Controller IP Core, Clocks & Reset TX PLLs, Data Path Request Generator thiab Response Monitor, TX/TX FIFO MAC, RX MAC, Test Avalon-MM Control thiab LEDs, Controller Status Interface , Avalon-MM I 2C Master, Initialization State Machine, TX Lane Swapper, Transceiver x16, RX Lane Swapper, Arria 10 Transceiver Reconfiguration Interface, thiab HMC Device. Cov example tsim kom muaj kev teeb tsa tshwj xeeb kom ua haujlwm tau zoo ntawm Arria 10 GX FPGA Development Kit nrog HMC tus ntxhais daim npav.

Cov ntaub ntawv ntxiv

Ntu Cov Ntaub Ntawv Ntxiv muab cov ntsiab lus ntawm cov qauv qhia rau tus tsim tsim example, kev hloov kho keeb kwm ntawm cov neeg siv phau ntawv qhia, typographic conventions siv nyob rau hauv phau ntawv qhia, thiab yuav ua li cas hu rau Intel rau kev txhawb nqa.

Cov lus qhia siv khoom

Ua raws li cov lus qhia hauv qab no kom siv HMC Controller kho vajtse tsim example:

1. Compile tus tsim exampsiv lub simulator
2. Ua haujlwm simulation
3. Tsim tus tsim example
4. Compile tus tsim exampsiv Quartus Prime
5. Kuaj qhov kho vajtse tsim

Nco ntsoov tias kho vajtse configuration thiab kuaj files rau tus tsim example nyob rau hauv /example_design/par, thaum lub simulation files nyob rau hauv /example_design/sim.

Txhawm rau pab koj nkag siab yuav ua li cas siv Hybrid Memory Cube Controller IP core, cov tub ntxhais muaj lub simulatable testbench thiab kho vajtse tsim example uas txhawb kev muab tso ua ke thiab kev sim kho vajtse. Thaum koj tsim tus tsim example, parameter editor cia li tsim cov files yuav tsum simulate, compile, thiab sim tus tsim nyob rau hauv hardware. Koj tuaj yeem rub tawm cov qauv tsim los rau Intel® Arria® 10 GX FPGA Development Kit.

Cov ntaub ntawv ntsig txog
Hybrid Memory Cube Controller IP Core User Guide

Tsim Example Directory Structure

Hardware configuration thiab kuaj files (the hardware design example) nyob rau hauvample_design_install_dir>/example_design/par. Kev simulation files (testbench rau simulation nkaus xwb) nyob rau hauvample_design_install_dir>/example_design/sim.

Tsim Exampcov Components

HMC Controller kho vajtse tsim example suav nrog cov hauv qab no:

• HMC Controller IP core nrog CDR siv moos teem rau 125 MHz thiab nrog default RX mapping thiab TX mapping nqis.
  Nco tseg: Design example xav kom cov chaw no ua haujlwm kom zoo ntawm Arria 10 GX FPGA Development Kit nrog HMC tus ntxhais daim npav.
• Cov neeg siv khoom logic uas tswj hwm qhov kev ua haujlwm ntawm IP core, thiab pob ntawv tsim thiab kuaj xyuas.
• JTAG xws li kev sib txuas lus nrog Altera System Console. Koj sib txuas lus nrog tus neeg siv khoom logic los ntawm System Console.

Sau tus yuam sij files uas implement example testbench.

/src/hmcc_example.sv	Sab saum toj-theem kho vajtse tsim example file.
/sim/hmcc_tb.sv	Qib saum toj kawg nkaus file rau simulation.
Testbench Scripts Nco tseg: Siv cov Makefile los tsim cov ntawv sau no.
/sim/run_vsim.do	ModelSim tsab ntawv los khiav lub testbench.
/sim/run_vcs.sh	Synopsys VCS tsab ntawv los khiav lub testbench.
/sim/run_ncsim.sh	Cadence NCSim tsab ntawv los khiav lub testbench.

Tsim cov Design Example

Daim duab 1-5: Example Tsim Tab hauv Hybrid Memory Cube Controller Parameter Editor

Ua raws li cov kauj ruam no los tsim Arria 10 kho vajtse tsim example and testbench:

1. Hauv IP Catalog (Cov Cuab Yeej> IP Catalog), xaiv Arria 10 lub hom phiaj ntaus tsev neeg.
2. Hauv IP Catalog, nrhiav thiab xaiv Hybrid Memory Cube Controller. Lub qhov rais tshiab IP Variation tshwm.
3. Qhia meej lub npe saum toj kawg nkaus rau koj qhov kev hloov pauv IP. Tus parameter editor txuag tus IP variation nqis hauv a file npe .qsy.
4. Koj yuav tsum xaiv ib qho tshwj xeeb Arria 10 ntaus ntawv hauv Cov Ntaus Ntaus, lossis khaws lub cuab yeej ua ntej Quartus Prime software xaiv.
5. Nyem OK. Tus IP parameter editor tshwm.
6. Ntawm tus IP tab, qhia qhov tsis muaj rau koj tus IP qhov hloov pauv.
7. Hauv Example Design tab, xaiv cov chaw hauv qab no rau tus tsim example:
   1. Rau Xaiv Tsim, xaiv HMCC Daughter Board xaiv.
   2. Rau Examptsim Files, xaiv qhov kev xaiv Simulation los tsim lub testbench, thiab xaiv qhov kev xaiv Synthesis los tsim kho vajtse tsim example.
   3. Rau Generated HDL Format, tsuas yog Verilog xwb.
   4. Rau Lub Hom Phiaj Kev Txhim Kho Cov Khoom Siv xaiv Arria 10 GX FPGA Development Kit (Tshuaj Silicon).
      Nco tseg: Thaum koj xaiv cov khoom siv no, kho vajtse tsim example overwrite koj yav dhau los ntaus ntawv xaiv nrog cov cuab yeej ntawm lub hom phiaj board. Thaum koj tsim tus tsim example, Intel Quartus Prime software tsim Intel
      Quartus Prime qhov project, teeb tsa, thiab pin cov haujlwm rau lub rooj tsavxwm koj xaiv. Yog tias koj tsis xav kom lub software tsom rau ib lub rooj tsav xwm tshwj xeeb, xaiv Tsis muaj.
8. Nyem qhov Generate Example Design button

Nkag siab Testbench

Altera muab tus qauv tsim example nrog HMC Controller IP core. Design example yog muaj ob qho tib si rau simulation ntawm koj tus IP core thiab muab tso ua ke. Design example hauv simulation ua haujlwm raws li HMC Controller IP core testbench.
Yog tias koj nyem Tsim Example Tsim nyob rau hauv HMC Controller parameter editor, Quartus Prime software tsim ib qho kev sim ua qauv qhia. Lub parameter editor qhia koj rau qhov xav tau qhov chaw ntawm lub testbench.
Txhawm rau simulate lub testbench, koj yuav tsum muab koj tus kheej HMC tsheb npav ua haujlwm qauv (BFM). Altera xeem tus tsim example testbench nrog Micron Hybrid Memory Cube BFM. Lub testbench tsis suav nrog I2C master module, vim tias Micron HMC BFM tsis txhawb nqa thiab tsis tas yuav teeb tsa los ntawm I2C module.
Hauv kev simulation, lub testbench tswj ib TX PLL thiab cov ntaub ntawv txoj kev sib cuam tshuam los ua cov nram qab no ua ntu zus:

1. Configures HMC BFM nrog HMC Controller IP core cov ntaub ntawv tus nqi thiab channel dav, nyob rau hauv teb Qhib Loop hom.
2. Tsim kev sib txuas ntawm BFM thiab IP core.
3. Qhia txhua tus IP tub ntxhais plaub qhov chaw nres nkoj los sau plaub pob ntawv cov ntaub ntawv rau BFM.
4. Qhia tus tub ntxhais IP kom nyeem cov ntaub ntawv rov qab los ntawm BFM.
5. Txheeb xyuas tias cov ntaub ntawv nyeem sib phim cov ntaub ntawv sau.
6. Yog tias cov ntaub ntawv sib phim, qhia TEST_PASSED.

Simulating Design Exampua Testbench
Daim duab 1-6: Cov txheej txheem

Ua raws li cov kauj ruam no los simulate lub testbench:

1. Ntawm kab hais kom ua, hloov mus rau qhovample>/sim directory.
2. Hom ua scripts.
3. Ntaus ib qho ntawm cov lus txib hauv qab no, nyob ntawm koj lub simulator:
4. Rau view Cov txiaj ntsig simulation:
   1. Thaum koj khiav lub testbench nyob rau hauv ib qho ntawm peb qhov kev txhawb nqa simulators, tsab ntawv ua tiav cov testbench ib ntus thiab teev cov haujlwm simulator hauvample directory>/example_ design/sim/ .log. is “vsim”, “ncsim”, or “vcs”.
   2. Thaum koj khiav lub testbench nyob rau hauv ib qho ntawm peb qhov kev txhawb nqa simulators, tsab ntawv tsim ib lub waveform file. Koj tuaj yeem khiav cov lus txib ua _gui mus thauj cov waveform hauv simulator-specific waveform viewua.
      Rau view lub waveform file hauv koj lub simulator, ntaus ib qho ntawm cov lus txib hauv qab no:

      Daim ntawv tso cai Simulator Mentor Graphics ModelSim	Kab hais kom ua ua vsim_gui	Waveform File <design exampli directory >/example_design/sim/ mentor/hmcc_wf.wlf
      Synopsys Discovery Visual Ib puag ncig	ua vcs_gui	<design exampli directory >/example_design/sim/ hmcc_wf.vpd
      Cadence SimVision Waveform	make ncsim_gui	<design exampli directory >/example_design/sim/ cadence/hmcc_wf.shm
5. Tshawb xyuas cov txiaj ntsig. Qhov kev vam meej testbench xa thiab tau txais kaum pob ntawv rau ib qhov chaw nres nkoj, thiab qhia Test_PASSED "

Kev teeb tsa lub Rooj Tswjhwm Saib

Teeb tsa lub rooj tsavxwm los khiav qhov kho vajtse tsim example.
Nco tseg: Xyuas kom tseeb tias lub hwj chim raug muab tua ua ntej koj hloov tej chaw.

1. Teem lub DIP keyboards ntawm tus ntxhais daim npav raws li hauv qab no:
2. Teem DIP hloov SW1 los qhia lub voos xwmfab ID 0:
   

   Hloov	Muaj nuj nqi	Kev teeb tsa
   1	CUB [0]	Qhib
   2	CUB [1]	Qhib
   3	CUB [2]	Qhib
   4	—	Tsis txhob txhawj

Teem DIP hloov SW2 kom qhia meej moos:

Hloov	Muaj nuj nqi	Kev teeb tsa
1	CLK1_FSEL0	Qhib (125 MHz)
2	CLK1_FSEL1	Qhib (125 MHz)
3	CLK1_SEL	Qhib (Crystal)
4	—	Tsis txhob txhawj

• Txuas HMC tus ntxhais daim npav rau Arria 10 FPGA Development Kit siv tus ntxhais daim npav J8 thiab J10 txuas.
• Teem lub jumpers ntawm Arria 10 GX FPGA Development Kit:
• Ntxiv shunts rau J8 jumper xaiv 1.5 V raws li qhov chaw VCCIO rau FMC connector B.
• Ntxiv shunts rau J11 jumper xaiv 1.8 V raws li VCCIO teeb tsa rau FMC connector A.

Compiling and Testing the Design Examphauv Hardware

Txhawm rau sau thiab khiav ib qho kev sim ua qauv qhia ntawm kev tsim kho vajtse example, ua raws li cov kauj ruam no

1. Xyuas kom hardware design example tiam tag.
2. Hauv Quartus Prime software, qhib qhov project Quartus Primeample_design_install_dir> /example_design/par/hmcc_examplwm qpf.
3. Nyob rau hauv Compilation Dashboard, nyem Compile Design (Intel Quartus Prime Pro Edition) los yog xaiv Kev Ua> Pib Tso Cai (Intel Quartus Prime Standard Edition).
4. Tom qab koj tsim ib .sof, ua raws li cov kauj ruam no los tsim kho kho vajtse example ntawm Arria 10 ntaus ntawv:
   1. Xaiv Cov Cuab Yeej> Programmer.
   2. Hauv Programmer, nyem Hardware Setup.
   3. Xaiv ib lub programming ntaus ntawv.
   4. Xaiv thiab ntxiv Arria 10 GX FPGA Development Kit uas koj qhov kev sib tham Quartus Prime tuaj yeem txuas tau.
   5. Xyuas kom meej tias hom yog teem rau JTAG.
   6. Nyem Auto Detect thiab xaiv ib qho khoom siv.
   7. Ob npaug nias rau Arria 10 ntaus ntawv.
   8. Qhib lub .sof hauvample_design_install_dir>/example_design/par/output_ files,
      Nco tseg: Lub Quartus Prime software hloov lub cuab yeej mus rau ib qho hauv .sof.
   9. Nyob rau hauv kab nrog koj .sof, khij lub npov nyob rau hauv qhov Program/Configure kem.
   10. Nyem Pib.
   11. Tom qab lub software configures lub cuab yeej nrog lub hardware tsim example, saib cov boards LEDs:
       1. Lub blinking liab LED qhia tias tus tsim tau khiav.
       2. Ob lub teeb ntsuab ntsuab nyob ze ntawm lub teeb liab liab LED qhia tias HMC txuas tau pib thiab qhov kev xeem dhau.
       3. Ib tug liab LED nyob ze ntawm lub liab blinking LED qhia tias qhov kev xeem ua tsis tau tejyam.
   12. xaiv tau. Siv qhov System Console testbench los soj ntsuam cov zis kuaj ntxiv.
       Nco tseg: Siv System Console los saib xyuas cov xwm txheej teeb liab hauv kev tsim example thaum lub rooj tsavxwm txuas nrog koj lub computer ntawm JTAG interface. Qhov System Console qhia lub rooj tsavxwm LED teeb meem rau kev saib xyuas tej thaj chaw deb, qhov pib txheej txheem rau txhua kauj ruam, thiab cov xwm txheej ntawm txhua qhov chaw nres nkoj qhov kev thov lub tshuab hluav taws xob thiab cov lus teb cov neeg kuaj xyuas. Lub System Console kuj tseem muaj qhov cuam tshuam los pib lossis rov pib qhov kev xeem.
       1. Xaiv Cov Cuab Yeej> Cov Cuab Yeej Debugging> System Console.
       2. Hauv System Console, xaiv File > Execute Script.
       3. Qhib lub file <example_design_install_dir>/example_design/par/sysconsole_ testbench.tcl.
       4. Lub software loads graphical xeem tso zis. Xaiv Re-start los khiav qhov kev sim dua.

Compiling and Testing the Design Examphauv Hardware

Hybrid Memory Cube Controller Tsim

Tsim Examplus piav qhia

Design example qhia txog kev ua haujlwm ntawm Hybrid Memory Cube Controller IP core. Koj tuaj yeem tsim qhov tsim los ntawm Example Tsim tab ntawm Hybrid Memory Cube Controller graphical user interface (GUI) hauv IP parameter editor.

Nta

• I2C tswv thiab I2C pib lub xeev tshuab rau HMC tus ntxhais daim npav thiab HMC teeb tsa
• ATX PLL thiab transceiver recalibration xeev tshuab
• Thov lub tshuab hluav taws xob
• Thov saib xyuas
• System Console interface

Hardware thiab Software Requirements
Altera siv cov cuab yeej kho vajtse thiab software hauv qab no los kuaj tus qauv tsim example:

• Intel Quartus Prime software
• System Console
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL nkaus xwb), lossis VCS simulator
• Arria 10 GX FPGA Development Kit
• HMC tus ntxhais daim npav

Functional Description

Altera muab kev sau ua ke-npaj tsim example nrog HMC Controller IP core. Qhov no tsim example lub hom phiaj Arria 10 GX FPGA Development Kit nrog HMC tus ntxhais daim npav txuas los ntawm FMC connectors.
Koj tuaj yeem siv tus qauv tsim ua tus example rau kev sib txuas kom raug ntawm koj tus IP tseem ceeb rau koj tus qauv tsim, lossis raws li tus qauv pib koj tuaj yeem hloov kho rau koj tus kheej tsim cov cai. Design example suav nrog I2C master module, PLL / CDR recalibration module, ib qho kev hloov pauv sab nraud PLL IP core, thiab cov laj thawj los tsim thiab txheeb xyuas kev lag luam. Design example assumes Micron HMC 15G-SR HMC ntaus ntawv, uas yog ib tug fourlink device, ntawm tus ntxhais card. Design example suav nrog ib qho piv txwv ntawm tus tub ntxhais IP thiab txuas rau ib qho txuas ntawm HMC ntaus ntawv. Daim duab 2-1: HMC Controller Design Exampthiab Block Diagram

Tom qab koj teeb tsa Arria 10 FPGA nrog tus tsim example, lub I2C maub los teeb tsa lub on-board moos generators thiab HMC ntaus ntawv. Thaum calibration tiav, tus tsim example calibrates ATX PLL. Thaum lub sijhawm ua haujlwm, lub tshuab hluav taws xob thov ua kom nyeem thiab sau cov lus txib uas HMC Controller IP core ces ua. Cov kev thov saib xyuas ntes cov lus teb los ntawm IP core thiab xyuas lawv kom raug.

Interface Signals
Table 2-1: HMC Controller IP Core Design Example Signals

Lub Npe Lub Npe cl_50	Kev taw qhia Tswv yim	Dav (ntsis) 1	Kev piav qhia 50 MHz input moos.
hssi_refclk	Tswv yim	1	CDR siv moos rau HMC thiab HMCC IP core.

Lub Npe Lub Npe hmc_lxrx	Kev taw qhia Tswv yim	Dav (ntsis) Channel suav (16 los yog 8)	Kev piav qhia FPGA transceiver txais pins.
hmc_lxtx	Tso zis	Channel suav (16 los yog 8)	FPGA transceiver kis tus pin.
hmc_ctrl_lxrxps	Tswv yim	1	FPGA transceiver zog txuag tswj.
hmc_ctrl_lxtxps	Tso zis	1	HMC transceiver fais fab txuag tswj.
hmc_ctrl_ferr_n	Tswv yim	1	HMC FERR_N tso zis.
hmc_ctrl_p_rst_n	Tso zis	1	HMC P_RST_N input.
hmc_ctrl_scl	Bi-Directional	1	HMC I2C configuration moos.
hmc_ctrl_sda	Bi-Directional	1	HMC I2C configuration data.
fmc0_scl	Tso zis	1	Tsis siv. Tsav qis los tiv thaiv FPGA I / O pins los ntawm 3.3 V rub rau ntawm daim npav tus ntxhais.
fmc0_sda	Tso zis	1	Tsis siv. Tsav qis los tiv thaiv FPGA I / O pins los ntawm 3.3 V rub rau ntawm daim npav tus ntxhais.
push_khawm	Tswv yim	1	Push khawm input siv rau pib dua.
heart_beat_n	Tso zis	1	Lub plawv dhia LED tso zis.
link_init_complete_n	Tso zis	1	Txuas kev pib ua kom tiav LED tso zis.
test_passed_n	Tso zis	1	Test dhau LED tso zis.
test_failed_n	Tso zis	1	Test ua tsis tau tejyam LED tso zis.

Tsim Example Register Map
Table 2-2: HMC Controller IP Core Design Example Register Map

Kev sau ntawv rau cov ntawv sau npe no rov pib tsim qauv.

Cov khoom 1:0 ua	Lub npe teb Chaw nres nkoj suav	Hom RO	Tus nqi ntawm Reset Ntau yam	Kev piav qhia Tus naj npawb ntawm cov chaw nres nkoj rau IP core piv txwv.
7:2 ua	Khaws tseg	RO	0 x 00

Table 2-4: BOARD_LEDs Sau npe
Daim ntawv teev npe no qhia txog cov xwm txheej ntawm pawg thawj coj saib LEDs

Cov khoom 0	Lub npe teb Kev Xeem Ua Tsis Tau	Hom RO	Tus nqi ntawm Reset 0 x 00	Kev piav qhia Kev xeem ua tsis tiav.
1	Xeem dhau lawm	RO	0 x 00	Kev xeem dhau.
2	HMCC Link Initialization tiav	RO	0 x 00	HMC txuas pib ua tiav thiab npaj rau kev khiav tsheb.
3	Lub plawv dhia	RO	0 x 00	Toggles thaum tus tsim ua haujlwm.
7:4 ua	Khaws tseg	RO	0 x 00

Table 2-5: TEST_INITIALIZATION_STATUS Sau npe

Cov khoom 0	Lub npe teb I2C Clock Generator Teeb	Hom RO	Tus nqi ntawm Reset 0 x 00	Kev piav qhia On-board moos generators configured.
1	ATX PLL thiab Transceiver Recalibration tiav	RO	0 x 00	ATX PLL thiab transceivers re-calibrated rau lub moos input.
2	I2C HMC Configuration tiav	RO	0 x 00	HMC ntaus ntawv teeb tsa dhau I2C ua tiav.
3	HMC Link Initialization Ua tiav	RO	0 x 00	HMC txuas pib ua tiav thiab npaj rau kev khiav tsheb.
7:4 ua	Khaws tseg	RO	0 x 00

Table 2-6: PORT_STATUS Sau npe

Cov khoom 0	Lub npe teb Chaw nres nkoj 0 Thov OK	Hom RO	Tus nqi ntawm Reset 0 x 00	Kev piav qhia Chaw nres nkoj 0 thov tsim tiav.
1	Chaw nres nkoj 0 Teb OK	RO	0 x 00	Chaw nres nkoj 0 teb kev kuaj xyuas dhau lawm.
2	Chaw nres nkoj 1 Thov OK	RO	0 x 00	Chaw nres nkoj 1 thov tsim tiav.
3	Chaw nres nkoj 1 Teb OK	RO	0 x 00	Chaw nres nkoj 1 teb kev kuaj xyuas dhau lawm.

Cov khoom 4	Lub npe teb Chaw nres nkoj 2 Thov OK	Hom RO	Tus nqi ntawm Reset 0 x 00	Kev piav qhia Chaw nres nkoj 2 thov tsim tiav.
5	Chaw nres nkoj 2 Teb OK	RO	0 x 00	Chaw nres nkoj 2 teb kev kuaj xyuas dhau lawm.
6	Chaw nres nkoj 3 Thov OK	RO	0 x 00	Chaw nres nkoj 3 thov tsim tiav.
7	Chaw nres nkoj 4 Teb OK	RO	0 x 00	Chaw nres nkoj 3 teb kev kuaj xyuas dhau lawm.

Cov ntaub ntawv ntxiv

HMC Controller Design Example User Guide Revision History
Table A-1: ​​Cov ntaub ntawv kho dua tshiab
Summizes tus tshiab nta thiab kev hloov nyob rau hauv tus tsim examptus neeg siv phau ntawv qhia rau HMC Controller IP core.

Hnub tim	ACDS Version	Hloov
2016.05.02	16.0	Kev tso tawm thawj zaug.

Yuav tiv tauj Intel li cas
Table A-2: Yuav Ua Li Cas Hu Rau Intel
Txhawm rau nrhiav cov ntaub ntawv tshiab tshaj plaws txog Intel cov khoom, xa mus rau lub rooj no. Koj tseem tuaj yeem tiv tauj koj lub chaw muag khoom hauv Intel lossis tus neeg muag khoom.

Hu rau	Txoj kev sib cuag	Chaw nyob
Kev txhawb nqa	Webqhov chaw	www.altera.com/support
Kev cob qhia txuj ci	Webqhov chaw	www.altera.com/training
	Email	FPGATraining@intel.com
Cov ntaub ntawv khoom	Webqhov chaw	www.altera.com/literature
Kev them nyiaj yug nontechnical: general	Email	nacomp@altera.com ua

Hu rau   Kev them nyiaj yug nontechnical: software ntawv tso cai

Txoj kev sib cuag   Email

Chaw nyob   authorization@altera.com

Cov ntaub ntawv ntsig txog

• www.altera.com/support
• www.altera.com/training
• cstrain@altera.com ib
• www.altera.com/literature
• nacomp@altera.com ua
• authorization@altera.com

Typographic Conventions

Table A-3: Typographic Conventions
Sau cov typographic conventions cov ntaub ntawv no siv

Lub tswv yim icon tso cai rau koj xa tawm tswv yim rau Altera txog cov ntaub ntawv. Cov txheej txheem los sau cov lus tawm tswv yim sib txawv raws li qhov tsim nyog rau txhua daim ntawv

Intel Corporation. Txhua txoj cai. Intel, Intel lub logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus thiab Stratix cov lus thiab lub logo yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom tes hauv Asmeskas thiab / lossis lwm lub tebchaws. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam.
Lwm lub npe thiab cov npe yuav raug lees paub tias yog cov cuab yeej ntawm lwm tus
101 Innovation Drive, San Jose, CA 95134

Hloov kho tshiab kawg rau Quartus Prime Design Suite: 16.0
UA-20027
2016.05.02
101 Tswvyim Tsav
San Jose, CA 95134
www.altera.com

Cov ntaub ntawv / Cov ntaub ntawv

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Cov ntaub ntawv

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