ALTERA Arria 10 Hybrid Memory Cube Controller Design Example

Tsararren ƙwaƙwalwar ƙwaƙwalwar ƙwaƙwalwar ƙwaƙwalwaampJagoran Mai Amfani yana ba da bayani kan ƙira da amfani da ƙirar kayan masarufi na Mai Kula da HMC Example. An sabunta jagorar don Quartus Prime Design Suite 16.0 kuma an sabunta shi a ƙarshe a kan Mayu 2, 2016.
Zane ExampLe Quick Start Guide yana ba da umarnin mataki-mataki don haɗawa, kwaikwayo, ƙirƙira, da gwada ƙirar HMC Controller ex.ample. Koma zuwa Hoto 1-1 don ƙarewaview na matakan ci gaba.

Zane Example Bayanin

Tsarin kayan aikin HMC Controller exampLe ya haɗa da abubuwa daban-daban kamar Board Arria 10 Na'ura, HMC Mai Kula da IP Core, Clocks & Sake saitin TX PLLs, Mai Rarraba Neman Bayanan Hanyar da Mai Kula da Amsa, TX/TX FIFO MAC, RX MAC, Gwajin Avalon-MM Control da LEDs, Mai Gudanarwa Matsayin Interface , Avalon-MM I 2C Master, Initialization State Machine, TX Lane Swapper, Transceiver x16, RX Lane Swapper, Arria 10 Transceiver Reconfiguration Interface, da HMC Na'urar. The exampzane yana buƙatar takamaiman saiti don aiki da kyau akan Arria 10 GX FPGA Development Kit tare da katin ɗiyar HMC.

Ƙarin Bayani

Sashen Ƙarin Bayani yana ba da cikakkun bayanai game da tsarin kundin adireshi don ƙirar ƙiraample, tarihin bita na jagorar mai amfani, ƙa'idodin rubutu da aka yi amfani da su a cikin jagorar, da yadda ake tuntuɓar Intel don tallafi.

Umarnin Amfani da samfur

Bi umarnin da ke ƙasa don amfani da ƙirar kayan aikin HMC Controller exampda:

1. Haɗa zane exampta amfani da na'urar kwaikwayo
2. Yi kwaikwayo na aiki
3. Ƙirƙirar ƙira example
4. Haɗa zane exampYi amfani da Quartus Prime
5. Gwada ƙirar kayan aikin

Lura cewa ƙirar hardware da gwaji files don zane example suna cikin /example_design/par, yayin da simulation files suna cikin /example_design/sim.

Don taimaka muku fahimtar yadda ake amfani da Hybrid Memory Cube Controller IP core, ainihin yana da simintin gwajin gwaji da ƙirar ƙirar kayan masarufi.ampwanda ke goyan bayan haɗawa da gwajin kayan aiki. Lokacin da ka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik fileya zama dole don kwaikwaya, tarawa, da gwada ƙira a cikin kayan masarufi. Kuna iya zazzage ƙirar da aka haɗa zuwa Intel® Arria® 10 GX FPGA Kit Development.

Bayanai masu alaƙa
Hybrid Memory Cube Controller IP Core User Guide

Zane Exampda Tsarin Jagora

Tsarin hardware da gwaji files (ƙirar kayan masarufi example) suna cikinample_ design_install_dir>/ misaliample_design/par. Simulation files (testbench don kwaikwayo kawai) suna cikinample_design_install_dir>/ misaliample_design/sim.

Zane ExampAbubuwan da aka gyara

Tsarin kayan aikin HMC Controller example ya ƙunshi abubuwa masu zuwa:

• HMC Controller IP core tare da agogon tunani na CDR saita zuwa 125 MHz kuma tare da tsoho taswirar RX da saitunan taswirar TX.
  Lura: Zane example yana buƙatar waɗannan saitunan suyi aiki da kyau akan Arria 10 GX FPGA Development Kit tare da katin 'yar HMC.
• Hankalin abokin ciniki wanda ke daidaita shirye-shiryen tushen tushen IP, da tsara fakiti da dubawa.
• JTAG mai sarrafawa wanda ke sadarwa tare da Altera System Console. Kuna sadarwa tare da dabarun abokin ciniki ta hanyar Console System.

Ya lissafa maɓalli files cewa aiwatar da exampda testbench.

/src/hmcc_example.sv	Babban matakin ƙirar hardware example file.
/sim/hmcc_tb.sv	Babban matakin file don kwaikwayo.
Rubutun Testbench Lura: Yi amfani da Samfuran da aka bayarfile don samar da waɗannan rubutun.
/sim/run_vsim.do	Rubutun ModelSim don gudanar da gwajin benci.
/sim/run_vcs.sh	Rubutun Synopsys VCS don gudanar da gwajin benci.
/sim/run_ncsim.sh	Rubutun Cadence NCsim don gudanar da testbench.

Samar da Zane Example

Hoto na 1-5: ExampLe forer tab a cikin mai kula da mai sarrafa Cube Perameter Edita

Bi waɗannan matakan don samar da ƙirar kayan aikin Arria 10 example da testbench:

1. A cikin Catalog na IP (Kayan aiki> Catalog na IP), zaɓi dangin na'urar da aka yi niyya ta Arria 10.
2. A cikin kasidar IP, gano wuri kuma zaɓi Mai Kula da Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Cube. Sabuwar taga Bambancin IP yana bayyana.
3. Ƙayyade sunan babban matakin don bambancin IP na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .qsys.
4. Dole ne ku zaɓi takamaiman na'urar Arria 10 a cikin filin Na'ura, ko kiyaye tsohuwar na'urar da Quartus Prime software ke zaɓa.
5. Danna Ok. Editan sigar IP yana bayyana.
6. A shafin IP, ƙididdige sigogi don ainihin bambancin IP ɗin ku.
7. A kan ExampDon Zane shafin, zaɓi saitunan masu zuwa don ƙira exampda:
   1. Don Zaɓi Zane, zaɓi zaɓi na Hukumar 'Yar HMCC.
   2. Don Exampda Design Files, zaɓi zaɓin Simulation don samar da testbench, kuma zaɓi zaɓi na Synthesis don samar da ƙirar ƙirar kayan aiki.ample.
   3. Don Haɓaka Tsarin HDL, Verilog kawai yana samuwa.
   4. Don Kit ɗin Ci gaban Target zaɓi Arria 10 GX FPGA Development Kit (Silicon Samar da).
      Lura: Lokacin da kuka zaɓi wannan kit, ƙirar ƙirar kayan aiki exampLe overwrites your baya na'urar zabin tare da na'urar a kan manufa jirgin. Lokacin da ka samar da zane exampHar ila yau, Intel Quartus Prime software ya haifar da Intel
      Ayyukan Quartus Prime, saiti, da ayyukan fil na hukumar da kuka zaɓa. Idan ba ka son software ta yi niyya ga takamaiman allo, zaɓi Babu.
8. Danna Generate Example Design button

Fahimtar Testbench

Altera yana ba da ƙirar ƙiraamptare da HMC Controller IP core. Zane exampLe yana samuwa duka don simulation na IP core da kuma don haɗawa. Zane exampLe in simulation ayyuka a matsayin HMC Controller IP core testbench.
Idan ka danna Generate ExampTsara a cikin editan siga na HMC Controller, software na Quartus Prime yana haifar da gwajin gwaji. Editan sigar yana sa ku ga wurin da ake so na testbench.
Don yin kwaikwayi gwajin benci, dole ne ku samar da naku samfurin aikin bas na HMC (BFM). Altera yana gwada ƙira example testbench tare da Micron Hybrid Memory Cube BFM. Testbench ba ya haɗa da babban tsarin I2C, saboda Micron HMC BFM ba ya goyan bayan kuma baya buƙatar daidaitawa ta tsarin I2C.
A cikin simulation, testbench yana sarrafa TX PLL da hanyoyin hanyoyin bayanai don aiwatar da jerin ayyuka masu zuwa:

1. Yana saita HMC BFM tare da HMC Controller IP ainihin ƙimar bayanai da faɗin tashoshi, a cikin Yanayin Buɗe Madauki na Amsa.
2. Yana kafa hanyar haɗi tsakanin BFM da IP core.
3. Yana jagorantar kowane tashar jiragen ruwa huɗu na IP core don rubuta fakitin bayanai huɗu zuwa BFM.
4. Yana jagorantar tushen IP don karanta baya bayanan daga BFM.
5. Yana duba cewa bayanan da aka karanta sun yi daidai da bayanan rubuta.
6. Idan bayanan sun yi daidai, suna nuna TEST_PASSED.

Simulating da Design Exampda Testbench
Hoto 1-6: Tsari

Bi waɗannan matakan don kwaikwaya testbench:

1. A layin umarni, canza zuwaample>/ sim directory.
2. Buga rubutun yin rubutun.
3. Buga ɗaya daga cikin umarni masu zuwa, dangane da na'urar kwaikwayo:
4. Zuwa view sakamakon kwaikwayo:
   1. Lokacin da kake gudanar da testbench a cikin kowane ɗayan na'urorin kwaikwayo guda uku da aka goyan baya, rubutun yana aiwatar da jerin gwaje-gwajen kuma ya rubuta ayyukan na'urar a ciki.ampda directory>/misaliample_ design/sim/ .log. shine "vsim", "ncsim", ko "vcs".
   2. Lokacin da kake gudanar da gwajin benci a kowane ɗayan na'urorin kwaikwayo guda uku da aka goyan baya, rubutun yana haifar da yanayin motsi file. Kuna iya gudanar da umarnin yin umarni _gui don loda tsarin igiyar ruwa a cikin ƙayyadaddun yanayin motsi na na'urar kwaikwayo viewer.
      Zuwa view da kalaman kalaman file a cikin na'urar kwaikwayo, rubuta ɗaya daga cikin umarni masu zuwa:

      Lasisi na Simulator Model Zane-zane na Mentor	Layin Umurni yi vsim_gui	Waveform File <design exampda directory>/example_design/sim/ mentor/hmcc_wf.wlf
      Synopsys Gano Kayayyakin Kayayyakin Kayayyakin	yi vcs_gui	<design exampda directory>/example_design/sim/ hmcc_wf.vpd
      Cadence SimVision Waveform	yi ncsim_gui	<design exampda directory>/example_design/sim/ cadence/hmcc_wf.shm
5. Yi nazarin sakamakon. Babban testbench mai nasara yana aikawa da karɓar fakiti goma a kowane tashar jiragen ruwa, kuma yana nuna Test_PASSED"

Kafa Hukumar

Saita allon don gudanar da ƙirar kayan masarufi example.
Lura: Tabbatar cewa an kashe wuta kafin ku canza kowane saiti.

1. Saita maɓallin DIP akan katin 'yar kamar haka:
2. Saita DIP sauya SW1 don nuna kubu ID 0:
   

   Sauya	Aiki	Saita
   1	KUB[0]	Bude
   2	KUB[1]	Bude
   3	KUB[2]	Bude
   4	—	Karka Kula

Saita DIP sauya SW2 don tantance saitunan agogo:

Sauya	Aiki	Saita
1	CLK1_FSEL0	Bude (125 MHz)
2	CLK1_FSEL1	Bude (125 MHz)
3	CLK1_SEL	Bude (Crystal)
4	—	Karka Kula

• Haɗa katin ɗiyar HMC zuwa Arria 10 FPGA Development Kit ta amfani da masu haɗin katin ɗiyar J8 da J10.
• Saita masu tsalle a kan Arria 10 GX FPGA Development Kit:
• Ƙara shunts zuwa J8 jumper don zaɓar 1.5 V azaman saitin VCCIO don haɗin FMC B.
• Ƙara shunts zuwa J11 jumper don zaɓar 1.8 V azaman saitin VCCIO don haɗin FMC A.

Haɗawa da Gwajin Zane Exampa cikin Hardware

Don haɗawa da gudanar da gwajin gwaji akan ƙirar kayan masarufi example, bi waɗannan matakan

1. Tabbatar da ƙirar hardware example tsara ya cika.
2. A cikin software na Quartus Prime, buɗe aikin Quartus Primeample_design_install_dir>/example_design/par/hmcc_exampku.qpf.
3. A cikin Dashboard ɗin Rubutun, danna Ƙirƙirar Ƙira (Intel Quartus Prime Pro Edition) ko zaɓi Gudanarwa> Fara Tari (Intel Quartus Prime Standard Edition).
4. Bayan kun ƙirƙiri .sof, bi waɗannan matakan don tsara ƙirar ƙirar kayan aikiampa kan na'urar Arria 10:
   1. Zaɓi Kayan aiki > Mai shirye-shirye.
   2. A cikin Programmer, danna Saitin Hardware.
   3. Zaɓi na'urar shirye-shirye.
   4. Zaɓi kuma ƙara Arria 10 GX FPGA Development Kit wanda zaman ku na Quartus Prime zai iya haɗawa.
   5. Tabbatar cewa an saita Yanayin zuwa JTAG.
   6. Danna Gane atomatik kuma zaɓi kowace na'ura.
   7. Danna na'urar Arria 10 sau biyu.
   8. Bude .sof inample_design_install_dir>/ misaliample_design/par/fitarwa_ files,
      Lura: The Quartus Prime software yana canza na'urar zuwa wacce ke cikin .sof.
   9. A cikin jere tare da .sof ɗinku, duba akwatin a cikin ginshiƙin Shirin/Sanya.
   10. Danna Fara.
   11. Bayan software ya daidaita na'urar tare da ƙirar hardware example, lura da allon LEDs:
       1. LED ja mai kyaftawa yana nuna ƙirar tana gudana.
       2. Ledojin kore guda biyu kusa da jajayen LED mai kyaftawa suna nuna cewa an fara hanyar haɗin HMC kuma gwajin ya wuce.
       3. Jajayen LED guda ɗaya kusa da jajayen LED mai kyaftawa yana nuna cewa gwajin ya faskara.
   12. Na zaɓi. Yi amfani da na'urar gwaji ta System Console don lura da ƙarin fitarwar gwaji.
       Lura: Yi amfani da na'ura mai ba da hanya tsakanin hanyoyin sadarwa don saka idanu da siginonin matsayi a cikin ƙirar ƙiraamplokacin da aka haɗa allo zuwa kwamfutarka ta hanyar JTAG dubawa. The System Console yana nuna matsayin LED na hukumar don saka idanu mai nisa, matsayin farawa na kowane mataki, da matsayin janareta na buƙatun kowane tashar jiragen ruwa da mai duba martani. Hakanan tsarin Console yana ba da hanyar sadarwa don farawa ko sake farawa gwajin.
       1. Zaɓi Kayan aiki > Kayan aikin Gyaran Tsari > Na'ura mai kwakwalwa.
       2. A cikin System Console, zaɓi File > Yi Rubutun.
       3. Bude file <example_design_install_dir>/ misaliample_design/par/sysconsole_ testbench.tcl.
       4. Software yana loda kayan aikin gwaji na hoto. Zaɓi Sake farawa don sake gudanar da gwajin.

Haɗawa da Gwajin Zane Exampa cikin Hardware

Haɓaka Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Cube Mai Sarrafa

Zane Example Bayanin

Zane example yana nuna aikin Hybrid Memory Cube Controller IP core. Kuna iya samar da zane daga ExampZaƙi shafin na Hybrid Memory Cube Controller graphical user interface (GUI) a cikin editan sigar IP.

Siffofin

• I2C master da I2C farawa injin jihar don katin 'yar HMC da daidaitawar HMC
• ATX PLL da transceiver recalibration state machine
• Nemi janareta
• Nemi saka idanu
• Keɓancewar tsarin Console

Bukatun Hardware da Software
Altera yana amfani da kayan masarufi da software masu zuwa don gwada ƙirar ƙiraampda:

• Intel Quartus Prime software
• Tsarin Console
• ModelSim-AE, Modelsim-SE, NCsim (Verilog HDL kawai), ko na'urar kwaikwayo ta VCS
• Arria 10 GX FPGA Development Kit
• HMC yar katin

Bayanin Aiki

Altera yana ba da tsarin ƙira da aka shirya examptare da HMC Controller IP core. Wannan zane exampLe ya kai hari ga Arria 10 GX FPGA Development Kit tare da katin 'yar HMC da aka haɗa ta masu haɗin FMC.
Kuna iya amfani da zane azaman exampdon daidai hanyar haɗin IP ɗin ku zuwa ƙirar ku, ko azaman ƙirar farawa zaku iya keɓance don buƙatun ƙirar ku. Zane exampLe ya haɗa da babban tsarin I2C, tsarin gyarawa na PLL/CDR, mai ɗaukar hoto ɗaya na PLL IP core, da dabaru don samarwa da duba ma'amaloli. Zane example yana ɗaukar na'urar HMC Micron HMC 15G-SR, wanda shine fourlna'urar tawada, akan katin 'yar. Zane example ya haɗa da misali guda ɗaya na ainihin IP kuma yana haɗi zuwa hanyar haɗi guda ɗaya akan na'urar HMC. Hoto 2-1: HMC Controller Design Exampda Block zane

Bayan kun saita Arria 10 FPGA tare da ƙirar exampHar ila yau, mai kula da I2C yana daidaita masu samar da agogon kan jirgin da na'urar HMC. Lokacin da calibration ya kammala, ƙirar exampLe calibrates ATX PLL. Yayin aiki, janareta na buƙatun yana haifar da karantawa da rubuta umarni waɗanda HMC Controller IP core sannan aiwatarwa. Mai saka idanu na buƙatun yana ɗaukar martani daga ainihin IP kuma yana bincika su don daidaito.

Siginonin Sadarwa
Tebur 2-1: Mai Kula da HMC IP Core Design Exampda Sigina

Sunan siginar clk_50	Hanyar Shigarwa	Nisa (Bits) 1	Bayani Agogon shigarwa 50 MHz.
hssi_refclk	Shigarwa	1	Agogon tunani na CDR don HMC da HMCC IP core.

Sunan siginar hmc_lxrx	Hanyar Shigarwa	Nisa (Bits) Ƙididdiga ta Channel (16 ko 8)	Bayani FPGA transceiver yana karɓar fil.
hmc_lxtx	Fitowa	Ƙididdiga ta Channel (16 ko 8)	FPGA transceiver watsa fil.
hmc_ctrl_lxrxps	Shigarwa	1	FPGA transceiver ikon ajiye iko.
hmc_ctrl_lxtxps	Fitowa	1	HMC transceiver ikon ajiye iko.
hmc_ctrl_ferr_n	Shigarwa	1	HMC FERR_N fitarwa.
hmc_ctrl_p_rst_n	Fitowa	1	Shigar HMC P_RST_N.
hmc_ctrl_scl	Bi-Directional	1	HMC I2C sanyi agogo.
hmc_ctrl_sda	Bi-Directional	1	Bayanan Bayani na HMC I2C.
fmc0_scl	Fitowa	1	Ba a yi amfani da shi ba. Kora ƙasa don kare FPGA I/O fil daga 3.3 V a kan katin 'yar.
fmc0_sda	Fitowa	1	Ba a yi amfani da shi ba. Kora ƙasa don kare FPGA I/O fil daga 3.3 V a kan katin 'yar.
tura_button	Shigarwa	1	Shigar da maɓallin danna da aka yi amfani da shi don sake saiti.
bugun zuciya_n	Fitowa	1	Fitar da bugun zuciya na LED.
link_init_complete_n	Fitowa	1	Ƙaddamar da haɗin haɗin kai cikakke fitarwa na LED.
gwada_cire_n	Fitowa	1	Gwajin ya wuce fitowar LED.
gwajin_ kasa_n	Fitowa	1	Gwajin ya kasa fitar da LED.

Zane Exampda Rajista taswira
Tebur 2-2: Mai Kula da HMC IP Core Design Exampda Rajista taswira

Rubutu zuwa waɗannan rajistar yana sake saita ƙira.

Bits 1:0	Sunan Filin Ƙidaya Port	Nau'in RO	Darajar akan Sake saiti Ya bambanta	Bayani Adadin tashoshin jiragen ruwa don misali na ainihin IP.
7:2	Ajiye	RO	0 x00

Tebur 2-4: BOARD_LEDs Rajista
Wannan rijistar tana nuna matsayin ledojin hukumar

Bits 0	Sunan Filin Gwajin ya gaza	Nau'in RO	Darajar akan Sake saiti 0 x00	Bayani Gwajin ya ci tura.
1	Gwaji Ya Cire	RO	0 x00	Gwaji ya wuce.
2	Haɗin HMCC Ya Kammala	RO	0 x00	Haɗin HMC ya cika kuma a shirye don zirga-zirga.
3	bugun zuciya	RO	0 x00	Juyawa lokacin da ƙirar ke gudana.
7:4	Ajiye	RO	0 x00

Tebur 2-5: TEST_INITIALIZATION_STATUS Rajista

Bits 0	Sunan Filin I2C Clock Generator Saita	Nau'in RO	Darajar akan Sake saiti 0 x00	Bayani An saita janareta na agogon kan jirgi.
1	ATX PLL da Transceiver Recalibration Complete	RO	0 x00	ATX PLL da transceivers an sake daidaita su zuwa agogon shigarwa.
2	Saukewa: HMC2C Kanfigareshan Ya Kammala	RO	0 x00	Tsarin na'urar HMC akan I2C cikakke.
3	Haɗin HMC ya Kammala	RO	0 x00	Haɗin HMC ya cika kuma a shirye don zirga-zirga.
7:4	Ajiye	RO	0 x00

Tebur 2-6: PORT_STATUS Rajista

Bits 0	Sunan Filin Port 0 Buƙatun Ok	Nau'in RO	Darajar akan Sake saiti 0 x00	Bayani Port 0 buƙatun ya cika.
1	Tashar jiragen ruwa 0 Martani yayi kyau	RO	0 x00	Duban martani na tashar jiragen ruwa 0 ya wuce.
2	Port 1 Buƙatun Ok	RO	0 x00	Port 1 buƙatun ya cika.
3	Tashar jiragen ruwa 1 Martani yayi kyau	RO	0 x00	Duban martani na tashar jiragen ruwa 1 ya wuce.

Bits 4	Sunan Filin Port 2 Buƙatun Ok	Nau'in RO	Darajar akan Sake saiti 0 x00	Bayani Port 2 buƙatun ya cika.
5	Tashar jiragen ruwa 2 Martani yayi kyau	RO	0 x00	Duban martani na tashar jiragen ruwa 2 ya wuce.
6	Port 3 Buƙatun Ok	RO	0 x00	Port 3 buƙatun ya cika.
7	Tashar jiragen ruwa 4 Martani yayi kyau	RO	0 x00	Duban martani na tashar jiragen ruwa 3 ya wuce.

Ƙarin Bayani

HMC Controller Design ExampTarihin Bita Jagoran Mai Amfani
Tebur A-1: ​​Tarihin Bita na Takardu
Yana taƙaita sabbin abubuwa da canje-canje a cikin ƙira exampJagorar mai amfani don HMC Controller IP core.

Kwanan wata	Sigar ACDS	Canje-canje
2016.05.02	16.0	Sakin farko.

Yadda ake Tuntuɓar Intel
Tebur A-2: Yadda ake Tuntuɓar Intel
Don nemo mafi sabunta bayanai game da samfuran Intel, koma zuwa wannan tebur. Hakanan zaka iya tuntuɓar ofishin tallace-tallace na Intel na gida ko wakilin tallace-tallace.

Tuntuɓar	Hanyar Tuntuɓa	Adireshi
Goyon bayan sana'a	Website	www.altera.com/support
Koyarwar fasaha	Website	www.altera.com/training
	Imel	FPGATraining@intel.com
Adabin samfur	Website	www.altera.com/literature
Taimakon mara fasaha: gabaɗaya	Imel	nacomp@altera.com

Tuntuɓar   Tallafin mara fasaha: lasisin software

Hanyar Tuntuɓa   Imel

Adireshi   izini@altera.com

Bayanai masu alaƙa

• www.altera.com/support
• www.altera.com/training
• custrain@altera.com
• www.altera.com/literature
• nacomp@altera.com
• izini@altera.com

Yarjejeniyar Rubutu

Tebur A-3: Yarjejeniyar Rubutu
Ya lissafa ƙa'idodin rubutu da wannan takaddar ke amfani da ita

Alamar martani tana ba ku damar ƙaddamar da martani ga Altera game da takaddar. Hanyoyin tattara ra'ayoyin sun bambanta kamar yadda ya dace ga kowace takarda

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus da Stratix kalmomi da tambura alamun kasuwanci ne na Intel Corporation ko rassan sa a Amurka da/ko wasu ƙasashe. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu
101 Innovation Drive, San Jose, CA 95134

An sabunta ta ƙarshe don Quartus Prime Design Suite: 16.0
Saukewa: UG-20027
2016.05.02
101 Innovation Drive
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