intel Afa 10 Native FloatingPoint DSP FPGA IP
Intel® Cyclone® 10 GX Native Floating Point DSP Intel® FPGA IP User Guide
Fa'ata'atia le Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP
Filifili ta'iala 'ese'ese e fai ai se IP fa'atatau mo lau mamanu.
- I le Intel® Quartus® Prime Pro Edition, faia se poloketi fou e faʻatatau i se masini Intel Cyclone® 10 GX.
- I le IP Catalog, kiliki ile Library ➤ DSP ➤ Primitive DSP ➤ Intel Cyclone 10 GX Native Floating Point DSP.
O le Intel Cyclone 10 GX Native Floating-Point DSP IP Core IP fa'atonu e tatala. - I le New IP Variation dialog box, ulufale i se Igoa Fa'alapotopotoga ma kiliki le OK.
- I lalo o Parameters, filifili le DSP Template ma le View e te manaʻo mo lau IP autu
- I le DSP Block View, sui le uati po'o le toe setiina o tusi resitala aoga taitasi.
- Mo Multiply Add or Vector Mode 1, kiliki i le Chain In multiplexer i le GUI e filifili ai mea mai le chainin port poʻo le Ax port.
- Kiliki le Fa'ailoga Fa'aopoopo i le GUI e filifili fa'aopoopo po'o toese.
- Kiliki i luga o le Chain Out multiplexer i le GUI e mafai ai ona faʻaogaina le taulaga.
- Kiliki Fausia HDL.
- Kiliki Fa'auma.
Intel Cyclone 10 GX Native Floating Point DSP Intel FPGA IP Parameter
Laulau 1. Parameter
| Parameter | Taua | Tau Fa'atonu | Fa'amatalaga |
| Fa'ata'ita'iga DSP | Fa'atele Faaopoopo
Fa'atele Fa'aopoopo Fa'ateleina Fa'aputuina Fa'a Vector 1 Faiga Vector 2 |
Fa'atele | Filifili le faiga fa'atinoina mo le poloka DSP.
O le gaioiga filifilia o loʻo atagia i le DSP poloka View. |
| View | Resitala Fa'aagaina le Resitala Fa'amama | Resitala Fa'aaga | Filifiliga e filifili ai le polokalame uati po'o le toe setiina o le polokalame mo resitala view. O le gaioiga filifilia o loʻo atagia i le DSP poloka View. |
| faaauau… | |||
| Parameter | Taua | Tau Fa'atonu | Fa'amatalaga |
| Filifili Resitala Fa'aaga mo DSP poloka View e fa'aali atu le faiga o le fa'ailo o tusi resitala. E mafai ona e suia uati mo resitara taitasi i lenei view.
Filifili Fa'amama le Resitala mo DSP poloka View e fa'aali tusi resitala polokalame toe setiina. Ki Fa'aoga Tasi Ta'itasi e sui le polokalame toe setiina resitala. |
|||
| Fa'aoga Tasi Ta'itasi | Ki pe pe | Tape | Fa'aola lenei ta'otoga pe afai e te mana'o i se seti se tasi e toe fa'afo'i uma resitala i le poloka DSP. Tape le ta'otoga lenei e fa'aoga ai ports toe setiina e toe seti ai tusi resitala.
Fa'aola mo le manino 0 ile tusi resitala o galuega; tape mo le manino 1 i luga o le tusi resitala o galuega. Fa'amama 0 mo tusi resitala fa'aoga fa'aoga aclr[0] faailoilo. Fa'amama 1 mo le fa'aogaina o galuega fa'atino ma resitara paipa aclr[1] faailoilo. O tusi resitala uma e fa'aoga ai le aclr[0] reset signal. E fa'aaoga uma e tusi resitala galuega ma paipa aclr[1] reset signal. |
| DSP View Poloka. | |||
| filifili i le teleplexer (14) | Faʻaleleia le avanoa | Fa'agata | Kiliki i luga ole multiplexer e mafai ai le chainin
uafu. |
| Filifiliga Fa'atele (12) | Faʻaleaoga Enable | Fa'agata | Kiliki i luga o le multiplexer e mafai ai le chainout
uafu. |
| Fa'aopoopo (13) | +
– |
+ | Kiliki ile Fa'aopoopo fa'ailoga e filifili ai le fa'aopoopo po'o le toese. |
| Resitala Uati
• ax_clock (2) • ua_ua (3) • az_clock (4) • tele_pipeline_clock k(5) • ax_chainin_pl_clock k (7) • adder_input_clock (9) • adder_input_2_clo ck (10) • uati_tulaga (11) • accumulate_clock (1) • accum_pipeline_cl ock (6) • accum_adder_clock k (8) |
Leai Uati 0
Uati 1 Uati 2 |
Uati 0 | Ina ia pasia so'o se tusi resitala, kili le uati resitala i Leai.
Su'e le uati resitala i: • Uati 0 e fa'aaoga le clk[0] faailo e fai ma puna o le uati • Uati 1 e fa'aaoga le clk[1] faailo e fai ma puna o le uati • Uati 2 e fa'aaoga le clk[2] faailo e fai ma puna o le uati E faatoa mafai ona e suia nei faatulagaga pe a e filifilia Resitala Fa'aaga in View fa'ata'oto. |
Ata 1. Poloka DSP View
Laulau 2. Fa'ata'ita'iga DSP
| Fa'ata'ita'iga DSP | Fa'amatalaga |
| Fa'atele | Fa'atino le fa'atelega sa'o e tasi ma fa'aoga le fa'atusa lea:
• I fafo = Ay * Az |
| Faaopoopo | Fa'atino fa'aopoopo sa'o tasi po'o le to'esega ma fa'aoga fa'atusa nei:.
• Out = Ay + Ax • Out = Ay – Ax |
| Faatele Faaopoopo | O lenei faiga e fa'atino ai le fa'atelega sa'o e tasi, soso'o ai ma le fa'aopoopo po'o le to'ese ma fa'aoga tutusa nei.
• Out = (Ay * Az) – chainin • I fafo = (Ay * Az) + chainin • Out = (Ay * Az) – Ax • I fafo = (Ay * Az) + Ax |
| Fa'ateleina Fa'aputu | Fa'atino le fa'atele-va'aiga fa'atele ona soso'o ai lea ma le fa'aopoopo po'o le to'ese o le mata'u fa'afefe ma le i'uga o le fa'atele talu ai ma fa'aoga tutusa nei:
• Out(t) = [Ay(t) * Az(t)] – Out(t-1) pe a fa'aputu. fa'ailoga ua fa'aoso maualuga. • Out(t) = [Ay(t) * Az(t)] + Out (t-1) pe a fa'aputu maualuga uafu. • Out(t) = Ay(t) * Az(t) pe a fa'aputu le taulaga ua fa'alalo ifo. |
| Faiga Vector 1 | Fa'atino le fa'atele o mata'itala soso'o soso'o ai ma le fa'aopoopo po'o le to'ese o le togi fa'a'a'e mai le poloka DSP fesuia'i muamua ma fa'aoga tutusa nei:. |
| faaauau… | |
| Fa'ata'ita'iga DSP | Fa'amatalaga |
| • Out = (Ay * Az) – chainin
• I fafo = (Ay * Az) + chainin • Out = (Ay * Az) , chainout = Ax |
|
| Faiga Vector 2 | Fa'atino le fa'atelega fa'afefeteina pe a fafaga e le IP core le fa'ateleina fa'ai'uga e sa'o i le filifili. Ona faaopoopo lea e le IP core pe toesea le chainin input mai le poloka DSP fesuia'i muamua mai le Ax input e fai ma taunuuga o galuega.
O lenei faiga e fa'aoga tutusa ai: • I fafo = Ax – chainin , chainout = Ay * Az • I fafo = Ax + chainin , chainout = Ay * Az • Out = Ax , chainout = Ay * Az |
Intel Cyclone 10 GX Native Floating Point DSP Intel FPGA IP Signals
Ata 2. Intel Cyclone 10 GX Native Floating Point DSP Intel FPGA IP Signals
O le ata o loʻo faʻaalia ai faʻailoga faʻaoga ma faʻailoga o le IP core.
Laulau 3. Intel Cyclone 10 GX Native Floating Point DSP Intel FPGA IP Input Signals
| Igoa Faailoga | Ituaiga | Lautele | Fa'atonu | Fa'amatalaga |
| matau[31:0] | Ulufale | 32 | Maulalo | Tu'u le pasi fa'amaumauga i le fa'atele. Avanoa ile:
• Fa'aopoopo faiga • Fa'atele-Fa'aopoopo faiga e aunoa ma le filifili filifili ma le fa'ailoga filifili • Faiga Vector 1 • Faiga Vector 2 |
| a[31:0] | Ulufale | 32 | Maulalo | Tu'u le pasi fa'amaumauga i le fa'atele.
E maua i faiga fa'a'au'a'ega uma. |
| ase[31:0] | Ulufale | 32 | Maulalo | Tu'u le pasi fa'amaumauga i le fa'atele. Avanoa ile:
• Faateleina • Faatele Faaopoopo • Fa'ateleina Fa'aputu • Faiga Vector 1 • Faiga Vector 2 |
| filifili[31:0] | Ulufale | 32 | Maulalo | Fa'afeso'ota'i nei fa'ailo i fa'ailo fa'ai'au mai le DSP IP core o lo'o muamua atu. |
| clk[2:0] | Ulufale | 3 | Maulalo | Tu'u fa'ailoga uati mo tusi resitala uma.
E na'o avanoa nei fa'ailo o le uati pe a fa'apipi'i se tusi resitala o fa'aoga, resitara o paipa, po'o le resitala o galuega Uati0 or Uati1 or Uati2. |
| ena[2:0] | Ulufale | 3 | Maualuga | E mafai e le uati mo clk[2:0]. O nei faailoilo e gaioi-maualuga.
• ena[0] e mo Uati0 • ena[1] e mo Uati1 • ena[2] e mo Uati2 |
| aclr[1:0] | Ulufale | 2 | Maulalo | Fa'ailo fa'aoga manino le fa'aogaina mo resitara uma. O nei faailo e malosi-maualuga.
Fa'aoga aclr[0] mo tusi resitala uma ma fa'aoga aclr[1] mo resitara uma o paipa ma galuega. |
| fa'aputu | Ulufale | 1 | Maulalo | Fa'ailo fa'aulu e mafai ai pe fa'amalo ai le vaega fa'aputu.
• Fa'ailoa le fa'ailo lea ina ia mafai ai ona fa'aalia le fa'atinoina o galuega a le fa'aopoopo. • Aveese le fa'amaonia o lenei fa'ailo e fa'amalo ai le faiga o fa'amatalaga. E mafai ona e fa'ailoa pe fa'amalo le fa'ailo lea i le taimi o le ta'avale. E maua ile Multiply Accumulate mode. |
| filifili[31:0] | Tuuina atu | 32 | — | Fa'afeso'ota'i nei fa'ailoga i fa'ailoga filifili o le isi fa'a'au'au fa'anofoa DSP IP core. |
| i'uga[31:0] | Tuuina atu | 32 | — | Fa'amatalaga pasi fa'amatalaga mai IP autu. |
Talafaasolopito Toe Iloiloga o Pepa
Suiga ile Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP User Guide
| Aso | Fa'aliliuga | Suiga |
| Novema 2017 | 2017.11.06 | Fa'asalalauga muamua. |
Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
Pepa / Punaoa
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intel Afa 10 Native FloatingPoint DSP FPGA IP [pdf] Taiala mo Tagata Fa'aoga Afa 10 Native FloatingPoint DSP FPGA IP, 10 Native FloatingPoint DSP FPGA IP, Native FloatingPoint DSP FPGA IP, FloatingPoint DSP FPGA IP, DSP FPGA IP, FPGA IP |
