intel Cyclone 10 Native FloatingPoint DSP FPGA IP
Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide
Parameterizing iyo Intel® Cyclone® 10 GX Native Inoyangarara-Point DSP Intel® FPGA IP
Sarudza akasiyana ma paramita kugadzira IP musimboti wakakodzera dhizaini yako.
- MuIntel® Quartus® Prime Pro Edition, gadzira chirongwa chitsva chakanangana neIntel Cyclone® 10 GX mudziyo.
- Mu IP Catalog, tinya pakaraibhurari ➤ DSP ➤ Primitive DSP ➤ Intel Cyclone 10 GX Native Floating Point DSP.
Iyo Intel Cyclone 10 GX Native Floating-Point DSP IP Core IP parameter mupepeti inovhura. - MuNew IP Variation dialog box, isa Zita reChipo uye tinya OK.
- Pasi peParameters, sarudza iyo DSP template uye iyo View iwe unoda yako IP musimboti
- MuDSP Block View, shandura wachi kana kuseta patsva rerejista yega yega.
- ZveKuwanza Wedzera kana Vector Mode 1, tinya paChain In multiplexer muGUI kusarudza mapindiro kubva kuchainin port kana Ax port.
- Dzvanya chiratidzo cheAdder muGUI kuti usarudze kuwedzera kana kubvisa.
- Dzvanya paChain Out multiplexer muGUI kugonesa chainout port.
- Dzvanya Gadzira HDL.
- Dzvanya Finish.
Intel Cyclone 10 GX Native Inoyangarara-Point DSP Intel FPGA IP Parameters
Tafura 1. Parameters
| Parameter | Value | Default Value | Tsanangudzo |
| DSP template | Wanza Wedzera
Wedzera Wedzera Kuwedzera Kuunganidza Vector Mode 1 Vector Mode 2 |
Wanza | Sarudza yaunoda mashandiro maitiro eiyo DSP block.
Basa rakasarudzwa rinoratidzwa mu DSP Block View. |
| View | Rejista Inogonesa Rejista Yakachena | Register Inobvumira | Sarudzo dzekusarudza clocking scheme kana reset scheme yemarejista view. Basa rakasarudzwa rinoratidzwa mu DSP Block View. |
| akaenderera… | |||
| Parameter | Value | Default Value | Tsanangudzo |
| Sarudza Register Inobvumira nokuti DSP Block View kuratidza marejista clocking scheme. Iwe unogona kushandura wachi kune imwe neimwe yerejista mune izvi view.
Sarudza Register Clears nokuti DSP Block View kuratidza marejista reset scheme. Batidza Shandisa Single Clear kushandura regist reset scheme. |
|||
| Shandisa Single Clear | Kudzima kana kudzima | Off | Batidza iyi paramende kana iwe uchida kuseta imwe chete kuseta zvakare marejista muDSP block. Dzima iyi parameter kuti ushandise akasiyana reset ports kugadzirisa zvakare marejista.
Batidza kuti ujekese 0 pane inobuda rejista; dzima kujekesa 1 pane inobuda rejista. Bvisa 0 kune marejista ekuisa anoshandisa aclr[0] chiratidzo. Bvisa 1 yezvinobuda uye marejista epombi anoshandiswa aclr[1] chiratidzo. Ese marejista ekuisa anoshandisa aclr[0] reset chiratidzo. Zvese zvinobuda uye marejista epombi anoshandisa aclr[1] reset chiratidzo. |
| DSP View Block. | |||
| Chain In Multiplexer (14) | Gonesa Disable | Disable | Dzvanya pane multiplexer kugonesa chainin
port. |
| Chain Out Multiplexer (12) | Dzima Enable | Disable | Dzvanya pane multiplexer kuti ugonese chainout
port. |
| Adder (13) | +
– |
+ | Dzvanya pa Adder chiratidzo chekusarudza kuwedzera kana kubvisa modhi. |
| Register Clock
• ax_clock (2) • ay_clock (3) • az_clock (4) • mult_pipeline_clock k(5) • ax_chainin_pl_clock k (7) • adder_input_clock (9) • adder_input_2_clock ck (10) • output_clock (11) • accumula_clock (1) • accum_pipeline_cl ock (6) • accum_adder_cloc k (8) |
Hapana Wachi 0
Wachi 1 Wachi 2 |
Wachi 0 | Kuti udarike chero rejista, shandura wachi yekunyoresa kuenda Hapana.
Shandura wachi yekunyoresa ku: • Wachi 0 kushandisa clk[0] chiratidzo sewachi sosi • Wachi 1 kushandisa clk[1] chiratidzo sewachi sosi • Wachi 2 kushandisa clk[2] chiratidzo sewachi sosi Unogona chete kushandura marongero aya kana wasarudza Register Inobvumira in View parameter. |
Mufananidzo 1. DSP Block View
Tafura 2. DSP Templates
| DSP Matemplate | Tsanangudzo |
| Wanza | Inoita kamwechete kunyatso wedzera oparesheni uye inoshandisa inotevera equation:
• Kunze = Ay * Az |
| Wedzera | Inoita imwechete chaiyo yekuwedzera kana kubvisa uye inoshandisa anotevera equation:.
• Kunze = Ay + Demo • Kunze = Ay – Demo |
| Wanza Wedzera | Iyi modhi inoita kuwedzeredza kumwechete, ichiteverwa nekuwedzera kana kubvisa uye inoshandisa equation inotevera.
• Kunze = (Ay * Az) - chainin • Kunze = (Ay * Az) + chainin • Kunze = (Ay * Az) – Demo • Kunze = (Ay * Az) + Demo |
| Wanza Uunganidze | Inoita inoyangarara-poindi yekuwedzera ichiteverwa neinoyangarara-poindi yekuwedzera kana kubvisa neyakare mhedzisiro yekuwedzera uye inoshandisa anotevera equations:
• Kunze (t) = [Ay(t) * Az(t)] – Kunze (t-1) painoungana chiratidzo chinofambiswa kumusoro. • Kunze (t) = [Ay(t) * Az(t)] + Kunze (t-1) apo chiteshi chengarava chinofambiswa kumusoro. • Kunze (t) = Ay(t) * Az(t) kana chiteshi chengarava chadzikiswa. |
| Vector Mode 1 | Inoita inoyangarara-poindi yekuwedzera ichiteverwa neinoyangarara-poindi yekuwedzera kana kubvisa nechainin yekupinda kubva kune yakapfuura vhezheni DSP block uye inoshandisa anotevera equations:. |
| akaenderera… | |
| DSP Matemplate | Tsanangudzo |
| • Kunze = (Ay * Az) - chainin
• Kunze = (Ay * Az) + chainin • Kunze = (Ay * Az) , chainout = Demo |
|
| Vector Mode 2 | Inoita inoyangarara-poindi yekuwedzera apo iyo IP musimboti inodyisa mhedzisiro yekuwedzera yakananga kune chainout. Iyo IP musimboti wobva wawedzera kana kubvisa iyo ketani yekupinza kubva kune yapfuura dhizaini DSP block kubva pakuisa Ax semhedzisiro.
Iyi modhi inoshandisa zvinotevera equations: • Kunze = Demo – chainin , chainout = Ay * Az • Kunze = Demo + chainin , chainout = Ay * Az • Kunze = Demo , chainout = Ay * Az |
Intel Cyclone 10 GX Native Inoyangarara-Point DSP Intel FPGA IP Zviratidzo
Mufananidzo 2. Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Signals
Iyo nhamba inoratidza yekupinda uye yekubuda masaini eiyo IP musimboti.
Tafura 3. Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Input Signals
| Zita rechiratidzo | Type | Upamhi | Default | Tsanangudzo |
| demo[31:0] | Input | 32 | Low | Isa data bhasi kune yawandisa. Inowanikwa mu:
• Wedzera maitiro • Kuwanza-Wedzera modhi pasina chainin uye chainout chimiro • Vector Mode 1 • Vector Mode 2 |
| Ay[31:0] | Input | 32 | Low | Isa data bhasi kune yawandisa.
Inowanikwa mune ese anoyangarara-poinzi maitiro ekushandisa. |
| az[31:0] | Input | 32 | Low | Isa data bhasi kune yawandisa. Inowanikwa mu:
• Wanza • Wanza Wedzera • Wanza Uunganidze • Vector Mode 1 • Vector Mode 2 |
| cheni[31:0] | Input | 32 | Low | Batanidza aya masaini kune masaini masaini kubva kune yakapfuura inoyangarara-poinzi DSP IP musimboti. |
| cl[2:0] | Input | 3 | Low | Isa masaini ewachi pamarejista ese.
Aya masaini ewachi anongowanikwa chete kana chero regiyo rekuisa, marejista epombi, kana regita rekubuda rakaiswa Wachi0 or Wachi1 or Wachi2. |
| ena[2:0] | Input | 3 | High | Wachi inogonesa clk[2:0]. Aya masaini ari kushanda-Pamusoro.
• ena[0] ndeye Wachi0 • ena[1] ndeye Wachi1 • ena[2] ndeye Wachi2 |
| aclr[1:0] | Input | 2 | Low | Asynchronous yakajeka yekupinza masaini kune ese marejista. Aya masaini ari kushanda-pamusoro.
Shandisa aclr[0] kune ese marejista ekuisa uye kushandiswa aclr[1] kune ese mapaipi uye marejista ekubuda. |
| kuunganidza | Input | 1 | Low | Input chiratidzo kugonesa kana kudzima iyo accumulator chimiro.
• Rongedza chiratidzo ichi kuitira kuti mhinduro ibude neadder. • De-assert iyi chiratidzo kuti uvhare maitiro emhinduro. Iwe unogona kutaura kana kurega-kusimbisa chiratidzo ichi panguva yekumhanya-nguva. Inowanikwa muKuwanza Kuunganidza modhi. |
| ketani[31:0] | Output | 32 | — | Batanidza masaini aya kune masaini masaini einotevera inoyangarara-poindi DSP IP musimboti. |
| mhedzisiro[31:0] | Output | 32 | — | Kuburitsa data bhazi kubva kuIP musimboti. |
Document Revision History
Shanduko kuIntel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP User Guide.
| Date | Version | Kuchinja |
| Mbudzi 2017 | 2017.11.06 | Kusunungurwa kwekutanga. |
Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.
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