intel Cyclone 10 Native FloatingPoint DSP FPGA IP

Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Tus Neeg Siv Qhia

Parameterizing Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP

Xaiv qhov sib txawv los tsim ib qho IP core haum rau koj tus qauv tsim.

1. Hauv Intel® Quartus® Prime Pro Edition, tsim ib txoj haujlwm tshiab uas tsom rau Intel Cyclone® 10 GX ntaus ntawv.
2. Hauv IP Catalog, nyem rau ntawm Lub Tsev Qiv Ntawv ➤ DSP ➤ Primitive DSP ➤ Intel Cyclone 10 GX Native Floating Point DSP.
   Intel Cyclone 10 GX Native Floating-Point DSP IP Core IP parameter editor qhib.
3. Hauv New IP Variation dialog box, nkag mus rau Lub Npe Lub Npe thiab nyem OK.
4. Hauv qab Parameters, xaiv DSP Template thiab cov View koj xav tau rau koj tus IP core
5. Hauv DSP Block View, toggle lub moos lossis rov pib dua ntawm txhua daim ntawv teev npe siv tau.
6. Rau Ntau Ntxiv lossis Vector Hom 1, nyem rau ntawm Chain In multiplexer hauv GUI xaiv cov tswv yim los ntawm chainin chaw nres nkoj lossis Ax chaw nres nkoj.
7. Nyem lub cim Adder hauv GUI los xaiv qhov sib ntxiv lossis rho tawm.
8. Nyem rau ntawm Chain Out multiplexer hauv GUI kom pab txhawb cov chaw nres nkoj.
9. Nyem Tsim HDL.
10. Nyem Ua kom tiav.

Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Parameters
Rooj 1. Parameters

Parameter	Tus nqi	Default tus nqi	Kev piav qhia
DSP Template	Ntau Ntxiv Multiply Add Multiply Accumulate Vector Hom 1 Vector hom 2	Ntau	Xaiv hom kev ua haujlwm xav tau rau DSP thaiv. Qhov kev xaiv ua haujlwm tau cuam tshuam hauv qhov DSP Block View.
View	Register Enables Register Clears	Sau npe Enables	Cov kev xaiv los xaiv clocking scheme los yog pib dua txheej txheem rau npe view. Qhov kev xaiv ua haujlwm tau cuam tshuam hauv qhov DSP Block View.
txuas ntxiv…

Parameter	Tus nqi	Default tus nqi	Kev piav qhia
			Xaiv Sau npe Enables rau DSP Block View los qhia cov ntawv sau npe clocking scheme. Koj tuaj yeem hloov cov moos rau txhua qhov kev sau npe hauv qhov no view. Xaiv Sau npe Clears rau DSP Block View kom pom cov ntawv sau npe pib dua txheej txheem. Qhib Siv Ib Leeg Clear hloov cov registers reset scheme.
Siv Ib Leeg Clear	Tawm los yog tawm	Tawm	Tig rau qhov ntsuas no yog tias koj xav tau ib zaug rov pib dua tag nrho cov npe hauv DSP thaiv. Tua qhov parameter no los siv cov chaw nres nkoj sib txawv los rov pib dua cov npe. Tig rau kom meej 0 ntawm cov ntawv tso zis tso zis; tua kom meej 1 ntawm cov ntawv tso zis. Ntshiab 0 rau cov ntawv sau npe siv aclr[0] teeb liab. Ntshiab 1 siv rau cov zis thiab cov raj xa dej sau npe siv aclr[1] signal. Tag nrho cov input registers siv aclr[0] reset signal. Tag nrho cov zis thiab cov raj xa dej tso npe siv aclr[1] pib dua teeb liab.
DSP View Thaiv.
Chain In Multiplexer (14)	Pab kom Disable	Disable	Nyem rau ntawm lub multiplexer kom pab chainin chaw nres nkoj.
Chain Out Multiplexer (12)	Lov tes Enable	Disable	Nyem rau ntawm lub multiplexer kom pab tau chainout chaw nres nkoj.
Adder (13)	+ –	+	Nyem rau ntawm qhov Adder cim xaiv hom ntxiv lossis rho tawm.
Sau npe moos • ax_clock (2) • ay_clock (3) • az_clock (4) • mult_pipeline_cloc k(5) • ax_chainin_pl_cloc k (7) • adder_input_clock (9) • adder_input_2_clo ck (10) • output_clock (11) • accumulate_clock (1) • accum_pipeline_cl ock (6) • accum_adder_cloc k (8)	Tsis muaj Lub moos 0 Lub moos 1 Lub moos 2	Lub moos 0	Txhawm rau hla kev sau npe, toggle lub teev teev npe rau Tsis muaj. Toggle lub teev teev npe rau: •    Lub moos 0 siv clk[0] teeb liab ua lub moos qhov chaw •    Lub moos 1 siv clk[1] teeb liab ua lub moos qhov chaw •    Lub moos 2 siv clk[2] teeb liab ua lub moos qhov chaw Koj tsuas tuaj yeem hloov cov chaw no thaum koj xaiv Sau npe Enables in View parameter.

Daim duab 1. DSP Thaiv View

Table 2. DSP Templates

DSP Templates	Kev piav qhia
Ntau	Ua ib qho kev sib tw ua haujlwm sib npaug thiab siv cov kab zauv hauv qab no: • Out = Ay* Az
Ntxiv	Ua ib qho kev sib ntxiv lossis kev rho tawm thiab siv cov kev sib npaug hauv qab no: . • Tawm = Ay + Ax • Tawm = Ay – Ax
Ntxiv Ntxiv	Hom no ua ib qho kev sib npaug ntawm qhov sib npaug, ua raws li kev sib ntxiv lossis rho tawm thiab siv cov kev sib npaug hauv qab no. • Tawm = (Ay * Az) – chainin • Out = (Ay * Az) + chainin • Tawm = (Ay * Az) – Ax • Tawm = (Ay * Az) + Ax
Sib Nqus	Ua floating-point multiplication ua raws li floating-point ntxiv lossis rho nrog cov txiaj ntsig yav dhau los thiab siv cov kev sib npaug hauv qab no: • Out(t) = [Ay(t) * Az(t)] – Out (t-1) thaum accumulate teeb liab yog tsav siab. • Tawm(t) = [Ay(t) * Az(t)] + Tawm (t-1) thaum cov chaw nres nkoj loj tau tsav siab. • Out(t) = Ay(t) * Az(t) thaum cov chaw nres nkoj loj tau tsav qis.
Vector hom 1	Ua raws li qhov sib npaug ntawm qhov sib npaug ua raws li qhov sib ntxiv los yog kev rho tawm nrog cov kev tawm tswv yim los ntawm qhov sib txawv ntawm DSP yav dhau los thiab siv cov kev sib npaug hauv qab no: .
txuas ntxiv…

DSP Templates	Kev piav qhia
	• Tawm = (Ay * Az) – chainin • Out = (Ay * Az) + chainin • Out = (Ay * Az), chainout = Ax
Vector hom 2	Ua qhov sib npaug ntawm qhov chaw uas tus IP core pub cov txiaj ntsig sib npaug ncaj qha mus rau chainout. Cov tub ntxhais IP tom qab ntawd ntxiv lossis rho tawm cov kev tawm tswv yim chainin los ntawm qhov sib txawv dhau los DSP thaiv los ntawm cov tswv yim Ax raws li cov txiaj ntsig tau txais. Hom no siv cov kev sib npaug hauv qab no: • Tawm = Ax – chainin , chainout = Ay * Az • Tawm = Ax + chainin , chainout = Ay * Az • Out = Ax , chainout = Ay * Az

Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Signals

Daim duab 2. Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Signals
Daim duab qhia tau hais tias cov tswv yim thiab tso tawm cov cim ntawm IP core.

Table 3. Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Input Signals

Lub Npe Lub Npe	Hom	Dav	Default	Kev piav qhia
loj [31:0]	Tswv yim	32	Tsawg	Input data bus mus rau tus multiplier. Muaj nyob rau hauv: • Ntxiv hom • Ntau-Ntxiv hom yam tsis muaj chainin thiab chainout feature • Vector hom 1 • Vector hom 2
yog [31:0]	Tswv yim	32	Tsawg	Input data bus mus rau tus multiplier. Muaj nyob rau hauv tag nrho cov floating-point ua hauj lwm hom.
ib [31:0]	Tswv yim	32	Tsawg	Input data bus mus rau tus multiplier. Muaj nyob rau hauv: • Ntau • Ntau Ntxiv • Ua kom ntau ntxiv • Vector hom 1 • Vector hom 2
chainin [31:0]	Tswv yim	32	Tsawg	Txuas cov teeb liab no mus rau cov teeb liab chainout los ntawm qhov ua ntej floating-point DSP IP core.
qw [2:0]	Tswv yim	3	Tsawg	Input moos signals rau tag nrho cov npe. Cov cim moos no tsuas yog muaj yog tias ib qho ntawm cov ntawv sau npe nkag, cov ntawv sau npe, lossis cov ntawv tso tawm tso tawm raug teeb tsa rau Moos 0 or Moos 1 or Moos 2.
ib [2:0]	Tswv yim	3	Siab	Lub moos pab rau clk[2:0]. Cov teeb liab no yog active-High. • ena[0] yog rau Moos 0 • ena[1] yog rau Moos 1 • ena[2] yog rau Moos 2
aclr [1:0]	Tswv yim	2	Tsawg	Asynchronous clear input signals rau tag nrho cov npe. Cov teeb liab no yog active-siab. Siv aclr[0] rau tag nrho cov input sau npe thiab siv aclr[1] rau tag nrho cov raj xa dej thiab cov ntawv tso tawm.
sau	Tswv yim	1	Tsawg	Input teeb liab los pab los yog lov tes taw lub accumulator feature. • Qhia qhov teeb liab no kom pab tau cov lus teb tus adder cov zis. • Tsis lees paub qhov teeb liab no kom lov tes taw cov tswv yim tswv yim. Koj tuaj yeem lees paub lossis tshem tawm qhov teeb meem no thaum lub sijhawm ua haujlwm. Muaj nyob rau hauv Multiply Accumulate hom.
xov xwm tshiab [31:0]	Tso zis	32	—	Txuas cov teeb liab no mus rau chainin cov cim ntawm qhov txuas txuas txuas ntxiv DSP IP core.
Qhov tshwm sim [31:0]	Tso zis	32	—	Tawm cov ntaub ntawv tsheb npav los ntawm IP core.

Cov ntaub ntawv kho dua tshiab

Hloov rau Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Tus Neeg Siv Qhia

Hnub tim	Version	Hloov
Kaum Ib Hlis 2017	2017.11.06	Kev tso tawm thawj zaug.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Cov ntaub ntawv / Cov ntaub ntawv

intel Cyclone 10 Native FloatingPoint DSP FPGA IP [ua pdf] Cov neeg siv phau ntawv qhia Cyclone 10 Native FloatingPoint DSP FPGA IP, 10 Native FloatingPoint DSP FPGA IP, Native FloatingPoint DSP FPGA IP, FloatingPoint DSP FPGA IP, DSP FPGA IP, FPGA IP

Cov ntaub ntawv

• Cov neeg siv phau ntawv