intel Cyclone 10 Native FloatingPoint DSP FPGA IP

Intel® Cyclone® 10 GX Native Floating Point DSP Intel® FPGA IP alakaʻi hoʻohana

Hoʻohālikelike i ka Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP

E koho i nā ʻāpana like ʻole e hana i kahi kumu IP kūpono no kāu hoʻolālā.

1. I loko o Intel® Quartus® Prime Pro Edition, hana i kahi papahana hou e kuhikuhi ana i kahi mea hana Intel Cyclone® 10 GX.
2. Ma IP Catalog, kaomi ma ka Hale Waihona Puke ➤ DSP ➤ Primitive DSP ➤ Intel Cyclone 10 GX Native Floating Point DSP.
   Wehe ka Intel Cyclone 10 GX Native Floating-Point DSP IP Core IP parameter hoʻoponopono.
3. I ka New IP Variation dialog box, e hookomo i ka Entity Name a kaomi OK.
4. Ma lalo o nā ʻāpana, koho i ka Template DSP a me ka View makemake ʻoe no kāu kumu IP
5. Ma ka DSP Block View, hoʻololi i ka uaki a i ʻole ka hoʻonohonoho hou ʻana o kēlā me kēia papa inoa kūpono.
6. No ka Multiply Add or Vector Mode 1, e kaomi i ka Chain In multiplexer ma ka GUI e koho i ka hookomo mai ke awa chainin a i ke awa Ax.
7. Kaomi i ka hōʻailona Adder ma ka GUI e koho i ka hoʻohui a i ʻole ka unuhi.
8. Kaomi ma ka Chain Out multiplexer ma ka GUI e hiki ai i ke awa chainout.
9. Kaomi i ka Generate HDL.
10. Kaomi Hoʻopau.

Intel Cyclone 10 GX Native Floating Point DSP Intel FPGA IP Parameters
Papa 1. Nā ʻāpana

ʻĀpana	Waiwai	Waiwai Paʻamau	wehewehe
Kāleka DSP	E hoonui Hoʻohui Hoʻonui i ka hoʻonui ʻana i ke ʻano Vector 1 ʻAno Vector 2	E hoonui	E koho i ke ʻano hana i makemake ʻia no ka poloka DSP. Hōʻike ʻia ka hana i koho ʻia ma ka Paʻa DSP View.
View	Hoʻopaʻa inoa i hiki ke hoʻopaʻa inoa	Hiki ke kakau inoa	Nā koho no ke koho ʻana i ka hoʻolālā hola a i ʻole ka hoʻonohonoho hou ʻana i ka papahana no nā papa inoa view. Hōʻike ʻia ka hana i koho ʻia ma ka Paʻa DSP View.
hoʻomau…

ʻĀpana	Waiwai	Waiwai Paʻamau	wehewehe
			E koho Hiki ke kakau inoa no ka mea Paʻa DSP View e hōʻike i ka hoʻopaʻa ʻana i ka hoʻolālā manawa. Hiki iā ʻoe ke hoʻololi i nā wati no kēlā me kēia papa inoa ma kēia view. E koho Hoʻopaʻa inoa no ka mea Paʻa DSP View e hōʻike i nā papa inoa hoʻonohonoho hou. Hōʻā E hoʻohana i Single Clear e hoʻololi i ka papa hana hoʻopaʻa inoa.
E hoʻohana i Single Clear	Pau a i ʻole	Paʻa	E hoʻohuli i kēia ʻāpana inā makemake ʻoe i hoʻokahi hoʻonohonoho hou e hoʻihoʻi i nā papa inoa āpau i ka poloka DSP. E hoʻopau i kēia ʻāpana no ka hoʻohana ʻana i nā awa hoʻihoʻi hou e hoʻihoʻi i nā papa inoa. E ho'ā no ka 0 akaka ma ka papa inoa puka; e pio no ka maopopo 1 ma ka papa inoa puka. ʻĀina 0 no nā papa inoa hoʻokomo e hoʻohana i ka aclr[0] hōʻailona. ʻĀina 1 no ka hoʻohana ʻana i nā hoʻopaʻa inoa puka a me nā paipu aclr[1] hōʻailona. Hoʻohana nā papa inoa hoʻokomo a pau i ka hōʻailona hōʻailona aclr[0]. Hoʻohana nā mea hoʻopaʻa inoa a pau a me nā pipeline aclr [1] reset signal.
DSP View Palaka.
Kahaohao ma ka Multiplexer (14)	Hiki iā hoʻopio	Hoʻopau	Kaomi ma ka multiplexer e hiki ai i ka chainin awa.
Hoʻokaʻawale i nā kaulahao (12)	Hoʻopio hiki ʻole	Hoʻopau	Kaomi ma ka multiplexer e hiki ai i ka chainout awa.
Mea hoʻohui (13)	+ –	+	Kaomi ma ka Pākuʻi hōʻailona e koho i ke ʻano hoʻohui a i ʻole ka unuhi ʻana.
Kakau Kakau • ax_clock (2) • ay_clock (3) • az_clock (4) • nui_pipeline_clock k(5) • ax_chainin_pl_cloc k (7) • hoʻokomo_kauka_hoʻokomo (9) • mea hoʻokomo_2_clo ck (10) • puka_uaki (11) • accumulate_clock (1) • accum_pipeline_cl ock (6) • accum_adder_cloc k (8)	ʻAʻohe Uaki 0 Uaki 1 Uaki 2	Uaki 0	No ke kāʻalo ʻana i kekahi papa inoa, e hoʻololi i ka uaki kakau i ʻAʻohe. E hoʻololi i ka uaki kakau i: •    Uaki 0 e hoʻohana i ka hōʻailona clk[0] ma ke ʻano he kumu uaki •    Uaki 1 e hoʻohana i ka hōʻailona clk[1] ma ke ʻano he kumu uaki •    Uaki 2 e hoʻohana i ka hōʻailona clk[2] ma ke ʻano he kumu uaki Hiki iā ʻoe ke hoʻololi i kēia mau hoʻonohonoho ke koho ʻoe Hiki ke kakau inoa in View ʻāpana.

Kiʻi 1. DSP Block View

Papa 2. DSP Templates

Nā Papahana DSP	wehewehe
E hoonui	Hana i ka hana hoonui pono hookahi a pili i ka hoohalike penei: • Iwaho = Ay * Az
Hoʻohui	Hana i ka hoʻohui a i ʻole ka unuhi pono ʻana i ka hana a hoʻopili i kēia mau hoohalike:. • Iwaho = Ay + Ax • Iwaho = Ay – Ax
Hoonui Hoonui	Hana kēia ʻano hana i ka hoʻonui pololei hoʻokahi, a ukali ʻia e nā hana hoʻohui a i ʻole ka unuhi ʻana a pili i nā hoohalike. • Out = (Ay * Az) – chainin • Out = (Ay * Az) + chainin • Out = (Ay * Az) – Ax • Out = (Ay * Az) + Ax
E hoonui i ka hoahu	Hana ʻia ka hoʻonui kiko lana a me ka hoʻohui ʻana a i ʻole ka unuhi ʻana me ka hopena o ka hoʻonui mua ʻana a hoʻopili i kēia mau hoohalike: • Out(t) = [Ay(t) * Az(t)] – Out (t-1) ke hōʻiliʻili ua hoʻokiʻekiʻe ʻia ka hōʻailona. • Out(t) = [Ay(t) * Az(t)] + Out (t-1) ke kiʻekiʻe ʻia ke awa hōʻiliʻili. • Iwaho(t) = Ay(t) * Az(t) ke ho'ohiolo ha'aha'a ka awa hō'ili'ili.
ʻAno Vector 1	Hana ʻia ka hoʻonui kiko lana ma hope o ka hoʻohui ʻana a i ʻole ka unuhi ʻana me ka hoʻokomo kaulahao mai ka poloka DSP hoʻololi mua a pili i nā hoohalike penei:.
hoʻomau…

Nā Papahana DSP	wehewehe
	• Out = (Ay * Az) – chainin • Out = (Ay * Az) + chainin • Out = (Ay * Az) , chainout = Ax
ʻAno Vector 2	Hana i ka hoʻonui kiko lana kahi e hānai pono ai ka IP core i ka hopena hoʻonui i ka chainout. Hoʻohui a unuhi paha ka IP core i ka hoʻokomo chainin mai ka poloka DSP hoʻololi mua mai ka hoʻokomo Ax ma ke ʻano he hopena. Hoʻohana kēia ʻano i nā hoohalike penei: • Ma waho = Ax – chainin , chainout = Ay * Az • Ma waho = Ax + chainin , kaulahao puka = ​​Ay * Az • Out = Ax , chainout = Ay * Az

Intel Cyclone 10 GX Native Floating Point DSP Intel FPGA IP hōʻailona

Kiʻi 2. Intel Cyclone 10 GX Native Floating Point DSP Intel FPGA IP hōʻailona
Hōʻike ke kiʻi i nā hōʻailona hoʻokomo a me nā hōʻailona o ka IP core.

Papa 3. Intel Cyclone 10 GX Native Floating Point DSP Intel FPGA IP Input Signals

inoa hōʻailona	ʻAno	Laulā	Paʻamau	wehewehe
koi[31:0]	Hookomo	32	Haʻahaʻa	E hoʻokomo i ka pahi ʻikepili i ka multiplier. Loaʻa ma: • Hoʻohui i ke ʻano • Multiply-Hoʻohui i ke ʻano me ka hiʻohiʻona ʻole o ka chainin a me ka chainout • Ke ano Vector 1 • Ke ano Vector 2
a[31:0]	Hookomo	32	Haʻahaʻa	E hoʻokomo i ka pahi ʻikepili i ka multiplier. Loaʻa i nā ʻano hana hana floating-point.
a[31:0]	Hookomo	32	Haʻahaʻa	E hoʻokomo i ka pahi ʻikepili i ka multiplier. Loaʻa ma: • Hoonui • Hoonui Hoonui • Hoʻonui Hoʻonui • Ke ano Vector 1 • Ke ano Vector 2
kaulahao[31:0]	Hookomo	32	Haʻahaʻa	E hoʻohui i kēia mau hōʻailona i nā hōʻailona kaulahao mai ke kiko lana DSP IP ma mua.
clk[2:0]	Hookomo	3	Haʻahaʻa	Hoʻokomo i nā hōʻailona uaki no nā papa inoa a pau. Loaʻa kēia mau hōʻailona uaki inā hoʻonohonoho ʻia kekahi o nā papa inoa hoʻokomo, nā papa inoa pipeline, a i ʻole ka papa inoa puka Uaki0 or Uaki1 or Uaki2.
ʻena[2:0]	Hookomo	3	Kiʻekiʻe	Hiki i ka uaki no clk[2:0]. Hoʻoikaika kēia mau hōʻailona-Kiʻekiʻe. • ena[0] no Uaki0 • ena[1] no Uaki1 • ena[2] no Uaki2
aclr[1:0]	Hookomo	2	Haʻahaʻa	Nā hōʻailona hoʻokomo asynchronous no nā papa inoa a pau. ʻO kēia mau hōʻailona he ikaika-kiʻekiʻe. Hoʻohana aclr[0] no nā papa inoa komo a pau aclr[1] no nā papa inoa paipu a pau.
hōʻiliʻili	Hookomo	1	Haʻahaʻa	Hoʻokomo i ka hōʻailona e hiki ai a hoʻopau paha i ka hiʻona accumulator. • E hōʻoia i kēia hōʻailona e hiki ai i ka manaʻo hoʻopuka i ka mea hoʻohui. • Hoʻopau i kēia hōʻailona no ka hoʻopau ʻana i ka mīkini manaʻo. Hiki iā ʻoe ke hōʻoia a hoʻopau paha i kēia hōʻailona i ka wā holo. Loaʻa ma ke ʻano Multiply Accumulate.
kaulahao[31:0]	Hoʻopuka	32	—	E hoʻohui i kēia mau hōʻailona i nā hōʻailona chainin o ke kiko lana DSP IP aʻe.
hopena[31:0]	Hoʻopuka	32	—	Kaʻa ʻikepili puka mai IP core.

Moolelo Hooponopono Palapala

Hoʻololi i ka Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP alakaʻi hoʻohana.

Lā	Manao	Nā hoʻololi
Nowemapa 2017	2017.11.06	Hoʻokuʻu mua.

Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā ​​​​lawelawe. * Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.

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