Intel Cyclone 10 Native FloatingPoint DSP FPGA IP
Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide
Parameterizing Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP
Sankhani magawo osiyanasiyana kuti mupange IP core yoyenera kapangidwe kanu.
- Mu Intel® Quartus® Prime Pro Edition, pangani pulojekiti yatsopano yomwe imayang'ana chipangizo cha Intel Cyclone® 10 GX.
- Mu IP Catalogue, dinani pa Library ➤ DSP ➤ Primitive DSP ➤ Intel Cyclone 10 GX Native Floating Point DSP.
Intel Cyclone 10 GX Native Floating-Point DSP IP Core IP parameter editor imatsegula. - Mu bokosi Latsopano la IP Variation, lowetsani Dzina la Entity ndikudina OK.
- Pansi pa Parameters, sankhani DSP Template ndi View mukufuna pa IP core
- Mu DSP Block View, sinthani wotchi kapena kukonzanso kaundula aliyense wovomerezeka.
- Kuti Muchulukitse Onjezani kapena Vector Mode 1, dinani Chain In multiplexer mu GUI kuti musankhe zolowetsa kuchokera ku doko la chainin kapena doko la Ax.
- Dinani chizindikiro cha Adder mu GUI kuti musankhe kuwonjezera kapena kuchotsa.
- Dinani pa Chain Out multiplexer mu GUI kuti mutsegule doko la chainout.
- Dinani Pangani HDL.
- Dinani Malizani.
Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Parameters
Table 1. Parameters
| Parameter | Mtengo | Mtengo Wofikira | Kufotokozera |
| Chithunzi cha DSP | Chulutsani Onjezani
Chulutsani Onjezani Kuchulukirachulukira Mayendedwe a Vector 1 Njira ya Vector 2 |
Chulutsani | Sankhani mawonekedwe ogwirira ntchito omwe mukufuna pa block ya DSP.
Ntchito yosankhidwa ikuwonetsedwa mu Chithunzi cha DSP Block View. |
| View | Kulembetsa Kumathandiza Kuchotsa kwa Register | Register Imayatsa | Zosankha kusankha clocking scheme kapena reset scheme kwa registry view. Ntchito yosankhidwa ikuwonetsedwa mu Chithunzi cha DSP Block View. |
| anapitiriza… | |||
| Parameter | Mtengo | Mtengo Wofikira | Kufotokozera |
| Sankhani Register Imayatsa za Chithunzi cha DSP Block View kuwonetsa registry clocking scheme. Mutha kusintha mawotchi a zolembetsa zilizonse mu izi view.
Sankhani Register Clears za Chithunzi cha DSP Block View kuwonetsa registry reset scheme. Yatsani Gwiritsani Ntchito Single Clear kusintha registry reset scheme. |
|||
| Gwiritsani Ntchito Single Clear | Kutsegula kapena kutseka | Kuzimitsa | Yatsani parameter iyi ngati mukufuna kukonzanso kamodzi kuti mukonzenso zolembetsa zonse mu block ya DSP. Zimitsani parameter iyi kuti mugwiritse ntchito madoko osiyanasiyana kuti mukonzenso zolembetsa.
Yatsani kuti muwonetsetse 0 pa registry yotulutsa; zimitsani kuti muwone 1 pa registry yotulutsa. Pafupi 0 pa zolembera zolowetsa amagwiritsa aclr[0] chizindikiro. Pafupi 1 kwa zotulutsa ndi kaundula wa mapaipi chizindikiro cha aclr[1]. Zolembera zonse zolembera zimagwiritsa ntchito chizindikiro cha aclr[0] chokhazikitsanso. Zolemba zonse zotulutsa ndi mapaipi zimagwiritsa ntchito chizindikiro cha aclr[1] chokhazikitsanso. |
| DSP View Block. | |||
| Chain In Multiplexer (14) | Thandizani Letsani | Letsani | Dinani pa multiplexer kuti mutsegule chainin
doko. |
| Chain Out Multiplexer (12) | Thandizani Yambitsani | Letsani | Dinani pa multiplexer kuti mutsegule chainout
doko. |
| Mdani (13) | +
– |
+ | Dinani pa Adder chizindikiro kusankha kuwonjezera kapena kuchotsa. |
| Register Clock
• ax_clock (2) • ay_clock (3) • az_clock (4) • mult_pipeline_cloc k(5) • ax_chainin_pl_cloc k (7) • adder_input_clock (9) • adder_input_2_clock ck (10) • output_clock (11) • accumulate_clock (1) • accum_pipeline_cl ock (6) • accum_adder_cloc k (8) |
Palibe Koloko 0
Koloko 1 Koloko 2 |
Koloko 0 | Kuti mulambalale kaundula aliyense, sinthani wotchi yolembetsa kukhala Palibe.
Sinthani wotchi yolembetsa kukhala: • Koloko 0 kugwiritsa ntchito clk[0] chizindikiro ngati gwero la wotchi • Koloko 1 kugwiritsa ntchito clk[1] chizindikiro ngati gwero la wotchi • Koloko 2 kugwiritsa ntchito clk[2] chizindikiro ngati gwero la wotchi Mutha kusintha izi mukasankha Register Imayatsa in View parameter. |
Chithunzi 1. DSP Block View
Table 2. DSP Templates
| Zithunzi za DSP | Kufotokozera |
| Chulutsani | Imagwira ntchito yochulutsa mwatsatanetsatane ndipo imagwiritsa ntchito equation iyi:
• Kutuluka = Ayi * Az |
| Onjezani | Imagwira ntchito yongowonjezera kapena kuchotsa ndipo imagwiritsa ntchito ma equation awa:.
• Kutuluka = Ay + Nkhwangwa • Kutuluka = Ayi – Nkhwangwa |
| Chulukitsani Onjezani | Mchitidwewu umachita kuchulutsa kumodzi, kutsatiridwa ndi kuwonjezera kapena kuchotsa ndikugwiritsa ntchito ma equation otsatirawa.
• Kutuluka = (Ay * Az) - chainin • Kutuluka = (Ay * Az) + chainin • Kutuluka = (Ay * Az) – Nkhwangwa • Kunja = (Ay * Az) + Nkhwangwa |
| Chulukitsani Wunjikani | Imachulutsa-malo oyandama motsatiridwa ndi kuwonjezera kapena kuchotsera malo oyandama ndi zotsatira zochulutsa zam'mbuyomo ndikugwiritsanso ntchito zotsatirazi:
• Out(t) = [Ay(t) * Az(t)] – Out (t-1) ikachuluka chizindikiro chimayendetsedwa pamwamba. • Kutuluka (t) = [Ay(t) * Az(t)] + Kutuluka (t-1) pamene doko lodziunjikira limayendetsedwa kwambiri. • Kutuluka (t) = Ay(t) * Az(t) pamene doko lodziunjikira limayendetsedwa pansi. |
| Njira ya Vector 1 | Imachulutsa mfundo zoyandama motsatiridwa ndi kuwonjezera-malo oyandama kapena kuchotsa ndi cholowa cha unyolo kuchokera ku block ya DSP yosinthika yapitayi ndipo imagwiritsa ntchito ma equation awa:. |
| anapitiriza… | |
| Zithunzi za DSP | Kufotokozera |
| • Kutuluka = (Ay * Az) - chainin
• Kutuluka = (Ay * Az) + chainin • Kutuluka = (Ay * Az) , chainout = Nkhwangwa |
|
| Njira ya Vector 2 | Imachulutsa-malo oyandama pomwe IP core imadyetsa zotsatira zochulutsa mwachindunji ndi chainout. IP pachimake ndiye imawonjezera kapena kuchotsera cholowetsa chachainin kuchokera ku block ya DSP yosinthika kuchokera pakulowetsa Ax monga zotsatira zake.
Njira iyi imagwiritsa ntchito ma equation awa: • Kutuluka = Nkhwangwa – unyolo , chainout = Ay * Az • Kutuluka = Nkhwangwa + chainin , chainout = Ay * Az • Kutuluka = Nkhwangwa , unyolo = Ay * Az |
Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Signals
Chithunzi 2. Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Signals
Chithunzichi chikuwonetsa zolowetsa ndi zotuluka za IP core.
Table 3. Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP Input Signals
| Dzina la Signal | Mtundu | M'lifupi | Zosasintha | Kufotokozera |
| nkhwangwa[31:0] | Zolowetsa | 32 | Zochepa | Lowetsani basi ya data kupita ku chochulukitsa. Ikupezeka mu:
• Add mode • Kuchulukitsa-Onjezani mawonekedwe opanda unyolo ndi mawonekedwe a chainout • Njira ya Vector 1 • Njira ya Vector 2 |
| ayi[31:0] | Zolowetsa | 32 | Zochepa | Lowetsani basi ya data ku chochulukitsa.
Imapezeka m'njira zonse zoyandama zoyandama. |
| [31:0] | Zolowetsa | 32 | Zochepa | Lowetsani basi ya data kupita ku chochulukitsa. Ikupezeka mu:
• Chulukitsani • Chulukitsani Onjezani • Chulutsa Bwino • Njira ya Vector 1 • Njira ya Vector 2 |
| unyolo [31:0] | Zolowetsa | 32 | Zochepa | Lumikizani ma siginecha awa ku ma siginecha a unyolo kuchokera pachimake choyandama cha DSP IP. |
| gulu [2:0] | Zolowetsa | 3 | Zochepa | Lowetsani chizindikiro cha wotchi pamarejista onse.
Zizindikiro za wotchizi zimapezeka pokhapokha ngati zolembera zilizonse, zolembera zamapaipi, kapena zolembera zotulutsa zakhazikitsidwa Koloko0 or Koloko1 or Koloko2. |
| ena[2:0] | Zolowetsa | 3 | Wapamwamba | Wotchi imathandizira clk[2:0]. Zizindikiro izi ndi yogwira-Pamwamba.
• ena[0] ndi ya Koloko0 • ena[1] ndi ya Koloko1 • ena[2] ndi ya Koloko2 |
| aclr[1:0] | Zolowetsa | 2 | Zochepa | Asynchronous zomveka bwino zolembera zolembera zonse. Zizindikiro izi ndi yogwira-mmwamba.
Gwiritsani ntchito aclr[0] pa zolembera zonse zolowetsa ndikugwiritsa ntchito aclr[1] kwa zolembera zonse za mapaipi ndi zotulutsa. |
| sonkhanitsa | Zolowetsa | 1 | Zochepa | Lowetsani chizindikiro kuti mutsegule kapena kuletsa mawonekedwe a accumulator.
• Yang'anirani chizindikiro ichi kuti muthandizire kutulutsa kwa adder. • Onetsani chizindikiro ichi kuti muyimitse njira yobwezera. Mutha kunena kapena kuletsa chizindikiro ichi panthawi yothamanga. Ikupezeka mu Multiply Accumulate mode. |
| unyolo [31:0] | Zotulutsa | 32 | — | Lumikizani ma siginecha awa ku ma signinin amtundu wotsatira wa DSP IP pachimake. |
| zotsatira [31:0] | Zotulutsa | 32 | — | Mabasi otuluka kuchokera ku IP core. |
Document Revision History
Zosintha ku Intel Cyclone 10 GX Native Floating-Point DSP Intel FPGA IP User Guide
| Tsiku | Baibulo | Zosintha |
| Novembala 2017 | 2017.11.06 | Kutulutsidwa koyamba. |
Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.
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