FPGA IP
Apẹrẹ Example User Itọsọna
F-Tile 25G àjọlò Intel®
Imudojuiwọn fun Intel® Quartus®
NOMBA Design Suite: 22.3
Ẹya IP: 1.0.0

Quick Bẹrẹ Itọsọna

F-tile 25G Ethernet Intel FPGA IP fun awọn ẹrọ Intel Agilex™ pese agbara ti ipilẹṣẹ apẹrẹ examples fun awọn atunto ti a ti yan.
olusin 1. Design Example Lilo

Ilana Ilana

olusin 2. 25G àjọlò Intel FPGA IP Design Eksample Directory Be

• Simulation naa files (testbench fun kikopa nikan) wa ninuample_dir>/ apẹẹrẹample_testbench.
• Apẹrẹ akopọ-nikan example wa ni be niample_dir>/ compilation_test_design.
• Awọn hardware iṣeto ni ati igbeyewo files (apẹrẹ example ni hardware) ti wa ni be niample_dir>/hardware_test_design.

Table 1. Liana ati File Awọn apejuwe

File Awọn orukọ	Apejuwe
eth_ex_25g.qpf	Intel Quartus® NOMBA ise agbese file.
eth_ex_25g.qsf	Intel Quartus NOMBA eto ise agbese file.
eth_ex_25g.sdc	Synopsys Design inira file. O le daakọ ati tunṣe eyi file fun ara rẹ 25GbE Intel FPGA IP mojuto oniru.
eth_ex_25g.v	Oke-ipele Verilog HDL oniru example file. Apẹrẹ ikanni kan lo Verilog file.
wọpọ/	Hardware oniru example ṣe atilẹyin files.
hwtest/main.tcl	Akọkọ file fun wiwọle System Console.

Ti o npese awọn Design Example

Olusin 4. Example Design Tab ni F-tile 25G àjọlò Intel FPGA IP Parameter Olootu

Tẹle awọn igbesẹ wọnyi lati ṣe ina apẹrẹ hardware example ati testbench:

1. Ni Intel Quartus Prime Pro Edition, tẹ File ➤ Oluṣeto Iṣẹ Tuntun lati ṣẹda iṣẹ akanṣe Quartus Prime tuntun, tabi File ➤ Ṣii Project lati ṣii iṣẹ akanṣe Quartus Prime ti o wa tẹlẹ. Oluṣeto naa ta ọ lati pato ẹrọ kan.
2. Ninu Katalogi IP, wa ati yan 25G Ethernet Intel FPGA IP fun Agilex. Ferese Iyipada IP Tuntun yoo han.
3. Pato orukọ ipele oke kan fun iyatọ IP rẹ ki o tẹ O DARA. Olootu paramita ṣafikun ipele-oke .ip file si awọn ti isiyi ise agbese laifọwọyi. Ti o ba ti ṣetan lati fi .ip kun pẹlu ọwọ file si ise agbese na, tẹ Project ➤ Fikun-un / Yọ Files ni Project lati fi awọn file.
4. Ninu sọfitiwia Intel Quartus Prime Pro Edition, o gbọdọ yan ẹrọ Intel Agilex kan pato ni aaye Ẹrọ, tabi tọju ẹrọ aifọwọyi ti sọfitiwia sọfitiwia Quartus Prime ni imọran.
   Akiyesi: Apẹrẹ hardware example ìkọlélórí yiyan pẹlu awọn ẹrọ lori afojusun ọkọ. O pato awọn afojusun ọkọ lati awọn akojọ ti oniru example awọn aṣayan ninu awọn Example Design taabu.
5. Tẹ O DARA. Olootu paramita yoo han.
6. Lori IP taabu, pato awọn paramita fun iyatọ ipilẹ IP rẹ.
7. Lori Example Design taabu, fun Example Apẹrẹ Files, yan aṣayan Simulation lati ṣe ina testbench, ki o yan aṣayan Synthesis lati ṣe ipilẹṣẹ apẹrẹ ohun elo example. Nikan Verilog HDL files ti wa ni ipilẹṣẹ.
   Akiyesi: Kokoro IP VHDL ti n ṣiṣẹ ko si. Pato Verilog HDL nikan, fun apẹrẹ ipilẹ IP rẹ example.
8. Fun Apo Idagbasoke Àkọlé, yan Agilex I-jara Transceiver-SoC Dev Kit
9. Tẹ Ina Example Design bọtini. Awọn Yan Example Design Directory window han.
10. Ti o ba fẹ lati yi awọn oniru exampọna itọsọna tabi orukọ lati awọn aṣiṣe ti o han (alt_e25_f_0_example_design), lọ kiri si ọna tuntun ki o tẹ apẹrẹ tuntun example orukọ liana (ample_dir>).
11. Tẹ O DARA.

1.2.1. Oniru Example Parameters
Tabili 2. Awọn paramita ni Example Design Tab

Paramita	Apejuwe
Example Apẹrẹ	Wa example awọn aṣa fun IP paramita eto. Nikan nikan- ikanni example oniru ni atilẹyin fun yi IP.
Example Apẹrẹ Files	Awọn files lati se ina fun awọn ti o yatọ idagbasoke alakoso. • Simulation-n ṣe ipilẹṣẹ pataki files fun kikopa Mofiample apẹrẹ. • Synthesis-n ṣe ipilẹṣẹ files. Lo awọn wọnyi files lati ṣajọ apẹrẹ ni sọfitiwia Intel Quartus Prime Pro Edition fun idanwo ohun elo ati ṣe itupalẹ akoko aimi.
Ṣẹda File Ọna kika	Ọna kika RTL files fun kikopa-Verilog.
Yan Board	Ohun elo atilẹyin fun imuse apẹrẹ. Nigbati o ba yan igbimọ idagbasoke Intel FPGA kan, lo ẹrọ AGIB027R31B1E2VRO bi Ẹrọ Àkọlé fun apẹrẹ apẹẹrẹ.ample iran. Agilex I-jara Transceiver-SoC Dev Kit: Aṣayan yii ngbanilaaye lati ṣe idanwo apẹrẹ tẹlẹample lori ohun elo idagbasoke Intel FPGA IP ti a yan. Aṣayan yii laifọwọyi yan Ẹrọ Àkọlé ti AGIB027R31B1E2VRO. Ti o ba ti rẹ ọkọ àtúnyẹwò ni o ni kan ti o yatọ ẹrọ ite, o le yi awọn afojusun ẹrọ. Kò: Aṣayan yii yọkuro awọn aaye ohun elo fun apẹrẹ example.

1.3. Ti o npese Tile Files

Iran Atilẹyin-Logic jẹ igbesẹ iṣaju iṣaju ti a lo lati ṣe ipilẹṣẹ ti o ni ibatan tile files beere fun kikopa ati hardware oniru. Tile iran ti wa ni ti beere fun gbogbo
Awọn iṣeṣiro apẹrẹ ti o da lori F-tile. O gbọdọ pari igbesẹ yii ṣaaju kikopa naa.

1. Ni aṣẹ aṣẹ, lilö kiri si folda compilation_test_design ninu iṣaaju rẹample apẹrẹ: cd / akopo_test_design.
2. Ṣiṣe aṣẹ wọnyi: quartus_tlg alt_eth_25g

1.4. Simulating F-tile 25G àjọlò Intel FPGA IP Design 
Example Testbench
O le ṣajọ ati ṣe afiwe apẹrẹ naa nipa ṣiṣe iwe afọwọkọ kikopa lati inu aṣẹ aṣẹ.

1. Ni aṣẹ tọ, yi testbench simulating ṣiṣẹ liana: cdample_dir>/ex_25g/sim.
2. Ṣiṣe simulation IP setup:ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Table 3. Igbesẹ lati Simulate awọn Testbench

Simulator	Awọn ilana
VCS*	Ninu laini aṣẹ, tẹ sh run_vcs.sh
QuestaSim*	Ninu laini aṣẹ, tẹ vsim -do run_vsim.do -logfile vsim.log Ti o ba fẹ lati ṣe adaṣe lai mu QuestaSim GUI soke, tẹ vsim -c -do run_vsim.do -logfile vsim.log
Cadence -Xcelium*	Ninu laini aṣẹ, tẹ sh run_xcelium.sh

Simulation aṣeyọri pari pẹlu ifiranṣẹ atẹle:
Simulation Ti kọja. tabi Testbench pari.
Lẹhin ipari aṣeyọri, o le ṣe itupalẹ awọn abajade.
1.5. Iṣakojọpọ ati Ṣiṣeto Oniru Example ni Hardware
Olootu paramita 25G Ethernet Intel FPGA IP mojuto n gba ọ laaye lati ṣajọ ati tunto apẹrẹ apẹẹrẹ tẹlẹ.ample lori ohun elo idagbasoke ibi-afẹde.

Lati ṣajọ ati tunto apẹrẹ exampLe lori hardware, tẹle awọn igbesẹ wọnyi:

1. Lọlẹ Intel Quartus Prime Pro Edition sọfitiwia ki o yan Ṣiṣẹpọ ➤ Bẹrẹ Iṣakojọpọ lati ṣajọ apẹrẹ naa.
2. Lẹhin ti o ṣe ina ohun SRAM file .sof, tẹle awọn igbesẹ wọnyi lati ṣe eto apẹrẹ hardware example lori ẹrọ Intel Agilex:
   a. Lori awọn Irinṣẹ akojọ, tẹ Programmer.
   b. Ni awọn Programmer, tẹ Hardware Setup.
   c. Yan ẹrọ siseto.
   d. Yan ki o ṣafikun igbimọ Intel Agilex si igba Intel Quartus Prime Pro Edition rẹ.
   e. Rii daju pe Ipo ti ṣeto si JTAG.
   f. Yan ẹrọ Intel Agilex ki o tẹ Fi ẹrọ kun. Awọn pirogirama han
   aworan atọka ti awọn asopọ laarin awọn ẹrọ lori ọkọ rẹ.
   g. Ni ila pẹlu .sof rẹ, ṣayẹwo apoti fun .sof.
   h. Ṣayẹwo apoti ti o wa ninu iwe Eto / Tunto.
   i. Tẹ Bẹrẹ.

1.6. Idanwo F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
Lẹhin ti o ṣajọ F-tile 25G Ethernet Intel FPGA IP mojuto oniru example ki o tunto lori ẹrọ Intel Agilex rẹ, o le lo Console System lati ṣe eto ipilẹ IP naa.
Lati tan-an Console System ati idanwo apẹrẹ hardware example, tẹle awọn igbesẹ wọnyi:

1. Ninu sọfitiwia Intel Quartus Prime Pro Edition, yan Awọn irinṣẹ ➤ Eto
   Awọn Irinṣẹ N ṣatunṣe aṣiṣe ➤ System Console lati ṣe ifilọlẹ console eto naa.
2. Ninu PAN Tcl Console, tẹ cd hwtest lati yi itọsọna pada si / hardware_test_design/hwest.
3. Tẹ orisun main.tcl lati ṣii asopọ si JTAG oluwa.

Tẹle ilana idanwo ni apakan Idanwo Hardware ti apẹrẹ example ṣe akiyesi awọn abajade idanwo ni Console System.

F-tile 25G àjọlò Design Eksample fun Intel Agilex Devices

F-tile 25G Ethernet apẹrẹ example ṣe afihan ojutu Ethernet kan fun awọn ẹrọ Intel Agilex nipa lilo 25G Ethernet Intel FPGA IP mojuto.
Ṣe ina apẹrẹ example lati Example Design taabu ti 25G àjọlò Intel FPGA IP paramita olootu. O tun le yan lati ṣe ina apẹrẹ pẹlu tabi laisi
Reed-Solomon Atunse Aṣiṣe Iwaju (RS-FEC) ẹya.
2.1. Awọn ẹya ara ẹrọ

• Ṣe atilẹyin ikanni Ethernet kan ti n ṣiṣẹ ni 25G.
• Ṣe ipilẹṣẹ apẹrẹ example pẹlu RS-FEC ẹya-ara.
• Pese testbench ati kikopa akosile.
• Instantiates F-Tile Reference ati System PLL aago Intel FPGA IP da lori IP iṣeto ni.

2.2. Hardware ati Software Awọn ibeere
Intel nlo awọn wọnyi hardware ati software lati se idanwo awọn oniru example ni eto Linux kan:

• Intel Quartus NOMBA Pro Edition software.
• Siemens* EDA QuestaSim, Synopsys* VCS, ati Cadence Xcelium simulator.
• Intel Agilex I-jara Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) fun idanwo ohun elo.

2.3. Apejuwe iṣẹ
F-tile 25G Ethernet apẹrẹ example oriširiši MAC + PCS + PMA mojuto iyatọ. Awọn aworan atọka bulọọki atẹle yii ṣafihan awọn paati apẹrẹ ati awọn ifihan agbara ipele oke ti iyatọ mojuto MAC+PCS+PMA ni F-tile 25G Ethernet design ex.ample.
Olusin 5. Àkọsílẹ aworan atọka-F-tile 25G àjọlò Design Example (MAC+PCS+PMA Core Variant)

2.3.1. Awọn irinše apẹrẹ
Tabili 4. Awọn irinše apẹrẹ

Ẹya ara ẹrọ	Apejuwe
F-tile 25G àjọlò Intel FPGA IP	Ni ti MAC, PCS, ati Transceiver PHY, pẹlu iṣeto ni atẹle: • Iyatọ mojuto: MAC+PCS+PMA • Mu iṣakoso sisan ṣiṣẹ: iyan • Mu iran aṣiṣe ọna asopọ ṣiṣẹ: iyan • Jeki apere passthrough ṣiṣẹ: iyan • Mu awọn iṣiro ṣiṣẹ: iyan • Mu awọn iṣiro iṣiro MAC ṣiṣẹ: iyan • Igbohunsafẹfẹ aago: 156.25 Fun apẹrẹ example pẹlu ẹya RS-FEC, paramita afikun atẹle ti wa ni tunto: • Mu RS-FEC ṣiṣẹ: iyan
F-Tile Reference ati System PLL Agogo Intel FPGA IP	Itọkasi Tile F-Tile ati Eto PLL Awọn eto oluṣatunṣe paramita IP Intel FPGA IP ni ibamu pẹlu awọn ibeere ti F-tile 25G Ethernet Intel FPGA IP. Ti o ba ṣe ina apẹrẹ example lo Ṣẹda Example Apẹrẹ bọtini ni IP paramita olootu, awọn IP instantiates laifọwọyi. Ti o ba ṣẹda ti ara rẹ oniru example, o gbọdọ ọwọ instantiate yi IP ki o si so gbogbo mo / O ebute oko. Fun alaye nipa IP yii, tọka si F-Tile Architecture ati PMA ati FEC Taara PHY IP Itọsọna olumulo.
Onibara kannaa	Ni ninu: • Olupilẹṣẹ ijabọ, eyiti o ṣe awọn apo-iwe ti nwaye si 25G Ethernet Intel FPGA IP mojuto fun gbigbe. • Atẹle ijabọ, eyiti o ṣe abojuto awọn apo-iwe ti nwaye ti o nbọ lati inu 25G Ethernet Intel FPGA IP mojuto.
Orisun ati Iwadi	Orisun ati awọn ifihan agbara iwadii, pẹlu ifihan agbara atunto eto, eyiti o le lo fun n ṣatunṣe aṣiṣe.

Alaye ti o jọmọ
F-Tile Architecture ati PMA ati FEC Taara PHY IP Itọsọna olumulo

Afọwọṣe

Testbench firanṣẹ ijabọ nipasẹ mojuto IP, ṣiṣe adaṣe ẹgbẹ atagba ati gba ẹgbẹ ti mojuto IP.
2.4.1. Testbench
olusin 6. Àkọsílẹ aworan atọka ti F-tile 25G Ethernet Intel FPGA IP Design Example Simulation Testbench

Table 5. Testbench irinše

Ẹya ara ẹrọ	Apejuwe
Ẹrọ ti o wa labẹ idanwo (DUT)	25G Ethernet Intel FPGA IP mojuto.
Àjọlò Packet monomono ati Packet Monitor	Olupilẹṣẹ apo n ṣe awọn fireemu ati gbejade si DUT. Atẹle Packet ṣe abojuto TX ati awọn ipa ọna data RX ati ṣafihan awọn fireemu ninu console simulator.
F-Tile Reference ati System PLL Agogo Intel FPGA IP	Ṣe ipilẹṣẹ transceiver ati eto awọn aago itọkasi PLL.

2.4.2. Simulation Design Example irinše
Table 6. F-tile 25G àjọlò Design Eksample Testbench File Awọn apejuwe

File Oruko	Apejuwe
Testbench ati Simulation Files
ipilẹ_avl_tb_top.v	Igbeyewo ipele oke file. Testbench naa ṣe imudara DUT naa, ṣe atunto Avalon® iranti-mapped iṣeto ni awọn paati apẹrẹ ati ọgbọn alabara, ati firanṣẹ ati gba apo-iwe si tabi lati 25G Ethernet Intel FPGA IP.
Awọn iwe afọwọkọ Testbench
tesiwaju…

File Oruko	Apejuwe
run_vsim.do	Iwe afọwọkọ ModelSim lati ṣiṣe testbench.
run_vcs.sh	Awọn Synopsys VCS iwe afọwọkọ lati ṣiṣe awọn testbench.
run_xcelium.sh	Iwe afọwọkọ Cadence Xcelium lati ṣiṣe testbench naa.

2.4.3. Ọran Idanwo
Ọran idanwo kikopa ṣe awọn iṣe wọnyi:

1. Instantiates F-tile 25G àjọlò Intel FPGA IP ati F-Tile Reference ati System PLL aago Intel FPGA IP.
2. Nduro fun aago RX ati ifihan ipo PHY lati yanju.
3. Tẹjade ipo PHY.
4. Firanṣẹ ati gba data to wulo 10.
5. Ṣe itupalẹ awọn abajade. Aṣeyọri testbench ṣe afihan “Testbench ti pari.”.

Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo kikopa aṣeyọri kan:

Iṣakojọpọ

Tẹle ilana naa ni Ṣiṣepo ati Ṣiṣeto Oniru Example ni Hardware lati ṣajọ ati tunto apẹrẹ example ninu awọn ti o yan hardware.
O le ṣe iṣiro lilo awọn orisun ati Fmax nipa lilo iṣakojọpọ-nikan apẹrẹ example. O le ṣe akopọ apẹrẹ rẹ nipa lilo aṣẹ Ibẹrẹ Ibẹrẹ lori awọn
Akojọ aṣayan iṣẹ-ṣiṣe ni sọfitiwia Intel Quartus Prime Pro Edition. Aṣeyọri ti o ṣaṣeyọri n ṣe agbejade akopọ ijabọ akopọ.
Fun alaye diẹ sii, tọka si Iṣakojọpọ Oniru ninu Itọsọna olumulo olumulo Intel Quartus Prime Pro Edition.
Alaye ti o jọmọ

• Iṣakojọpọ ati Ṣiṣeto Oniru Example in Hardware loju iwe 7
• Iṣakojọpọ Oniru Ni Itọsọna olumulo olumulo Intel Quartus Prime Pro Edition

2.6. Hardware Igbeyewo
Ni hardware oniru exampLe, o le eto awọn IP mojuto ni ti abẹnu ni tẹlentẹle loopback mode ati ina ijabọ lori awọn atagba ẹgbẹ ti o losiwajulosehin pada nipasẹ awọn gba ẹgbẹ.
Tẹle ilana naa ni ọna asopọ alaye ti o ni ibatan ti a pese lati ṣe idanwo apẹrẹ example ninu awọn ti o yan hardware.
Alaye ti o jọmọ
Idanwo F-tile 25G Ethernet Intel FPGA IP Hardware Design Example ni oju -iwe 8
2.6.1. Ilana Idanwo
Tẹle awọn igbesẹ wọnyi lati ṣe idanwo apẹrẹ example ni hardware:

1. Ṣaaju ki o to ṣiṣe awọn igbeyewo hardware fun yi oniru example, o gbọdọ tun eto naa:
   a. Tẹ Awọn irinṣẹ ➤ Awọn orisun inu-System & irinṣẹ Olootu fun orisun aiyipada ati GUI Probe.
   b. Yi ifihan eto atunto eto (Orisun[3:0]) lati 7 si 8 lati lo awọn atunto ati da ifihan eto atunto pada si 7 lati tu eto naa silẹ lati ipo atunto.
   c. Bojuto awọn ifihan agbara Iwadi ati rii daju pe ipo naa wulo.
2. Ninu console eto, lilö kiri si folda hwtest ati ṣiṣe aṣẹ naa: main.tcl orisun lati yan J kanTAG oluwa. Nipa aiyipada, akọkọ JTAG oluwa lori JTAG pq ti yan. Lati yan JTAG titunto si fun awọn ẹrọ Intel Agilex, ṣiṣe aṣẹ yii: set_jtag <number of appropriate JTAG oluwa>. Example: set_jtag 1.
3. Ṣiṣe awọn aṣẹ wọnyi ni console eto lati bẹrẹ idanwo loopback ni tẹlentẹle:

Table 7. Òfin paramita

Paramita	Apejuwe	Example Lilo
chkphy_ipo	Ṣe afihan awọn igbohunsafẹfẹ aago ati ipo titiipa PHY.	% chkphy_status 0 # Ṣayẹwo ipo ọna asopọ 0
chkmac_stats	Ṣe afihan awọn iye ninu awọn iṣiro iṣiro MAC.	% chkmac_stats 0 # Ṣayẹwo iṣiro iṣiro mac ti ọna asopọ 0
clear_all_stats	Pa awọn iṣiro iṣiro ipilẹ IP kuro.	% clear_all_stats 0 # Pa awọn iṣiro iṣiro ti ọna asopọ 0 kuro
bẹrẹ_gen	Bẹrẹ awọn soso monomono.	% start_gen 0 # Bẹrẹ iran soso lori ọna asopọ 0
Duro_gen	Da packet monomono.	% stop_gen 0 # Duro iran soso lori ọna asopọ 0
loop_lori	Yipada ti abẹnu ni tẹlentẹle loopback.	% loop_on 0 # Tan loopback inu lori ọna asopọ 0
loop_off	Pa ti abẹnu ni tẹlentẹle loopback.	% loop_off 0 # Pa a loopback inu lori ọna asopọ 0
reg_read	Pada iye iforukọsilẹ mojuto IP pada ni .	% reg_read 0x402 # Ka iforukọsilẹ IP CSR ni adirẹsi 402 ti ọna asopọ 0
reg_write	Kọ si iforukọsilẹ mojuto IP ni adirẹsi .	% reg_write 0x401 0x1 # Kọ 0x1 si IP CSR iforukọsilẹ ibere ni adirẹsi 401 ti ọna asopọ 0

a. Tẹ loop_on lati tan awọn ti abẹnu ni tẹlentẹle loopback mode.
b. Tẹ chkphy_status lati ṣayẹwo ipo ti PHY. Ipo TXCLK, RXCLK, ati RX yẹ ki o ni awọn iye kanna ti o han ni isalẹ fun ọna asopọ iduroṣinṣin:

c. Tẹ clear_all_stats lati ko awọn iforukọsilẹ awọn iṣiro TX ati RX kuro.
d. Tẹ start_gen lati bẹrẹ iran soso.
e. Tẹ stop_gen lati da soso iran.
f. Tẹ chkmac_stats lati ka TX ati awọn iṣiro iṣiro RX. Rii daju pe:
i. Awọn fireemu soso ti a tan kaakiri baamu awọn fireemu apo-iwe ti o gba.
ii. Ko si awọn fireemu aṣiṣe ti gba.
g. Tẹ loop_off lati yipada si pa awọn ti abẹnu ni tẹlentẹle loopback.
Olusin 7. Sample Igbeyewo Jade-TX ati RX Statistics Counters

Itan Atunyẹwo iwe fun F-tile 25G Ethernet FPGA IP Design Example User Itọsọna

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
2022.10.14	22.3	1.0.0	Itusilẹ akọkọ.

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO
9001:2015
Iforukọsilẹ

Idajọ Ayelujara
Fi esi ranṣẹ
ID: 750200
Ẹya: 2022.10.14

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intel F-Tile 25G àjọlò FPGA IP Design Eksample [pdf] Itọsọna olumulo F-Tile 25G àjọlò FPGA IP Design Eksample, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Design Example, IP Design Example,750200

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