intel Cyclone 10 Native FloatingPoint DSP FPGA IP
Intel® Cyclone® 10 GX Native Point-Point DSP Intel® FPGA IP Jagorar Mai Amfani
Daidaita Intel® Cyclone® 10 GX Native Point-Point DSP Intel® FPGA IP
Zaɓi sigogi daban-daban don ƙirƙirar ainihin IP wanda ya dace da ƙirar ku.
- A cikin Intel® Quartus® Prime Pro Edition, ƙirƙiri sabon aikin da ke hari na'urar Intel Cyclone® 10 GX.
- A cikin Catalog na IP, danna kan Laburare ➤ DSP ➤ Primitive DSP ➤ Intel Cyclone 10 GX Native Floating Point DSP.
The Intel Cyclone 10 GX Native Floating-Point DSP IP Core IP editan siga yana buɗewa. - A cikin sabon akwatin maganganu na IP, shigar da sunan mahallin kuma danna Ok.
- A ƙarƙashin Parameters, zaɓi Samfuran DSP da View kana so don IP core
- A cikin DSP Block View, kunna agogo ko sake saitin kowace rijista mai inganci.
- Don Ƙirƙirar Ƙara ko Yanayin Vector 1, danna kan Sarkar In multiplexer a cikin GUI don zaɓar shigarwa daga tashar tashar tashar ko tashar Ax.
- Danna alamar Adder a cikin GUI don zaɓar ƙari ko ragi.
- Danna kan Sarkar Out multiplexer a cikin GUI don kunna tashar tashar sarkar.
- Danna Ƙirƙirar HDL.
- Danna Gama.
Intel Cyclone 10 GX Native Point-Point DSP Intel FPGA IP Parameters
Tebur 1. Ma'auni
| Siga | Daraja | Default Value | Bayani |
| Samfuran DSP | Yawan ninka Ƙara
Haɓaka Ƙara Haɓaka Haɓaka Haɓaka Yanayin Vector 1 Yanayin Vector 2 |
Yawan ninka | Zaɓi yanayin aiki da ake so don toshewar DSP.
Aikin da aka zaɓa yana nunawa a cikin DSP Block View. |
| View | Rijista yana ba da damar share rijista | Rijista Yana Kunnawa | Zaɓuɓɓuka don zaɓar tsarin clocking ko tsarin sake saiti don rajista view. Aikin da aka zaɓa yana nunawa a cikin DSP Block View. |
| ci gaba… | |||
| Siga | Daraja | Default Value | Bayani |
| Zaɓi Rijista Yana Kunnawa domin DSP Block View don nuna tsarin clocking rajista. Kuna iya canza agogo don kowane rajista a cikin wannan view.
Zaɓi Rijista Shares domin DSP Block View don nuna tsarin sake saitin rajista. Kunna Yi amfani da Bayyanar Single don canza tsarin sake saitin rajista. |
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| Yi amfani da Bayyanar Single | Kunnawa ko kashewa | Kashe | Kunna wannan sigar idan kuna son sake saiti ɗaya don sake saita duk rajistar da ke cikin toshewar DSP. Kashe wannan siga don amfani da tashoshin sake saiti daban-daban don sake saita rijistar.
Kunna don share 0 akan rijistar fitarwa; kashe don share 1 akan rijistar fitarwa. Share 0 don shigar da rajista yana amfani da aclr[0] sigina. Share 1 don amfani da fitarwa da rajistar bututu aclr[1]. Duk rijistar shigarwa suna amfani da siginar sake saiti aclr[0]. Duk fitarwa da rajistar bututu suna amfani da siginar sake saiti aclr[1]. |
| DSP View Toshe | |||
| Sarkar a Multiplexer (14) | Kunna Kashe | A kashe | Danna kan multiplexer don kunna chainin
tashar jiragen ruwa. |
| Sarkar da yawa (12) | Kashe kunna | A kashe | Danna kan Multixer don kunna sarkar
tashar jiragen ruwa. |
| Adder (13) | +
– |
+ | Danna kan Adder alama don zaɓar ƙari ko yanayin ragi. |
| Agogon rajista
• agogon karfe (2) • agogon aya (3) • az_clock (4) • mult_pipeline_clock k(5) • ax_chainin_pl_clock k (7) • Adder_input_clock (9) • adder_input_2_clock ck (10) • agogon fitarwa (11) • tara_clock (1) • accum_pipeline_cl ock (6) • accum_adder_clock k (8) |
Babu Agogo 0
Agogo 1 Agogo 2 |
Agogo 0 | Don ketare kowace rajista, kunna agogon rajista zuwa Babu.
Juya agogon rajista zuwa: • Agogo 0 don amfani da siginar clk[0] azaman tushen agogo • Agogo 1 don amfani da siginar clk[1] azaman tushen agogo • Agogo 2 don amfani da siginar clk[2] azaman tushen agogo Kuna iya canza waɗannan saitunan kawai lokacin da kuka zaɓa Rijista Yana Kunnawa in View siga. |
Hoto 1. DSP Block View
Tebur 2. Samfuran DSP
| Samfuran DSP | Bayani |
| Yawan ninka | Yana aiwatar da daidaitaccen aikin ninkawa guda ɗaya kuma yana amfani da ma'auni mai zuwa:
• Fita = Ay * Az |
| Ƙara | Yana aiwatar da daidaitaccen ƙari ko aikin ragewa guda ɗaya kuma yana amfani da ma'auni masu zuwa:.
• Fita = Ay + Gatari • Fita = Ay – Gatari |
| Ƙara Ƙara | Wannan yanayin yana yin daidaici guda ɗaya, tare da ƙari ko ayyukan ragi kuma yana aiwatar da ma'auni masu zuwa.
• Out = (Ay * Az) - sarkar • Out = (Ay * Az) + sarkar • Fita = (Ay * Az) - Gatari • Fita = (Ay * Az) + Gatari |
| Haɓaka Tara | Yana yin ninka-makamai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-mai-kan-kan-bi-bi-bi-bi-bi-bi-bi-bi-bi-ta-manu-mama-ko ragi tare da sakamakon da ya gabata da kuma amfani da wadannan equations:
• Fita (t) = [Ay (t) * Az(t)] - Fita (t-1) lokacin da aka tara sigina yana motsawa sama. • Out(t) = [Ay (t) * Az(t)] + Fita (t-1) lokacin da tara tashar jiragen ruwa ke da ƙarfi. • Out(t) = Ay(t) * Az(t) lokacin da aka tara tashar jiragen ruwa. |
| Yanayin Vector 1 | Yana yin ninka-makamai-mai iyo wanda ya biyo baya da ƙari ko ragi tare da shigarwar chainin daga madaidaicin toshewar DSP da ya gabata kuma yana aiwatar da ma'auni masu zuwa:. |
| ci gaba… | |
| Samfuran DSP | Bayani |
| • Out = (Ay * Az) - sarkar
• Out = (Ay * Az) + sarkar • Out = (Ay * Az) , sarkar = Gatari |
|
| Yanayin Vector 2 | Yana yin ninka-makamai-mai iyo inda tushen IP ke ciyar da sakamakon ninkawa kai tsaye zuwa sarkar. Sa'an nan IP core yana ƙara ko rage shigarwar chainin daga madaidaicin DSP toshe na baya daga shigar da Ax azaman sakamakon fitarwa.
Wannan yanayin yana amfani da ma'auni masu zuwa: • Out = Gatari – sarkar , sarkar = Ay * Az • Out = Gatari + sarkar , sarkar = Ay * Az • Out = Gatari , sarkar = Ay * Az |
Intel Cyclone 10 GX Native Point-Point DSP Intel FPGA IP Sigina
Hoto 2. Intel Cyclone 10 GX Native-Point-Point DSP Intel FPGA IP Sigina
Hoton yana nuna alamun shigarwa da fitarwa na ainihin IP.
Tebur 3. Intel Cyclone 10 GX Native Point-Point DSP Intel FPGA IP Siginoni
| Sunan siginar | Nau'in | Nisa | Default | Bayani |
| gata[31:0] | Shigarwa | 32 | Ƙananan | Shigar da bas ɗin bayanai zuwa mai ninkawa. Akwai a:
• Ƙara yanayin • Haɓaka-Ƙara yanayin ba tare da fasalin sarƙoƙi ba • Yanayin Vector 1 • Yanayin Vector 2 |
| ina[31:0] | Shigarwa | 32 | Ƙananan | Shigar da bas ɗin bayanai zuwa mai ninkawa.
Akwai a cikin duk yanayin aiki mai iyo-point. |
| zo[31:0] | Shigarwa | 32 | Ƙananan | Shigar da bas ɗin bayanai zuwa mai ninkawa. Akwai a:
• ninka • Haɓaka Ƙara • Haɓaka Taruwa • Yanayin Vector 1 • Yanayin Vector 2 |
| sarkar[31:0] | Shigarwa | 32 | Ƙananan | Haɗa waɗannan sigina zuwa siginar sarƙoƙi daga madaidaicin madaidaicin madaidaicin DSP IP na gaba. |
| kowa[2:0] | Shigarwa | 3 | Ƙananan | Sigina na agogon shigarwa don duk rajista.
Waɗannan sigina na agogo suna samuwa ne kawai idan an saita kowane rajistar shigarwa, rajistar bututu, ko rajistar fitarwa zuwa Agogo0 or Agogo1 or Agogo2. |
| ina[2:0] | Shigarwa | 3 | Babban | Kunna agogo don clk[2:0]. Waɗannan sigina suna aiki-Mafi girma.
• ena[0] don Agogo0 • ena[1] don Agogo1 • ena[2] don Agogo2 |
| ku[1:0] | Shigarwa | 2 | Ƙananan | Siginonin shigarwa masu daidaitawa ga duk rijistar. Waɗannan sigina suna aiki-high.
Amfani aclr[0] don duk shigarwar rajista da amfani aclr[1] ga duk rajistar bututu da fitarwa. |
| tara | Shigarwa | 1 | Ƙananan | Siginar shigarwa don kunna ko kashe fasalin tarawa.
Tabbatar da wannan siginar don ba da damar mayar da martani ga fitar da ƙara. Kashe wannan siginar don kashe hanyar mayar da martani. Kuna iya tabbatarwa ko kashe wannan siginar yayin lokacin gudu. Akwai a cikin Yanayin Haɓakawa. |
| [31:0] | Fitowa | 32 | — | Haɗa waɗannan sigina zuwa siginar sarƙoƙi na madaidaicin madaidaicin IP na gaba na DSP. |
| sakamako[31:0] | Fitowa | 32 | — | Bus ɗin fitarwa daga cibiyar IP. |
Tarihin Bita daftarin aiki
Canje-canje ga Intel Cyclone 10 GX Native Point Point DSP Intel FPGA IP Jagorar Mai Amfani
| Kwanan wata | Sigar | Canje-canje |
| Nuwamba 2017 | 2017.11.06 | Sakin farko. |
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
Takardu / Albarkatu
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intel Cyclone 10 Native FloatingPoint DSP FPGA IP [pdf] Jagorar mai amfani Cyclone 10 Native FloatingPoint DSP FPGA IP, 10 Native FloatingPoint DSP FPGA IP, Native FloatingPoint DSP FPGA IP, FloatingPoint DSP FPGA IP, DSP FPGA IP, FPGA IP |
