FPGA IP
Moqapi Example Bukana ea Mosebelisi
F-Tile 25G Ethernet Intel®
E ntlafalitsoe bakeng sa Intel® Quartus®
Prime Design Suite: 22.3
Phetolelo ea IP: 1.0.0

Tataiso ea ho Qala ka Potlako

F-tile 25G Ethernet Intel FPGA IP bakeng sa lisebelisoa tsa Intel Agilex ™ e fana ka bokhoni ba ho hlahisa moralo oa khale.amples bakeng sa litlhophiso tse khethiloeng.
Setšoantšo sa 1. Moqapi Example Tšebeliso

Sebopeho sa Directory

Setšoantšo sa 2. 25G Ethernet Intel FPGA IP Design Example Sebopeho sa Directory

• Ketsiso files (testbench bakeng sa ketsiso feela) li tengample_dir>/example_testbench.
• Moqapi oa ho bokella feela example e tengample_dir>/ compilation_test_design.
• Sebopeho sa hardware le teko files (moqapi, mohlalaample in hardware) li tengample_dir>/hardware_test_design.

Lethathamo la 1. Directory le File Litlhaloso

File Mabitso	Tlhaloso
eth_ex_25g.qpf	Morero oa mantlha oa Intel Quartus® file.
eth_ex_25g.qsf	Litlhophiso tsa projeke ea Intel Quartus Prime file.
eth_ex_25g.sdc	Litšitiso tsa Moqapi oa Synopsys file. U ka kopitsa le ho fetola sena file bakeng sa moralo oa hau oa mantlha oa 25GbE Intel FPGA IP.
eth_ex_25g.v	Moralo oa maemo a holimo oa Verilog HDL example file. Moralo oa mocha o le mong o sebelisa Verilog file.
tloaelehileng/	Moetso oa li-hardware example tšehetso files.
hwtest/main.tcl	Ka sehloohong file bakeng sa ho fihlella System Console.

Ho Hlahisa Moqapi Example

Setšoantšo sa 4. Example Design Tab ho F-tile 25G Ethernet Intel FPGA IP Parameter Editor

Latela mehato ena ho hlahisa sebopeho sa hardware example le testbench:

1. Ho Intel Quartus Prime Pro Edition, tobetsa File ➤ Project Wizard e Ncha ho theha projeke e ncha ea Quartus Prime, kapa File ➤ Open Project ho bula morero o teng oa Quartus Prime. Wizate e o kopa hore o hlalose sesebediswa.
2. Ho IP Catalog, fumana 'me u khethe 25G Ethernet Intel FPGA IP bakeng sa Agilex. Ho hlaha fensetere e ncha ea IP Variation.
3. Hlalosa lebitso la boemo bo holimo bakeng sa phapano ea hau ea IP ebe o tobetsa OK. Mohlophisi oa parameter o eketsa boemo bo holimo .ip file ho morero oa hajoale ka bo eona. Haeba u khothalletsoa ho kenya .ip ka letsoho file ho morero, tobetsa Morero ➤ Eketsa/ Tlosa Files ho Morero ho eketsa file.
4. Ho software ea Intel Quartus Prime Pro Edition, o tlameha ho khetha sesebelisoa se itseng sa Intel Agilex tšimong ea Sesebelisoa, kapa u boloke sesebelisoa sa kamehla se hlahisoang ke Intel Quartus Prime software.
   Hlokomela: Moetso oa hardware example overwrites kgetho le sesebediswa ka shebiloeng boto. U hlakisa boto e shebiloeng ho tsoa ho menu ea moralo oa example dikgetho ho Example Design tab.
5. Tobetsa OK. Mohlophisi oa parameter oa hlaha.
6. Ho tab ea IP, hlakisa li-parameter tsa IP ea hau ea mantlha.
7. Ho Example Design tab, bakeng sa Example Design Files, khetha Simulation kgetho ho hlahisa testbench, 'me khetha Synthesis kgetho ho hlahisa hardware moralo ex.ample. Ke Verilog HDL feela files li hlahisoa.
   Hlokomela: Sesebelisoa se sebetsang sa VHDL IP ha se fumanehe. Hlalosa Verilog HDL feela, bakeng sa moralo oa hau oa mantlha oa IPample.
8. Bakeng sa Target Development Kit, khetha Agilex I-series Transceiver-SoC Dev Kit
9. Tobetsa Hlahisa Example konopo ea Design. Khetha Exampho hlaha fensetere ea Design Directory.
10. Haeba u lakatsa ho fetola moralo examptsela ea directory kapa lebitso ho tsoa ho li-defaults tse bontšitsoeng (alt_e25_f_0_example_design), sheba tsela e ncha ebe u thaepa sebopeho se secha sa examplebitso la directory (ample_dir>).
11. Tobetsa OK.

1.2.1. Moralo Example Li-Parameters
Lethathamo la 2. Mekhahlelo ho Example Design Tab

Paramethara	Tlhaloso
Example Design	E fumaneha example meralo bakeng sa litlhophiso tsa paramethara ea IP. Ke mohlala oa mocha o le mong feelaample moralo o tšehetsoa bakeng sa IP ena.
Example Design Files	The files ho hlahisa bakeng sa mokhahlelo o fapaneng oa ntlafatso. • Ketsiso—e hlahisa se hlokahalang files bakeng sa ho etsisa exampmoralo. • Synthesis-e hlahisa motsoako files. Sebelisa tsena files ho bokella moralo ho software ea Intel Quartus Prime Pro Edition bakeng sa tlhahlobo ea lisebelisoa le ho etsa tlhahlobo ea nako e tsitsitseng.
Hlahisa File Sebopeho	Sebopeho sa RTL files bakeng sa ketsiso — Verilog.
Khetha Boto	Hardware e tšehelitsoeng bakeng sa ts'ebetsong ea moralo. Ha u khetha boto ea nts'etsopele ea Intel FPGA, sebelisa sesebelisoa sa AGIB027R31B1E2VRO joalo ka Sesebelisoa sa Target bakeng sa moralo oa khale.ample moloko. Agilex I-Series Transceiver-SoC Dev Kit: Khetho ena e u lumella ho lekola moralo oa khale.ample ho lisebelisoa tse khethiloeng tsa Intel FPGA IP. Khetho ena e ikhethela sesebelisoa sa Target sa AGIB027R31B1E2VRO. Haeba tlhahlobo ea boto ea hau e na le kereiti e fapaneng ea sesebelisoa, o ka fetola sesebelisoa se shebiloeng. Ha ho letho: Khetho ena ha e kenyelle likarolo tsa hardware bakeng sa ex designample.

1.3. Ho Hlahisa Tile Files

The Support-Logic Generation ke mohato oa pele-pele o sebelisetsoang ho hlahisa tse amanang le lithaele files hlokahala bakeng sa ketsiso le moralo hardware. Ho hlahisa lithaele ho hlokahala bakeng sa bohle
Lipapiso tsa moralo tse thehiloeng ho F-tile. U tlameha ho qeta mohato ona pele ho ketsiso.

1. Ka taelo ea litaelo, ea ho foldara ea compilation_test_design ho ex ea hauample moralo: cd /compilation_test_design.
2. Etsa taelo e latelang: quartus_tlg alt_eth_25g

1.4. Ho etsisa F-tile 25G Ethernet Intel FPGA IP Design 
Example Testbench
O ka bokella le ho etsisa moralo ka ho sebelisa mongolo oa ketsiso ho tsoa ho taelo ea taelo.

1. Ka potlako ea taelo, fetola sesebelisoa sa testbench simulating: cdample_dir>/ex_25g/sim.
2. Etsa ketsiso ea ho seta ea IP:ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Letlapa la 3. Mehato ea ho etsisa Testbench

Moetsisi	Litaelo
VCS*	Moleng oa taelo, thaepa sh run_vcs.sh
QuestaSim*	Moleng oa taelo, thaepa vsim -do run_vsim.do -logfile vsim.log Haeba u khetha ho etsisa ntle le ho hlahisa QuestaSim GUI, thaepa vsim -c -do run_vsim.do -logfile vsim.log
Cadence -Xcelium*	Moleng oa taelo, thaepa sh run_xcelium.sh

Ketsiso e atlehileng e qetella ka molaetsa o latelang:
Ketsiso e Fetile. kapa Testbench e phethiloe.
Ka mor'a ho qeta ka katleho, u ka sekaseka liphetho.
1.5. Ho Kopanya le ho Hlophisa Moralo Example ho Hardware
25G Ethernet Intel FPGA IP core parameter editor e u lumella ho bokella le ho lokisa moralo oa ex.ample ho khithi ea ntlafatso e reriloeng.

Ho bokella le ho lokisa sebopeho sa exampka hardware, latela mehato ena:

1. Qala software ea Intel Quartus Prime Pro Edition ebe u khetha Ho sebetsa ➤ Qala Kopano ho hlophisa moralo.
2. Ka mor'a hore u hlahise ntho ea SRAM file .sof, latela mehato ena ho hlophisa moralo oa hardware example sesebelisoa sa Intel Agilex:
   a. Ho Tools menu, tobetsa Programmer.
   b. Ho "Programmer", tobetsa "Hardware Setup".
   c. Khetha sesebelisoa sa ho etsa mananeo.
   d. Khetha 'me u kenye boto ea Intel Agilex sebokeng sa hau sa Intel Quartus Prime Pro Edition.
   e. Netefatsa hore Mode e setetsoe ho JTAG.
   f. Khetha sesebelisoa sa Intel Agilex ebe o tobetsa Eketsa Sesebelisoa. Lenaneo le bonts'a
   setšoantšo sa li-block tsa likhokahano lipakeng tsa lisebelisoa tse botong ea hau.
   g. Moleng le .sof ea hau, hlahloba lebokose la .sof.
   h. Tshwaya lebokoso mo kholomong ya Lenaneo/Configure.
   ke. Tobetsa Qala.

1.6. Ho lekola F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
Kamora hore o bokelle moralo oa mantlha oa F-tile 25G Ethernet Intel FPGA IP example 'me u e hlophise sesebelisoa sa hau sa Intel Agilex, u ka sebelisa System Console ho hlophisa motheo oa IP.
Ho bulela System Console le ho leka moralo oa hardware example, latela mehato ena:

1. Ho software ea Intel Quartus Prime Pro Edition, khetha Lisebelisoa ➤ Sisteme
   Lisebelisoa tsa Debugging ➤ System Console ho qala komporo ea sistimi.
2. Fensetereng ea Tcl Console, thaepa cd hwtest ho fetola directory ho / hardware_test_design/hwtest.
3. Tlanya source main.tcl ho bula khokahanyo ho JTAG monghadi.

Latela mokhoa oa teko karolong ea Hardware Testing ea ex designamp'me u shebe liphetho tsa liteko ho System Console.

F-tile 25G Ethernet Design Example bakeng sa lisebelisoa tsa Intel Agilex

Moqapi oa F-tile 25G Ethernet example e bonts'a tharollo ea Ethernet bakeng sa lisebelisoa tsa Intel Agilex tse sebelisang 25G Ethernet Intel FPGA IP core.
Hlahisa sebopeho sa mohlalaample ho tsoa ho Example Design tab ea 25G Ethernet Intel FPGA IP parameter editor. U ka boela ua khetha ho hlahisa moralo ka kapa ntle le
karolo ea Reed-Solomon Forward Error Correction (RS-FEC).
2.1. Likarolo

• E tšehetsa mocha o le mong oa Ethernet o sebetsang ho 25G.
• E hlahisa example e nang le tšobotsi ea RS-FEC.
• E fana ka testbench le script ketsiso.
• Instatiates F-Tile Reference le System PLL Clocks Intel FPGA IP e thehiloeng ho tlhophiso ea IP.

2.2. Litlhoko tsa Hardware le Software
Intel e sebelisa lisebelisoa tse latelang le software ho leka moralo oa exampka sistimi ea Linux:

• Software ea Intel Quartus Prime Pro Edition.
• Siemens* EDA QuestaSim, Synopsys* VCS, le simulator ea Cadence Xcelium.
• Intel Agilex I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) bakeng sa tlhahlobo ea hardware.

2.3. Tlhaloso ea Ts'ebetso
Moqapi oa F-tile 25G Ethernet example e na le mofuta oa mantlha oa MAC+PCS+PMA. Litšoantšo tse latelang tsa li-block li bonts'a likarolo tsa moralo le matšoao a holimo-limo a MAC + PCS + PMA e fapaneng ea mantlha ho F-tile 25G Ethernet design ex.ample.
Setšoantšo sa 5. Block Diagram-F-tile 25G Ethernet Design Example (MAC+PCS+PMA Core Variant)

2.3.1. Likarolo tsa Moqapi
Lethathamo la 4. Likarolo tsa Moqapi

Karolo	Tlhaloso
F-tile 25G Ethernet Intel FPGA IP	E na le MAC, PCS, le Transceiver PHY, ka tlhophiso e latelang: • Phapang ea mantlhaTlhaloso: MAC+PCS+PMA • Numella taolo ea phallo: Taba ea boikhethelo • Lumella ho hlahisa liphoso tsa lihokelo: Taba ea boikhethelo • Lumella ho fetela pele: Taba ea boikhethelo • Lumella pokello ea lipalo: Taba ea boikhethelo • Lumella li-counters tsa lipalo tsa MAC: Taba ea boikhethelo • Reference clock frequency:156.25 Bakeng sa moqapi example karolo ea RS-FEC, paramente e latelang e lokiselitsoe: • Numella RS-FEC: Taba ea boikhethelo
Reference F-Tile le System PLL Lioache Intel FPGA IP	The F-Tile Reference le System PLL Clocks Intel FPGA IP parameter editor setting e ikamahanya le litlhoko tsa F-tile 25G Ethernet Intel FPGA IP. Haeba u hlahisa sebopeho sa example sebelisa Hlahisa Example Design konopo ho mohlophisi oa paramente ea IP, IP e itlhahisa ka bo eona. Haeba u iketsetsa moralo oa exampLeha ho le joalo, o tlameha ho tiisa IP ena ka letsoho ebe o hokela likou tsohle tsa I/O. Ho fumana lintlha ka IP ena, sheba ho F-Tile Architecture le PMA le FEC Direct PHY IP User Guide.
Monahano oa bareki	E na le: • Jenereithara ea sephethephethe, e hlahisang lipakete tse phatlohileng ho 25G Ethernet Intel FPGA IP core bakeng sa phetiso. • Traffic monitor, e hlokomelang lipakete tse phatlohileng tse tsoang ho 25G Ethernet Intel FPGA IP core.
Mohloli le Probe	Matshwao a Mohlodi le a probe, ho kenyeletswa letshwao la ho kenya botjha tsamaiso, leo o ka le sebedisang ho lokisa bothata.

Lintlha Tse Amanang
F-Tile Architecture le PMA le FEC Direct PHY IP User Guide

Ketsiso

Testbench e romela sephethephethe ka IP core, ho sebelisa lehlakore la phetisetso le ho amohela lehlakore la IP core.
2.4.1. Testbench
Setšoantšo sa 6. Thibela Setšoantšo sa F-tile 25G Ethernet Intel FPGA IP Design Example Simulation Testbench

Letlapa la 5. Likarolo tsa Testbench

Karolo	Tlhaloso
Sesebelisoa se lekoa (DUT)	25G Ethernet Intel FPGA IP ea mantlha.
Ethernet Packet jenereithara le Packet Monitor	• Jenereithara ea liphutheloana e etsa liforeimi ebe e fetisetsa DUT. • Packet Monitor monitors TX le RX datapaths and display the frames in the simulator console.
Reference F-Tile le System PLL Lioache Intel FPGA IP	E hlahisa lioache tsa litšupiso tsa transceiver le system PLL.

2.4.2. Moqapi oa Ketsiso Example Likarolo
Letlapa la 6. F-tile 25G Ethernet Design Example Testbench File Litlhaloso

File Lebitso	Tlhaloso
Testbench le Simulation Files
basic_avl_tb_top.v	Testbench ea boemo bo holimo file. Testbench e tiisa DUT, e etsa tlhophiso ea 'mapa oa mohopolo oa Avalon® holim'a likarolo tsa moralo le mohopolo oa bareki, mme e romela le ho amohela pakete ho ea kapa ho tsoa ho 25G Ethernet Intel FPGA IP.
Litemana tsa Testbench
e tsoela pele…

File Lebitso	Tlhaloso
run_vsim.do	Sengoloa sa ModelSim ho tsamaisa testbench.
run_vcs.sh	Mongolo oa Synopsys VCS ho tsamaisa testbench.
run_xcelium.sh	Sengoloa sa Cadence Xcelium ho tsamaisa testbench.

2.4.3. Nyeoe ea Teko
Sehlahisoa sa tlhahiso ea mohlala se etsa liketso tse latelang:

1. Instatiates F-tile 25G Ethernet Intel FPGA IP le F-Tile Reference le System PLL Clocks Intel FPGA IP.
2. E emetse oache ea RX le lets'oao la boemo ba PHY ho lula.
3. E hatisa boemo ba PHY.
4. E romela le ho amohela lintlha tse 10 tse sebetsang.
5. E sekaseka sephetho. Testbench e atlehileng e bonts'a "Testbench e felile".

Tse latelang sample output e bonts'a ts'ebetso e atlehileng ea teko ea ketsiso:

Pokello

Latela mokhoa oa ho Kopanya le ho Hlophisa Moqapi Example ho Hardware ho bokella le ho hlophisa sebopeho sa example ho hardware e khethiloeng.
O ka hakanya ts'ebeliso ea lisebelisoa le Fmax o sebelisa moralo oa ho bokella feela example. O ka bokella moralo oa hau o sebelisa taelo ea Start Compilation ho
Ho sebetsa lethathamo la software ea Intel Quartus Prime Pro Edition. Ho bokella ka katleho ho hlahisa kakaretso ea tlaleho ea ho bokella.
Bakeng sa tlhaiso-leseling e batsi, sheba ho Design Compilation ho Intel Quartus Prime Pro Edition User Guide.
Lintlha Tse Amanang

• Ho Kopanya le ho Hlophisa Moralo Example ho Hardware leqepheng la 7
• Mokhabiso oa Moqapi ho Intel Quartus Prime Pro Edition User Guide

2.6. Teko ea Hardware
Moqapi oa lisebelisoa tsa thepa example, o ka hlophisa mantlha ea IP ka har'a mokhoa oa ka hare oa serial loopback mme o hlahise sephethephethe lehlakoreng la phetisetso le khutlelang ka lehlakoreng le amohelang.
Latela mokhoa o ho sehokelo sa tlhaiso-leseling se amanang ho leka sebopeho sa example ho hardware e khethiloeng.
Lintlha Tse Amanang
Ho lekola F-tile 25G Ethernet Intel FPGA IP Hardware Design Example leqepheng la 8
2.6.1. Tsamaiso ea Teko
Latela mehato ena ho leka moralo oa example ka hardware:

1. Pele o etsa tlhahlobo ea lisebelisoa bakeng sa moralo ona oa exampLeha ho le joalo, o tlameha ho tsosolosa tsamaiso:
   a. Tobetsa Lisebelisoa ➤ Mehloli ea In-System & Probes Editor sesebelisoa bakeng sa Mohloli oa kamehla le Probe GUI.
   b. Fetola lets'oao la reset ea sistimi (Mohloli [3: 0]) ho tloha ho 7 ho isa ho 8 ho kenya ts'ebetso ea li-reset le ho khutlisetsa lets'oao la reset ea sistimi ho 7 ho lokolla sistimi ho tsoa boemong ba ho qala bocha.
   c. Lekola matshwao a Probe mme o netefatse hore boemo bo nepahetse.
2. Ho system console, ea ho hwtest foldareng 'me u tsamaise taelo: source main.tcl ho khetha J.TAG monghadi. Ka kakaretso, lengolo la pele la JTAG master ho JTAG ketane e khethoa. Ho khetha mofuta oa JTAG master bakeng sa lisebelisoa tsa Intel Agilex, tsamaisa taelo ena: set_jtag <number of appropriate JTAG monghali>. Example: set_jtag 1.
3. Etsa litaelo tse latelang ho sistimi ea khomphutha ho qala tlhahlobo ea serial loopback:

Letlapa la 7. Li-Parameters tsa Taelo

Paramethara	Tlhaloso	Example Tšebeliso
chkphy_boemo	E bonts'a maqhubu a oache le boemo ba senotlolo sa PHY.	% chkphy_status 0 # Sheba boemo ba sehokelo 0
chkmac_stats	E bonts'a boleng ho li-counters tsa lipalo tsa MAC.	% chkmac_stats 0 # E hlahloba palo ea lipalo-palo tsa mac ea link 0
hlaka_all_stats	E hlakola lisebelisoa tsa lipalo tsa IP tsa mantlha.	% clear_all_stats 0 # E hlakola k'hamphani ea lipalo-palo ea link 0
qala_gen	E qala jenereithara ea pakete.	% start_gen 0 # Qala ho hlahisa liphutheloana ho sehokelo sa 0
emisa_gen	E emisa jenereithara ea pakete.	% stop_gen 0 # Emisa tlhahiso ea lipakete ho sehokelo sa 0
loop_on	E bulela serial loopback ea ka hare.	% loop_on 0 # Bulela loopback e kahare ho sehokelo sa 0
loop_off	E tima "loopback" ea ka hare.	% loop_off 0 # Tima loopback e ka hare ho sehokelo sa 0
reg_bala	E khutlisa boleng ba rejisete ea mantlha ea IP ho .	% reg_read 0x402 # Bala ngoliso ea IP CSR atereseng ea 402 ea sehokelo 0
reg_ngola	E ngola ho aterese ea mantlha ea IP atereseng .	% reg_write 0x401 0x1 # Ngola 0x1 ho IP CSR scratch register atereseng ea 401 ea link 0

a. Tlanya loop_on ho bulela mokgwa wa kahare wa serial loopback.
b. Tlanya chkphy_status ho hlahloba boemo ba PHY. Boemo ba TXCLK, RXCLK, le RX bo lokela ho ba le litekanyetso tse bontšitsoeng ka tlase bakeng sa sehokelo se tsitsitseng:

c. Tlanya clear_all_stats ho hlakola lirekoto tsa lipalo tsa TX le RX.
d. Tlanya start_gen ho qala tlhahiso ea lipakete.
e. Tlanya stop_gen ho emisa tlhahiso ea liphutheloana.
f. Tlanya chkmac_stats ho bala lipalo-palo tsa TX le RX. Etsa bonnete ba hore:
ke. Liforeimi tsa pakete tse fetisoang li ts'oana le liforeimi tse amoheloang tsa pakete.
ii. Ha ho liforeimi tsa liphoso tse amoheloang.
g. Tlanya loop_off ho tima seriele se ka hare.
Setšoantšo sa 7. Sample Test Output-TX le RX Statistics Counters

Nalane ea Phetoho ea Litokomane bakeng sa F-tile 25G Ethernet FPGA IP Design Example Bukana ea Mosebelisi

Tokomane Version	Intel Quartus Prime Version	IP Version	Liphetoho
2022.10.14	22.3	1.0.0	Tokollo ea pele.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO
9001:2015
Ngodisitsoe

Online Version
Romella Maikutlo
ID: 750200
Phetolelo: 2022.10.14

Litokomane / Lisebelisoa

intel F-Tile 25G Ethernet FPGA IP Design Example [pdf] Bukana ea Mosebelisi F-Tile 25G Ethernet FPGA IP Design Example, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Design Example, IP Design Example, 750200

Litšupiso

• Bukana ea Mosebelisi