DisplayPort Agilex F-Tile FPGA IP Dhizaini Example
User Guide
Yakagadziridzwa Intel® Quartus® Prime Dhizaini Suite: 21.4
IP Shanduro: 21.0.0

DisplayPort Intel FPGA IP Dhizaini Exampuye Quick Start Guide

Iyo DisplayPort Intel® FPGA IP dhizaini examples yeIntel Agilex ™ F-tile zvishandiso zvinoratidzira testbench uye dhizaini yehardware inotsigira kuunganidza uye kuyedza Hardware.
Iyo DisplayPort Intel FPGA IP inopa inotevera dhizaini exampzvishoma:

• DisplayPort SST parallel loopback isina Pixel Clock Recovery (PCR) module pa static rate

Kana iwe ukagadzira dhizaini example, iyo parameter editor inogadzira iyo fileinodiwa kutevedzera, kuunganidza, uye kuyedza dhizaini muhardware.
Cherechedza: Intel Quartus® Prime 21.4 software version inotsigira chete Preliminary Design Example yeSimulation, Synthesis, Compilation, uye Nguva yekuongorora zvinangwa. Hardware inoshanda haina kusimbiswa zvizere.
Mufananidzo 1. Budiriro Stages

Related Information

• DisplayPort Intel FPGA IP User Guide
• Kutamira kuIntel Quartus Prime Pro Edition

1.1. Directory Structure
Mufananidzo 2. Dhairekitori Mamiriro

Tafura 1. Dhizaini Example Components

Folders	Files
rtl/core	dp_core.ip
	dp_rx.ip
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX chivakwa chekuvaka)
	dp_rx_data_fifo.ip
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX chivakwa chekuvaka)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Hardware uye Software Zvinodiwa
Intel inoshandisa iyi inotevera Hardware uye software kuyedza iyo dhizaini example:
Hardware

• Intel Agilex I-Series Development Kit

Software

• Intel Quartus Prime
• Synopsy * VCL Simulator

1.3. Kugadzira Dhizaini
Shandisa DisplayPort Intel FPGA IP parameter mupepeti muIntel Quartus Prime software kugadzira dhizaini example.
Mufananidzo 3. Kugadzira Kuyerera Kwekugadzira

1. Sarudza Zvishandiso ➤ IP Catalog, uye sarudza Intel Agilex F-tile semhuri yakanangwa mudziyo.
   Cherechedza: Iyo yakagadzirwa example inongotsigira Intel Agilex F-tile zvishandiso.
2. Mune IP Catalog, tsvaga uye tinya kaviri DisplayPort Intel FPGA IP. The New IP Variation hwindo rinoonekwa.
3. Rondedzera zita repamusoro-soro kune yako tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .ip.
4. Iwe unogona kusarudza chaiyo Intel Agilex F-tile mudziyo mumudziyo weChishandiso, kana chengetedza yakasarudzika Intel Quartus Prime software mudziyo kusarudzwa.
5. Dzvanya OK. Iyo parameter editor inooneka.
6. Gadzirisa maparamita anodiwa ezvose zviri zviviri TX uye RX
7. Pamusoro peDesign Exampuye tab, sarudza DisplayPort SST Parallel Loopback Pasina PCR.
8. Sarudza Simulation kugadzira testbench, uye sarudza Synthesis kugadzira iyo hardware dhizaini example. Iwe unofanirwa kusarudza inokwana imwe yeiyi sarudzo kuti ugadzire iyo dhizaini example files. Kana ukasarudza zvose zviri zviviri, nguva yechizvarwa irefu.
9. Dzvanya Gadzira Example Design.

1.4. Kutevedzera Magadzirirwo
Iyo DisplayPort Intel FPGA IP dhizaini example testbench inoteedzera serial loopback dhizaini kubva kuTX muenzaniso kune RX muenzaniso. Yemukati vhidhiyo pateni jenareta module inotyaira iyo DisplayPort TX muenzaniso uye iyo RX muenzaniso wevhidhiyo inobuda inobatanidza neCRC cheki mu testbench.
Mufananidzo 4. Dhizaini Simulation Flow

1. Enda kuSynopsys simulator folda uye sarudza VCS.
2. Mhanyai simulation script.
   Kunobva vcs_sim.sh
3. Iyo script inoita Quartus TLG, inounganidza uye inomhanyisa testbench mune simulator.
4. Ongorora mhedzisiro.
   Kutevedzera kwakabudirira kunopera neKwakabva uye Sink SRC kuenzanisa.

1.5. Kugadzira uye Kutevedzera Dhizaini
Mufananidzo 5. Kuunganidza uye Kufananidza Dhizaini

Kuunganidza uye kumhanyisa bvunzo yekuratidzira pane Hardware example design, tevera matanho aya:

1. Ita shuwa kuti hardware example design generation yapera.
2. Tangisa iyo Intel Quartus Prime Pro Edition software uye vhura /quartus/agi_dp_demo.qpf.
3. Tinya Kugadzirisa ➤ Tanga Kuunganidza.
4. Mirira kusvika Compilation yapera.

Cherechedza: Iyo yakagadzirwa example haishande inotsigira Preliminary Design Example pane Hardware mukuburitswa kweQuartus.
Related Information
Intel Agilex I-Series FPGA Development Kit User Guide

1.6. DisplayPort Intel FPGA IP Dhizaini Example Parameters
Tafura 2. DisplayPort Intel FPGA IP Dhizaini Exampuye Parameters yeIntel Agilex F-tile Chishandiso

Parameter	Value	Tsanangudzo
Inowanikwa Dhizaini Example
Sarudza Dhizaini	• Hakuna • DisplayPort SST Parallel Loopback pasina PCR	Sarudza dhizaini exampkuti igadzirwe. • Hapana: Hapana dhizaini example inowanikwa kune yazvino parameter kusarudzwa • DisplayPort SST Parallel Loopback isina PCR: Iyi dhizaini example inoratidza parallel loopback kubva kuDisplayPort sink kuenda kuDisplayPort source isina Pixel Clock Recovery (PCR) module paunobatidza Inogonesa Vhidhiyo Yekupinza Image Port parameter.
Design Example Files
Simulation	Vhura, Bvisa	Batidza iyi sarudzo kuti uite zvinodiwa files yekufananidza testbench.
Synthesis	Vhura, Bvisa	Batidza iyi sarudzo kuti uite zvinodiwa files yeIntel Quartus Prime kuunganidza uye hardware dhizaini.
Yakagadzirwa HDL Format
Gadzira File Format	Verilog, VHDL	Sarudza yako yaunofarira HDL fomati yeyakagadzirwa dhizaini example fileset. Cherechedza: Iyi sarudzo inongotarisa iyo fomati yeiyo yakagadzirwa yepamusoro level IP files. Zvimwe zvese files (semuenzanisoample testbenches uye yepamusoro-soro files yekuratidzira kwehardware) ari muVerilog HDL fomati.
Target Development Kit
Sarudza Bhodhi	• Hapana Development Kit • Intel Agilex I-Series Development Kit	Sarudza bhodhi yezvakanangwa dhizaini example. • No Development Kit: Iyi sarudzo haisanganisi zvinhu zvese zvehardware zvedesign example. Iyo IP musimboti inoseta ese mapini ekupa kune chaiwo mapini. • Intel Agilex I-Series FPGA Development Kit: Iyi sarudzo inosarudza otomatiki mudziyo wakanangana nepurojekiti kuti uenderane nemudziyo uri pane ino yekuvandudza kit. Unogona kushandura mudziyo waunonongedza uchishandisa Shandura Target Chidimbu paramende kana yako bhodhi redhiyo ine akasiyana mudziyo musiyano. Iyo IP musimboti inoseta ese pini migove zvinoenderana nebudiriro kit. Cherechedza: Preliminary Design Example haina kushanda yakasimbiswa pane Hardware mukuburitswa kweQuartus. • Custom Development Kit: Iyi sarudzo inobvumira dhizaini example yekuedzwa pane yechitatu-bato rekuvandudza kit ine Intel FPGA. Ungangoda kuseta mapini ekuita uri wega.
	Target Device
Shandura Chinangwa Chishandiso	Vhura, Bvisa	Batidza iyi sarudzo uye sarudza yaunofarira mudziyo musiyano weti yekuvandudza.

Parallel Loopback Dhizaini Examples

Iyo DisplayPort Intel FPGA IP dhizaini examples kuratidza parallel loopback kubva kuDisplayPort RX muenzaniso kuenda kuDisplayPort TX muenzaniso pasina Pixel Clock Recovery (PCR) module pa static rate.
Tafura 3. DisplayPort Intel FPGA IP Dhizaini Example yeIntel Agilex F-tile Chishandiso

Design Example	Designation	Data Rate	Chiteshi Mamiriro	Loopback Type
DisplayPort SST parallel loopback isina PCR	DisplayPort SST	HBR3	Simplex	Parallel pasina PCR

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Dhizaini Zvimiro
Iyo SST yakafanana loopback dhizaini exampzvinotaridza kutapurirana kwevhidhiyo imwe chete kubva kuDisplayPort kunyura kuenda kuDisplayPort sosi isina Pixel Clock Recovery (PCR) pamwero wakamira.

Mufananidzo 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback pasina PCR

• Mukusiyana uku, DisplayPort source parameter, TX_SUPPORT_IM_ENABLE, inobatidzwa uye mufananidzo wevhidhiyo unoshandiswa.
• Iyo DisplayPort sink inogashira vhidhiyo uye kana odhiyo kutenderera kubva kunze kwevhidhiyo sosi seGPU uye inoigadzirisa kuita yakafanana vhidhiyo interface.
• Iyo DisplayPort inonyura vhidhiyo inobuda inotyaira yakananga DisplayPort sosi vhidhiyo interface uye encodes kuDisplayPort main link isati yaendesa kumonitor.
• Iyo IOPLL inotyaira ese ari maviri DisplayPort kunyura uye sosi vhidhiyo wachi pane yakatarwa frequency.
• Kana DisplayPort singi uye kwakabva MAX_LINK_RATE parameter ikagadziridzwa kuita HBR3 uye PIXELS_PER_CLOCK ikagadziridzwa kuita Quad, wachi yevhidhiyo inomhanya pa300 MHz kuti itsigire 8Kp30 pixel rate (1188/4 = 297 MHz).

2.2. Clock Scheme
Chirongwa chewachi chinoratidza madomasi ewachi muDisplayPort Intel FPGA IP dhizaini example.
Mufananidzo 7. Intel Agilex F-tile DisplayPort Transceiver clocking scheme

Tafura 4. Kuvhara Scheme Zviratidzo

Wachi mudhayagiramu	Tsanangudzo
SysPLL refclk	F-tile System PLL referensi wachi inogona kuve chero frequency yewachi iyo inopatsanurika neSystem PLL yeiyo inobuda frequency. Muchirongwa ichi example, system_pll_clk_link uye rx/tx refclk_link iri kugovera zvakafanana SysPLL refclk iyo iri 150Mhz. Inofanira kunge iri wachi yemahara inomhanya iyo yakabatana kubva kune yakatsaurirwa transceiver referensi wachi yepini kuenda kune yekuisa wachi chiteshi cheReference uye System PLL Clocks IP, usati wabatanidza inoenderana inobuda chiteshi kuDisplayPort Phy Pamusoro.
system_pll_clk_link	Iyo yakaderera System PLL yekubuda frequency kutsigira ese DisplayPort chiyero ndeye 320Mhz. Iyi dhizaini example inoshandisa 900 Mhz (yepamusoro) inobuda frequency kuitira kuti SysPLL refclk igovane ne rx/tx refclk_link inova 150 Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	Rx CDR uye Tx PLL Link refclk iyo yakatarwa ku150 Mhz kutsigira ese DisplayPort data rate.
rx_ls_clkout/tx Is clkout	DisplayPort Link Yekumhanyisa Clock kune wachi DisplayPort IP musimboti. Frequency yakaenzana neData Rate patsanura neparallel data wide. Example: Frequency = chiyero che data / upamhi hwedata = 8.1G (HBR3) / 40bits = 202.5 Mhz

2.3. Simulation Testbench
Iyo simulation testbench inoteedzera iyo DisplayPort TX serial loopback kuRX.
Mufananidzo 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block Diagram

Tafura 5. Testbench Zvikamu

Chikamu	Tsanangudzo
Vhidhiyo Pattern Generator	Jenareta iyi inogadzira mapatani emabhawa emavara aunogona kugadzirisa. Iwe unogona parameterize vhidhiyo fomati nguva.
Testbench Control	Iri bhuroka rinotonga kutevedzana kwekuyedza kweyekufananidza uye rinogadzira masaini anodiwa ekusimudzira kune iyo TX musimboti. Iyo testbench control block inoverengawo kukosha kweCRC kubva kune zvese sosi uye kunyura kuita kuenzanisa.
RX Link Speed ​​​​Clock Frequency Checker	Iyi yekutarisa inosimbisa kana iyo RX transceiver yakadzoreredza wachi frequency ichienderana neinodiwa data data.
TX Link Speed ​​​​Clock Frequency Checker	Iyi yekutarisa inoongorora kana iyo TX transceiver yakadzoreredza wachi frequency ichienderana neinodiwa data data.

Iyo simulation testbench inoita zvinotevera ongororo:
Tafura 6. Testbench Verifications

Test Criteria	Verification
• Batanidza Kudzidziswa paData Rate HBR3 • Verenga marejista eDPCD kuti uone kana DP Status yakaseta uye inoyera zvese zviri zviviri TX neRX Link Speed ​​frequency.	Inobatanidza Frequency Checker kuyera iyo Link Speed ​​​​wachi frequency kubuda kubva kuTX uye RX transceiver.
• Mhanya vhidhiyo muenzaniso kubva TX kusvika RX. • Ongorora CRC kune zvose kwakabva uye sink kuti uone kana zvinoenderana	• Inobatanidza jenareta yevhidhiyo kuDisplayPort Source kuti ibudise pateni yevhidhiyo. • Testbench control inotevera inoverenga zvese Source uye Sink CRC kubva kuDPTX uye DPRX marejista uye kuenzanisa kuti ive nechokwadi chekuti ese CRC tsika dzakafanana. Cherechedza: Kuti uone kuti CRC yakaverengerwa, unofanirwa kugonesa Tsigiro yeCTS bvunzo otomatiki parameter.

Gwaro Revision Nhoroondo yeDisplayPort Intel

Agilex F-tile FPGA IP Dhizaini Example User Guide

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2021.12.13	21.4	21.0.0	Kusunungurwa kwekutanga.

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UG-20347
ID: 709308
Shanduro: 2021.12.13

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Intel DisplayPort Agilex F-Tile FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi DisplayPort Agilex F-Tile FPGA IP Dhizaini Example, DisplayPort Agilex, F-Tile FPGA IP Dhizaini Example, F-Tile FPGA IP Dhizaini, FPGA IP Dhizaini Example, IP Dhizaini Example, IP Dhizaini, UG-20347, 709308

References

• User Manual