F-Tile DisplayPort FPGA IP Dhizaini Example
User Guide

F-Tile DisplayPort FPGA IP Dhizaini Example

Yakagadziridzwa yeIntel® Quartus® Prime Design Suite: 22.2 IP Version: 21.0.1

DisplayPort Intel FPGA IP Dhizaini Exampuye Quick Start Guide

Iyo DisplayPort Intel® F-tile zvishandiso inoratidzira yekufananidza testbench uye dhizaini yehardware inotsigira kuunganidzwa uye kuyedza hardware FPGA IP dhizaini ex.ampzvimwe zveIntel Agilex™
Iyo DisplayPort Intel FPGA IP inopa inotevera dhizaini exampzvishoma:

• DisplayPort SST parallel loopback isina Pixel Clock Recovery (PCR) module
• DisplayPort SST parallel loopback neAXIS Vhidhiyo Interface

Kana iwe ukagadzira dhizaini example, iyo parameter editor inogadzira iyo fileinodiwa kutevedzera, kuunganidza, uye kuyedza dhizaini muhardware.
Mufananidzo 1. Budiriro StagesRelated Information

• DisplayPort Intel FPGA IP User Guide
• Kutamira kuIntel Quartus Prime Pro Edition

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
*Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.
ISO 9001:2015 Yakanyoreswa
1.1. Directory Structure
Mufananidzo 2. Dhairekitori Mamiriro

Tafura 1. Dhizaini Example Components

Folders	Files
rtl/core	dp_core.ip
	dp_rx . ip
	dp_tx . ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX chivakwa chekuvaka)
	dp_rx_data_fifo . ip
	rx_top_phy . sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX chivakwa chekuvaka)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Hardware uye Software Zvinodiwa
Intel inoshandisa iyi inotevera Hardware uye software kuyedza iyo dhizaini example:
Hardware

• Intel Agilex I-Series Development Kit
• DisplayPort Source GPU
• DisplayPort Sink (Monitor)
• Bitec DisplayPort FMC mwanasikana kadhi Revision 8C
• DisplayPort tambo

Software

• Intel Quartus® Prime
• Synopsy * VCS Simulator

1.3. Kugadzira Dhizaini
Shandisa DisplayPort Intel FPGA IP parameter mupepeti muIntel Quartus Prime software kugadzira dhizaini example.
Mufananidzo 3. Kugadzira Kuyerera Kwekugadzira

1.  Sarudza Zvishandiso ➤ IP Catalog, uye sarudza Intel Agilex F-tile semhuri yakanangwa mudziyo.
   Cherechedza: Iyo yakagadzirwa example inongotsigira Intel Agilex F-tile zvishandiso.
2. Mune IP Catalog, tsvaga uye tinya kaviri DisplayPort Intel FPGA IP. The New IP Variation hwindo rinoonekwa.
3. Rondedzera zita repamusoro-soro kune yako tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .ip.
4. Sarudza Intel Agilex F-tile mudziyo mumudziyo weChishandiso, kana chengeta yakasarudzika Intel Quartus Prime software mudziyo kusarudzwa.
5. Dzvanya OK. Iyo parameter editor inooneka.
6. Gadzirisa maparamita anodiwa ezvose zviri zviviri TX uye RX.
7. Pasi peDesign Exampuye tab, sarudza DisplayPort SST Parallel Loopback Pasina PCR.
8. Sarudza Simulation kugadzira testbench, uye sarudza Synthesis kugadzira iyo hardware dhizaini example. Iwe unofanirwa kusarudza inokwana imwe yeiyi sarudzo kuti ugadzire iyo dhizaini example files. Kana ukasarudza zvose, nguva yechizvarwa inova yakareba.
9. YeTarget Development Kit, sarudza Intel Agilex I-Series SOC Development Kit. Izvi zvinokonzeresa kuti chinonangwa mudziyo wakasarudzwa mudanho rechina kuti uchinje kuti uenderane nemudziyo uri pakiti yekuvandudza. YeIntel Agilex I-Series SOC Development Kit, mudziyo wakasarudzika ndeye AGIB4R027B31E1VR2.
10. Dzvanya Gadzira Example Design.

1.4. Kutevedzera Magadzirirwo
Iyo DisplayPort Intel FPGA IP dhizaini example testbench inoteedzera serial loopback dhizaini kubva kuTX muenzaniso kune RX muenzaniso. Yemukati vhidhiyo pateni jenareta module inotyaira iyo DisplayPort TX muenzaniso uye iyo RX muenzaniso wevhidhiyo inobuda inobatanidza neCRC cheki mu testbench.
Mufananidzo 4. Dhizaini Simulation Flow

1. Enda kuSynopsys simulator folda uye sarudza VCS.
2. Mhanyai simulation script.
   Kunobva vcs_sim.sh
3. Iyo script inoita Quartus TLG, inounganidza uye inomhanyisa testbench mune simulator.
4. Ongorora mhedzisiro.
   Kutevedzera kwakabudirira kunopera neKwakabva uye Sink SRC kuenzanisa.

1.5. Kunyora uye Kuedza Dhizaini
Mufananidzo 5. Kuunganidza uye Kufananidza DhizainiKuunganidza uye kumhanyisa bvunzo yekuratidzira pane Hardware example design, tevera matanho aya:

1. Ita shuwa kuti hardware example design generation yapera.
2. Tangisa iyo Intel Quartus Prime Pro Edition software uye vhura / quartus/agi_dp_demo.qpf.
3. Tinya Kugadzirisa ➤ Tanga Kuunganidza.
4. Mushure mekubudirira kuunganidza, software yeIntel Quartus Prime Pro Edition inogadzira .sof file mudhairekitori rako rawakataura.
5. Batanidza iyo DisplayPort RX yekubatanidza paBitec mwanasikana kadhi kune yekunze DisplayPort sosi, senge kadhi remifananidzo paPC.
6. Batanidza DisplayPort TX yekubatanidza pane Bitec mwanasikana kadhi kune DisplayPort sink mudziyo, senge vhidhiyo analyzer kana PC yekutarisa.
7.  Ita shuwa kuti zvese zvinochinja pabhodhi rekuvandudza zviri munzvimbo yekusarudzika.
8. Rongedza yakasarudzwa Intel Agilex F-Tile mudziyo pabhodhi rekuvandudza uchishandisa yakagadzirwa .sof file (Zvishandiso ➤ Mugadziri).
9. Iyo DisplayPort sink mudziyo unoratidza vhidhiyo inogadzirwa kubva kune vhidhiyo sosi.

Related Information
Intel Agilex I-Series FPGA Development Kit User Guide/
1.5.1. Kuvandudza ELF File
Nekusagadzikana, iyo ELF file inogadzirwa kana iwe uchigadzira iyo inoshanduka dhizaini example.
Nekudaro, mune dzimwe nguva, iwe unofanirwa kuvandudza iyo ELF file kana iwe ukagadzirisa software file kana gadzira patsva dp_core.qsys file. Kugadzira patsva dp_core.qsys file inovandudza .sopcinfo file, izvo zvinoda kuti udzorezve ELF file.

1. Enda ku / software uye gadzirisa kodhi kana zvichidikanwa.
2. Enda ku /script uye ita inotevera kuvaka script: sosi build_sw.sh
   • PaWindows, tsvaga uye vhura Nios II Command Shell. MuNios II Command Shell, enda ku /script uye ita sosi build_sw.sh.
   Cherechedza: Kuti uite kuvaka script pa Windows 10, yako system inoda Windows Subsystems yeLinux (WSL). Kuti uwane rumwe ruzivo nezve WSL yekuisa matanho, tarisa kuNios II Software Developer Handbook.
   • PaLinux, vhura Platform Designer, uye vhura Zvishandiso ➤ Nios II Raira Shell. MuNios II Command Shell, enda ku /script uye ita sosi build_sw.sh.
3. Iva nechokwadi chekuti .elf file inogadzirwa mu /software/ dp_demo.
4. Dhaunirodha yakagadzirwa .elf file kupinda muFPGA pasina kudzorera .sof file nekumhanyisa script inotevera: nios2-download /software/dp_demo/*.elf
5. Dzvanya bhatani reset paFPGA board kuti software itsva iite.

1.6. DisplayPort Intel FPGA IP Dhizaini Example Parameters
Tafura 2. DisplayPort Intel FPGA IP Dhizaini Exampuye QSF inomanikidza yeIntel Agilex Ftile Chishandiso

QSF Constraint	Tsanangudzo
set_global_assignment -zita VERILOG_MACRO “__DISPLAYPORT_rutsigiro__=1”	Kubva paQuartus 22.2 zvichienda mberi, ichi chinomanikidza cheQSF chinodiwa kugonesa DisplayPort tsika SRC (Soft Reset Controller) kuyerera.

Tafura 3. DisplayPort Intel FPGA IP Dhizaini Exampuye Parameters yeIntel Agilex F-tile Chishandiso

Parameter	Value	Tsanangudzo
Inowanikwa Dhizaini Example
Sarudza Dhizaini	•Hapana •DisplayPort SST Parallel Loopback isina PCR •DisplayPort SST Parallel Loopback ine AXIS Vhidhiyo Interface	Sarudza dhizaini exampkuti igadzirwe. •Hapana: Hapana dhizaini example inowanikwa kune yazvino parameter kusarudzwa. •DisplayPort SST Parallel Loopback isina PCR: Iyi dhizaini example inoratidza parallel loopback kubva kuDisplayPort sink kuenda kuDisplayPort source isina Pixel Clock Recovery (PCR) module paunobatidza Inogonesa Vhidhiyo Yekupinza Image Port parameter. •DisplayPort SST Parallel Loopback ine AXIS Vhidhiyo Interface: Iyi dhizaini example inoratidza parallel loopback kubva kuDisplayPort kunyura kuenda kuDisplayPort sosi ine AXIS Vhidhiyo interface apo Inogonesa Active Vhidhiyo Data Protocols yakaiswa kuAXIS-VVP Yakazara.
Design Example Files
Simulation	Vhura, Bvisa	Batidza iyi sarudzo kuti uite zvinodiwa files yekufananidza testbench.
Synthesis	Vhura, Bvisa	Batidza iyi sarudzo kuti uite zvinodiwa files yeIntel Quartus Prime kuunganidza uye hardware dhizaini.
Yakagadzirwa HDL Format
Gadzira File Format	Verilog, VHDL	Sarudza yako yaunofarira HDL fomati yeyakagadzirwa dhizaini example fileset. Ongorora: Iyi sarudzo inongotarisa iyo fomati yeiyo yakagadzirwa yepamusoro level IP files. Zvimwe zvese files (semuenzanisoample testbenches uye yepamusoro-soro files yekuratidzira kwehardware) ari muVerilog HDL fomati.
Target Development Kit
Sarudza Bhodhi	•Hapana Development Kit •Intel Agilex I-Series Development Kit	Sarudza bhodhi yezvakanangwa dhizaini example.

Parameter	Value	Tsanangudzo
		•No Development Kit: Iyi sarudzo haisanganisi zvinhu zvese zvehardware zvedesign example. Iyo P musimboti inoseta ese mapini ekupa kune chaiwo mapini. •Intel Agilex I-Series FPGA Development Kit: Iyi sarudzo inosarudza yega mudziyo wakanangana neprojekiti kuti uenderane nemudziyo uri pane ino yekuvandudza kit. Unogona kushandura mudziyo waunonongedza uchishandisa Shandura Target Chidimbu paramende kana yako bhodhi redhiyo ine akasiyana mudziyo musiyano. Iyo IP musimboti inoseta ese pini migove zvinoenderana neiyo yekuvandudza kit. Cherechedza: Preliminary Design Example haina kushanda yakasimbiswa pane Hardware mukuburitswa kweQuartus. •Custom Development Kit: Iyi sarudzo inobvumira dhizaini example yekuedzwa pane yechitatu-bato rekuvandudza kit ine Intel FPGA. Ungangoda kuseta mapini ekuita uri wega.
Target Device
Shandura Chinangwa Chishandiso	Vhura, Bvisa	Batidza iyi sarudzo uye sarudza yaunofarira mudziyo musiyano weti yekuvandudza.

Parallel Loopback Dhizaini Examples

Iyo DisplayPort Intel FPGA IP dhizaini examples ratidza parallel loopback kubva kuDisplayPort RX muenzaniso kuenda kuDisplayPort TX muenzaniso pasina Pixel Clock Recovery (PCR) module.
Tafura 4. DisplayPort Intel FPGA IP Dhizaini Example yeIntel Agilex F-tile Chishandiso

Design Example	Designation	Data Rate	Chiteshi Mamiriro	Loopback Type
DisplayPort SST parallel loopback isina PCR	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Parallel pasina PCR
DisplayPort SST parallel loopback neAXIS Vhidhiyo Interface	DisplayPort SST	RBR, HRB, HRB2, HBR3	Simplex	Parallel neAXIS Vhidhiyo Interface

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Dhizaini Features
Iyo SST yakafanana loopback dhizaini exampzvinotaridza kutapurirana kwevhidhiyo rwizi rwumwechete kubva kuDisplayPort kunyura kuenda kuDisplayPort sosi.
Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.
ISO 9001:2015 Yakanyoreswa
Mufananidzo 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback pasina PCR

• Mukusiyana uku, DisplayPort source parameter, TX_SUPPORT_IM_ENABLE, inobatidzwa uye mufananidzo wevhidhiyo unoshandiswa.
• Iyo DisplayPort sink inogashira vhidhiyo uye kana odhiyo kutenderera kubva kunze kwevhidhiyo sosi seGPU uye inoigadzirisa kuita yakafanana vhidhiyo interface.
• Iyo DisplayPort inonyura vhidhiyo inobuda inotyaira yakananga DisplayPort sosi vhidhiyo interface uye encodes kuDisplayPort main link isati yaendesa kumonitor.
• Iyo IOPLL inotyaira ese ari maviri DisplayPort kunyura uye sosi vhidhiyo wachi pane yakatarwa frequency.
• Kana DisplayPort singi uye kwakabva MAX_LINK_RATE parameter ikagadziridzwa kuita HBR3 uye PIXELS_PER_CLOCK ikagadziridzwa kuita Quad, wachi yevhidhiyo inomhanya pa300 MHz kuti itsigire 8Kp30 pixel rate (1188/4 = 297 MHz).

Mufananidzo 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback neAXIS Vhidhiyo Interface

• Mune iyi musiyano, iyo DisplayPort sosi uye sink parameter, sarudza AXIS-VVP FULL mu ITA KUTI ACTIVE Vhidhiyo DATA PROTOCOLS kugonesa Axis Vhidhiyo Data Interface.
• Iyo DisplayPort sink inogashira vhidhiyo uye kana odhiyo kutenderera kubva kunze kwevhidhiyo sosi seGPU uye inoigadzirisa kuita yakafanana vhidhiyo interface.
• Iyo DisplayPort Sink inoshandura vhidhiyo yedata rwizi kuita axis vhidhiyo data uye inotyaira DisplayPort sosi axis vhidhiyo data interface kuburikidza neVVP Vhidhiyo Frame Buffer. DisplayPort Source inoshandura axis vhidhiyo data kuita DisplayPort main link isati yaendesa kune yekutarisa.
• Mune iyi dhizaini musiyano, kune matatu makuru evhidhiyo wachi, anoti rx/tx_axi4s_clk, rx_vid_clk, uye tx_vid_clk. axi4s_clk inomhanya pa300 MHz kune ese maAXIS modules mu Source uye Sink. rx_vid_clk inomhanyisa DP Sink Vhidhiyo pombi pa300 MHz (kutsigira chero sarudzo inosvika 8Kp30 4PIPs), nepo tx_vid_clk ichimhanyisa DP Source Vhidhiyo pombi pane chaiyo Pixel Clock frequency (yakakamurwa nePIPs).
• Iyi dhizaini yakasiyana-siyana inogadzirisa tx_vid_clk frequency kuburikidza neI2C hurongwa kune-bhodhi SI5391B OSC kana dhizaini yaona switch mukugadziriswa.
• Musiyano wedhizaini uyu unongoratidza nhamba yakatarwa yezvisarudzo sezvakatsanangurwa muDisplayPort software, zvinoti:
  — 720p60, RGB
  — 1080p60, RGB
  — 4K30, RGB
  — 4K60, RGB

2.2. Clock Scheme
Chirongwa chewachi chinoratidza madomasi ewachi muDisplayPort Intel FPGA IP dhizaini example.
Mufananidzo 8. Intel Agilex F-tile DisplayPort Transceiver clocking schemeTafura 5. Kuvhara Scheme Zviratidzo

Wachi mudhayagiramu	Tsanangudzo
SysPLL refclk	F-tile System PLL referensi wachi inogona kuve chero frequency yewachi iyo inopatsanurika neSystem PLL yeiyo inobuda frequency. Muchirongwa ichi example, system_pll_clk_link uye rx/tx refclk_link inogovera zvakafanana 150 MHz SysPLL refclk.

Wachi mudhayagiramu	Tsanangudzo
	Inofanira kunge iri wachi yemahara inomhanya iyo yakabatana kubva kune yakatsaurirwa transceiver referensi wachi yepini kuenda kune yekuisa wachi chiteshi cheReference uye System PLL Clocks IP, usati wabatanidza inoenderana inobuda chiteshi kuDisplayPort Phy Pamusoro. Cherechedza: Kune iyi dhizaini example, gadzirisa Clock Controller GUI Si5391A OUT6 kusvika 150 MHz.
system pll clk link	Iyo yakaderera System PLL yekubuda frequency kutsigira ese DisplayPort chiyero ndeye 320 MHz. Iyi dhizaini example inoshandisa 900 MHz (yepamusoro) inobuda frequency kuitira kuti SysPLL refclk igovane ne rx/tx refclk_link inova 150 MHz.
rx_cdr_refclk_link / tx_pll_refclk_link	Rx CDR uye Tx PLL Link refclk iyo yakatarwa ku150 MHz kutsigira ese DisplayPort data rate.
rx_ls_clkout / tx_ls_clkout	DisplayPort Link Yekumhanyisa Clock kune wachi DisplayPort IP musimboti. Frequency yakaenzana neData Rate patsanura neparallel data wide. Example: Frequency = chiyero che data / upamhi hwe data = 8.1G (HBR3) / 40 bits = 202.5 MHz

2.3. Simulation Testbench
Iyo simulation testbench inoteedzera iyo DisplayPort TX serial loopback kuRX.
Mufananidzo 9. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block DiagramTafura 6. Testbench Zvikamu

Chikamu	Tsanangudzo
Vhidhiyo Pattern Generator	Jenareta iyi inogadzira mapatani emabhawa emavara aunogona kugadzirisa. Iwe unogona parameterize vhidhiyo fomati nguva.
Testbench Control	Iri bhuroka rinotonga kutevedzana kwekuyedza kweyekufananidza uye rinogadzira masaini anodiwa ekusimudzira kune iyo TX musimboti. Iyo testbench control block inoverengawo kukosha kweCRC kubva kune zvese sosi uye kunyura kuita kuenzanisa.
RX Link Speed ​​​​Clock Frequency Checker	Iyi yekutarisa inosimbisa kana iyo RX transceiver yakadzoreredza wachi frequency ichienderana neinodiwa data data.
TX Link Speed ​​​​Clock Frequency Checker	Iyi yekutarisa inoongorora kana iyo TX transceiver yakadzoreredza wachi frequency ichienderana neinodiwa data data.

Iyo simulation testbench inoita zvinotevera ongororo:
Tafura 7. Testbench Verifications

Test Criteria	Verification
• Batanidza Kudzidziswa paData Rate HBR3 • Verenga marejista eDPCD kuti uone kana DP Status yakaseta uye inoyera zvese zviri zviviri TX neRX Link Speed ​​frequency.	Inobatanidza Frequency Checker kuyera iyo Link Speed wachi yekubuda kwewachi kubva kuTX uye RX transceiver.
• Mhanya vhidhiyo muenzaniso kubva TX kusvika RX. • Ongorora CRC kune zvose kwakabva uye sink kuti uone kana zvinoenderana	• Inobatanidza jenareta yevhidhiyo kuDisplayPort Source kuti ibudise pateni yevhidhiyo. • Testbench control inotevera inoverenga zvese Source uye Sink CRC kubva kuDPTX uye DPRX marejista uye kuenzanisa kuti ive nechokwadi chekuti ese CRC tsika dzakafanana. Ongorora: Kuti uone kuti CRC yakaverengerwa, unofanirwa kugonesa iyo Tsigiro CTS bvunzo otomatiki parameter.

Gwaro Rekudzokorora Nhoroondo yeF-Tile DisplayPort Intel FPGA IP Dhizaini Example User Guide

Document Version	Intel Quartus Prime Version	IP Version	Kuchinja
2022.09.02	22.	20.0.1	•Yachinjwa zita regwaro kubva kuDisplayPort Intel Agilex F-Tile FPGA IP Dhizaini Exampuye Mushandisi Yekushandisa kuF-Tile DisplayPort Intel FPGA IP Dhizaini Example User Guide. •Yakagonesa AXIS Vhidhiyo Dhizaini Example variant. • Yakabviswa Static Rate dhizaini ndokuitsiva neMulti Rate Dhizaini Example. • Yakabvisa chinyorwa muDisplayPort Intel FPGA IP Dhizaini Example Quick Start Guide inoti Intel Quartus Prime 21.4 software version inotsigira chete Preliminary Design Examples. •Yakatsiva iyo Directory Structure figure nenhamba chaiyo. •Yakawedzera chikamu Kugadzirazve ELF File pasi peKunyora uye Kuedza Dhizaini. •Vakamutsiridza chikamu cheHardware neSoftware Requirements kuti chisanganise zvimwe zvinhu zvinodiwa.
2021.12.13	21.	20.0.0	Kusunungurwa kwekutanga.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.
*Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.
ISO 9001:2015 Yakanyoreswa

Online Version
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UG-20347
ID: 709308
Shanduro: 2022.09.02

Zvinyorwa / Zvishandiso

Intel F-Tile DisplayPort FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi F-Tile DisplayPort FPGA IP Dhizaini Example, F-Tile DisplayPort, DisplayPort, FPGA IP Dhizaini Example, IP Dhizaini Example, UG-20347, 709308

References

• User Manual