DisplayPort Agilex F-Tile FPGA IP Design Example
Itọsọna olumulo
Imudojuiwọn fun Intel® Quartus® Prime Design Suite: 21.4
Ẹya IP: 21.0.0

DisplayPort Intel FPGA IP Design Example Quick Bẹrẹ Itọsọna

DisplayPort Intel® FPGA IP apẹrẹamples fun Intel Agilex ™ F-tile awọn ẹrọ ṣe ẹya simulating testbench ati apẹrẹ ohun elo kan ti o ṣe atilẹyin iṣakojọpọ ati idanwo ohun elo.
DisplayPort Intel FPGA IP nfunni ni apẹrẹ atẹleample:

• DisplayPort SST parallel loopback laisi module Aago Pixel Ìgbàpadà (PCR) ni oṣuwọn aimi

Nigba ti o ba se ina kan oniru example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe simulate, ṣajọ, ati idanwo apẹrẹ ni hardware.
Akiyesi: Ẹya sọfitiwia Intel Quartus® Prime 21.4 nikan ṣe atilẹyin Apẹrẹ Alakoko Example fun Simulation, Synthesis, Compilation, and Time analysis ìdí. Iṣẹ ṣiṣe Hardware ko ni ijẹrisi ni kikun.
Nọmba 1. Idagbasoke Stages

Alaye ti o jọmọ

• DisplayPort Intel FPGA IP Itọsọna olumulo
• Iṣilọ si Intel Quartus Prime Pro Edition

1.1. Ilana Ilana
olusin 2. Directory Be

Table 1. Design Example irinše

Awọn folda	Files
rtl/mojuto	dp_core.ip
	dp_rx.ip
	dp_tx.ip
rtl/rx_phy	dp_gxb_rx/ ((DP PMA UX ile idina)
	dp_rx_data_fifo.ip
	rx_top_phy.sv
rtl/tx_phy	dp_gxb_rx/ ((DP PMA UX ile idina)
	dp_tx_data_fifo.ip
	dp_tx_data_fifo.ip

1.2. Hardware ati Software Awọn ibeere
Intel nlo awọn wọnyi hardware ati software lati se idanwo awọn oniru example:
Hardware

• Intel Agilex I-Series Development Kit

Software

• Intel kuotisi NOMBA
• Synopsys * VCL Simulator

1.3. Ti o npese awọn Design
Lo olootu paramita IP DisplayPort Intel FPGA ni sọfitiwia Intel Quartus Prime lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample.
olusin 3. Ti o npese awọn Design sisan

1. Yan Awọn irinṣẹ ➤ IP Catalog, ki o si yan Intel Agilex F-tile bi idile ẹrọ afojusun.
   Akiyesi: Apẹrẹ example nikan atilẹyin Intel Agilex F-tile awọn ẹrọ.
2. Ninu Katalogi IP, wa ati tẹ-lẹẹmeji DisplayPort Intel FPGA IP. Ferese Iyipada IP Tuntun yoo han.
3. Pato orukọ ipele-oke fun iyatọ IP aṣa rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip.
4. O le yan ẹrọ Intel Agilex F-tile kan pato ni aaye Ẹrọ, tabi tọju yiyan ẹrọ sọfitiwia Intel Quartus Prime aiyipada.
5. Tẹ O DARA. Olootu paramita yoo han.
6. Tunto awọn paramita ti o fẹ fun mejeeji TX ati RX
7. Lori apẹrẹ Examptaabu, yan DisplayPort SST Parallel Loopback Laisi PCR.
8. Yan Simulation lati se ina testbench, ki o si yan Synthesis lati se ina awọn hardware oniru example. O gbọdọ yan o kere ju ọkan ninu awọn aṣayan wọnyi lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample files. Ti o ba yan awọn mejeeji, akoko iran naa gun.
9. Tẹ ina Example Design.

1.4. Simulating awọn Design
DisplayPort Intel FPGA IP apẹrẹ example testbench ṣe apẹẹrẹ apẹrẹ loopback ni tẹlentẹle lati apẹẹrẹ TX si apẹẹrẹ RX kan. Module olupilẹṣẹ apẹẹrẹ fidio ti inu wakọ apẹẹrẹ DisplayPort TX ati iṣelọpọ fidio apẹẹrẹ RX sopọ si awọn oluyẹwo CRC ni testbench.
olusin 4. Ṣiṣan Simulation Design

1. Lọ si folda Simulator Synopsys ko si yan VCS.
2. Ṣiṣe akosile kikopa.
   Orisun vcs_sim.sh
3. Iwe afọwọkọ naa n ṣe Quartus TLG, ṣe akopọ ati ṣiṣe testbench ni simulator.
4. Ṣe itupalẹ abajade.
   Simulation aṣeyọri pari pẹlu Orisun ati afiwe SRC Sink.

1.5. Iṣakojọpọ ati Simulating Apẹrẹ
Ṣe nọmba 5. Ṣiṣepọ ati Simulating Apẹrẹ

Lati ṣajọ ati ṣiṣe idanwo ifihan lori hardware exampFun apẹrẹ, tẹle awọn igbesẹ wọnyi:

1. Rii daju hardware example oniru iran jẹ pari.
2. Lọlẹ Intel Quartus Prime Pro Edition sọfitiwia ati ṣii /quartus/agi_dp_demo.qpf.
3. Tẹ Ṣiṣeto ➤ Bẹrẹ Iṣakojọpọ.
4. Duro titi Akopọ yoo pari.

Akiyesi: Apẹrẹ example ko ni iṣẹ-ṣiṣe mọ daju Alakoko Design Example lori ohun elo ni idasilẹ Quartus yii.
Alaye ti o jọmọ
Intel Agilex I-Series FPGA Development Apo olumulo Itọsọna

1.6. DisplayPort Intel FPGA IP Design Example Parameters
Table 2. DisplayPort Intel FPGA IP Design Eksample Parameters fun Intel Agilex F-tile Device

Paramita	Iye	Apejuwe
Apẹrẹ ti o wa Example
Yan Oniru	• Ko si • DisplayPort SST Parallel Loopback laisi PCR	Yan apẹrẹ example lati wa ni ipilẹṣẹ. • Ko si: Ko si oniru example wa fun yiyan paramita lọwọlọwọ • DisplayPort SST Parallel Loopback laisi PCR: Apẹrẹ yii example ṣe afihan loopback ti o jọra lati ifọwọ DisplayPort si orisun DisplayPort laisi module Aago Pixel Ìgbàpadà (PCR) nigbati o ba tan-an Jeki paramita Port Aworan Input Fidio ṣiṣẹ.
Apẹrẹ Example Files
Afọwọṣe	Tan, paa	Tan aṣayan yii lati ṣe ina pataki files fun testbench kikopa.
Akopọ	Tan, paa	Tan aṣayan yii lati ṣe ina pataki files fun Intel Quartus Prime akopo ati hardware design.
Ti ipilẹṣẹ HDL kika
Ṣẹda File Ọna kika	Verilog, VHDL	Yan ọna kika HDL ti o fẹ fun apẹrẹ ti ipilẹṣẹ example fileṣeto. Akiyesi: Aṣayan yii nikan pinnu ọna kika fun ipilẹṣẹ IP ipele oke files. Gbogbo miiran files (fun apẹẹrẹample testbenches ati oke ipele files fun ifihan ohun elo) wa ni ọna kika Verilog HDL.
Àkọlé Development Kit
Yan Board	• Ko si Apo Idagbasoke • Intel Agilex I-Series Idagbasoke Apo	Yan igbimọ fun apẹrẹ ìfọkànsí example. Ko si Apo Idagbasoke: Aṣayan yii yọkuro gbogbo awọn aaye ohun elo fun apẹrẹ apẹẹrẹample. Ipilẹ ipilẹ IP ṣeto gbogbo awọn iṣẹ iyansilẹ pin si awọn pinni foju. • Intel Agilex I-Series FPGA Development Kit: Aṣayan yii laifọwọyi yan ẹrọ ibi-afẹde ti iṣẹ akanṣe lati baamu ẹrọ naa lori ohun elo idagbasoke yii. O le yi ẹrọ ibi-afẹde pada nipa lilo paramita Ẹrọ Iyipada Iyipada ti atunyẹwo igbimọ rẹ ba ni iyatọ ẹrọ ti o yatọ. Ipilẹ IP ṣeto gbogbo awọn iṣẹ iyansilẹ pin ni ibamu si ohun elo idagbasoke. Akiyesi: Apẹrẹ alakoko Example ko ni iṣeduro iṣẹ ṣiṣe lori ohun elo ni idasilẹ Quartus yii. • Aṣa Development Apo: Eleyi aṣayan faye gba awọn oniru example ṣe idanwo lori ohun elo idagbasoke ẹni-kẹta pẹlu Intel FPGA kan. O le nilo lati ṣeto awọn iṣẹ iyansilẹ pin lori tirẹ.
	Àkọlé Device
Yi Àkọlé Device	Tan, paa	Tan aṣayan yii ki o yan iyatọ ẹrọ ti o fẹ fun ohun elo idagbasoke.

Apẹrẹ Loopback Ti o jọra Eksamples

DisplayPort Intel FPGA IP apẹrẹ examples ṣe afihan loopback ti o jọra lati apẹẹrẹ DisplayPort RX si apẹẹrẹ DisplayPort TX laisi module Aago Pixel Ìgbàpadà (PCR) ni oṣuwọn aimi.
Table 3. DisplayPort Intel FPGA IP Design Eksample fun Intel Agilex F-tile Device

Apẹrẹ Example	Orúkọ	Data Oṣuwọn	Ipo Ikanni	Loopback Iru
DisplayPort SST ni afiwe loopback lai PCR	DisplayPort SST	HBR3	Simplex	Ni afiwe laisi PCR

2.1. Intel Agilex F-tile DisplayPort SST Parallel Loopback Design Awọn ẹya ara ẹrọ
The SST ni afiwe loopback oniru examples ṣe afihan gbigbe ti ṣiṣan fidio kan lati DisplayPort rii si orisun DisplayPort laisi Pixel Clock Recovery (PCR) ni oṣuwọn aimi.

olusin 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback lai PCR

• Ninu iyatọ yii, paramita orisun DisplayPort, TX_SUPPORT_IM_ENABLE, wa ni titan ati wiwo aworan fidio ti lo.
• Awọn ifọwọ DisplayPort gba fidio ati tabi ṣiṣan ohun lati orisun fidio ita gẹgẹbi GPU ati ṣe ipinnu rẹ sinu wiwo fidio ti o jọra.
• Ijade fidio ti DisplayPort rii taara taara ni wiwo fidio orisun DisplayPort ati awọn koodu si ọna asopọ akọkọ DisplayPort ṣaaju gbigbe si atẹle naa.
• IOPLL n ṣe awakọ mejeeji ifọwọ DisplayPort ati awọn aago fidio orisun ni igbohunsafẹfẹ ti o wa titi.
• Ti DisplayPort rii ati paramita MAX_LINK_RATE orisun ti wa ni tunto si HBR3 ati PIXELS_PER_CLOCK ti wa ni tunto si Quad, aago fidio nṣiṣẹ ni 300 MHz lati se atileyin 8Kp30 pixel oṣuwọn (1188/4 = 297 MHz).

2.2. Eto aago
Eto clocking ṣe apejuwe awọn ibugbe aago ni DisplayPort Intel FPGA IP apẹrẹ example.
olusin 7. Intel Agilex F-tile DisplayPort Transceiver clocking eni

Table 4. clocking Ero awọn ifihan agbara

Aago ni aworan atọka	Apejuwe
SysPLL atunṣe	Aago itọkasi F-tile System PLL eyiti o le jẹ igbohunsafẹfẹ aago eyikeyi ti o jẹ pinpin nipasẹ Eto PLL fun igbohunsafẹfẹ iṣelọpọ yẹn. Ninu apẹrẹ yii example, system_pll_clk_link ati rx/tx refclk_link jẹ pinpin SysPLL refclk kanna ti o jẹ 150Mhz. O gbọdọ jẹ aago ṣiṣiṣẹ ọfẹ eyiti o sopọ lati pin aago itọkasi transceiver igbẹhin si ibudo aago titẹ sii ti Itọkasi ati Eto PLL Clocks IP, ṣaaju ki o to so ebute iṣelọpọ ti o baamu si DisplayPort Phy Top.
system_pll_clk_link	Igbohunsafẹfẹ eto PLL ti o kere ju lati ṣe atilẹyin gbogbo oṣuwọn DisplayPort jẹ 320Mhz. Apẹrẹ yii example nlo 900 Mhz (ga julọ) igbohunsafẹfẹ iṣelọpọ ki SysPLL refclk le ṣe pinpin pẹlu rx/tx refclk_link ti o jẹ 150 Mhz.
rx_cdr_refclk_link/tx_pll_refclk_link	Rx CDR ati Tx PLL Link refclk eyiti o wa titi si 150 Mhz lati ṣe atilẹyin gbogbo oṣuwọn data DisplayPort.
rx_ls_clkout/tx Ṣe clkout	Aago Iyara Ọna asopọ DisplayPort si aago DisplayPort IP mojuto. Igbohunsafẹfẹ deede si Ipin Data Oṣuwọn nipasẹ iwọn data ti o jọra. Example: Igbohunsafẹfẹ = data oṣuwọn/data iwọn = 8.1G (HBR3) / 40bits = 202.5 Mhz

2.3. Testbench kikopa
Testbench kikopa simulates DisplayPort TX ni tẹlentẹle loopback to RX.
olusin 8. DisplayPort Intel FPGA IP Simplex Mode Simulation Testbench Block aworan atọka

Table 5. Testbench irinše

Ẹya ara ẹrọ	Apejuwe
Video Àpẹẹrẹ monomono	Olupilẹṣẹ yii ṣe agbejade awọn ilana igi awọ ti o le tunto. O le parameterize awọn akoko kika fidio.
Testbench Iṣakoso	Bulọọki yii n ṣakoso ọna idanwo ti kikopa ati ṣe ipilẹṣẹ awọn ifihan agbara ayun pataki si ipilẹ TX. Bulọọki iṣakoso testbench tun ka iye CRC lati orisun mejeeji ati rii lati ṣe awọn afiwera.
Oluyẹwo Igbohunsafẹfẹ Aago Iyara RX Ọna asopọ	Oluṣayẹwo yii jẹri boya transceiver RX ti o gba igbohunsafẹfẹ aago ibaamu oṣuwọn data ti o fẹ.
TX Link Speed ​​Aago Igbohunsafẹfẹ Checker	Oluyẹwo yii jẹri boya transceiver TX ti o gba igbohunsafẹfẹ aago ibaamu oṣuwọn data ti o fẹ.

Ijẹẹri simulation ṣe awọn iṣeduro wọnyi:
Table 6. Testbench Verifications

Igbeyewo àwárí mu	Ijerisi
• Ikẹkọ Ọna asopọ ni Oṣuwọn Data HBR3 Ka awọn iforukọsilẹ DPCD lati ṣayẹwo boya Ipo DP ṣeto ati wiwọn mejeeji TX ati igbohunsafẹfẹ Iyara Ọna asopọ RX.	Ṣepọ Oluṣayẹwo Igbohunsafẹfẹ lati wiwọn abajade igbohunsafẹfẹ aago iyara Ọna asopọ lati TX ati transceiver RX.
Ṣiṣe apẹẹrẹ fidio lati TX si RX. Ṣayẹwo CRC fun orisun mejeeji ati rii lati ṣayẹwo boya wọn baamu	• Sopọ olupilẹṣẹ apẹẹrẹ fidio si Orisun DisplayPort lati ṣe agbekalẹ ilana fidio. • Iṣakoso Testbench nigbamii ti ka mejeeji Orisun ati Sink CRC lati DPTX ati awọn iforukọsilẹ DPRX ati ṣe afiwe lati rii daju pe awọn iye CRC mejeeji jẹ aami kanna. Akiyesi: Lati rii daju pe a ṣe iṣiro CRC, o gbọdọ muu paramita adaṣe adaṣe Atilẹyin CTS ṣiṣẹ.

Itan Atunyẹwo iwe fun DisplayPort Intel

Agilex F-tile FPGA IP Design Eksample User Itọsọna

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
2021.12.13	21.4	21.0.0	Itusilẹ akọkọ.

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ṣiṣe ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.
* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO 9001: 2015 forukọsilẹ

Idajọ Ayelujara
Fi esi ranṣẹ
UG-20347
ID: 709308
Ẹya: 2021.12.13

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intel DisplayPort Agilex F-Tile FPGA IP Design Eksample [pdf] Itọsọna olumulo DisplayPort Agilex F-Tile FPGA IP Design Example, DisplayPort Agilex, F-Tile FPGA IP Design Eksample, F-Tile FPGA IP Design, FPGA IP Design Eksample, IP Design Example, IP Design, UG-20347, 709308

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