FPGA IP
Zane ExampJagorar Mai Amfani
F-Tile 25G Ethernet Intel®
An sabunta don Intel® Quartus®
Babban Design Suite: 22.3
Shafin IP: 1.0.0

Jagoran Fara Mai Sauri

F-tile 25G Ethernet Intel FPGA IP don na'urorin Intel Agilex™ yana ba da damar haɓaka ƙirar ƙira.amples don zaɓaɓɓun saiti.
Hoto 1. Zane Exampda Amfani

Tsarin Jagora

Hoto 2. 25G Ethernet Intel FPGA IP Design Exampda Tsarin Jagora

• Simulation files (testbench don kwaikwayo kawai) suna cikinample_dir>/ misaliample_testbench.
• Ƙirƙirar-kawai ƙira example is located inample_dir>/ compilation_test_design.
• Tsarin hardware da gwaji files (tsarin example in hardware) suna cikinample_dir>/hardware_test_design.

Tebura 1. Directory da File Bayani

File Sunaye	Bayani
eth_ex_25g.qpf	Intel Quartus® Prime aikin file.
eth_ex_25g.qsf	Saitunan ayyukan Intel Quartus Prime file.
eth_ex_25g.sdc	Ƙuntataccen Ƙira na Synopsys file. Kuna iya kwafa da gyara wannan file don 25GbE Intel FPGA IP core zane.
eth_ex_25g.v	Babban matakin ƙirar Verilog HDL example file. Tsarin tashoshi ɗaya yana amfani da Verilog file.
gama gari/	Hardware zane exampda goyon baya files.
hwtest/main.tcl	Babban file don samun damar System Console.

Samar da Zane Example

Hoto na 4. ExampTab Zane a cikin F-tile 25G Ethernet Intel FPGA IP Parameter Editan

Bi waɗannan matakan don samar da ƙirar kayan masarufi example da testbench:

1. A cikin Intel Quartus Prime Pro Edition, danna File ➤ Sabon Project Wizard don ƙirƙirar sabon aikin Quartus Prime, ko File ➤ Bude Project don buɗe aikin Quartus Prime da ke akwai. Mayen yana tambayarka don saka na'ura.
2. A cikin Catalog na IP, gano wuri kuma zaɓi 25G Ethernet Intel FPGA IP don Agilex. Sabuwar taga Bambancin IP yana bayyana.
3. Saka sunan babban matakin don bambancin IP ɗin ku kuma danna Ok. Editan siga yana ƙara babban matakin .ip file zuwa aikin na yanzu ta atomatik. Idan an sa ka ƙara da .ip file zuwa aikin, danna Project ➤ Ƙara / Cire Files a cikin Project don ƙara da file.
4. A cikin software na Intel Quartus Prime Pro Edition, dole ne ka zaɓi takamaiman na'urar Intel Agilex a cikin filin Na'ura, ko kiyaye tsohuwar na'urar da Intel Quartus Prime software ke bayarwa.
   Lura: Kayan aikin hardware example overwrites zabin da na'urar a kan manufa jirgin. Kuna saka allon manufa daga menu na ƙira exampzažužžukan a cikin Exampda Design tab.
5. Danna Ok. Editan siga ya bayyana.
6. A shafin IP, ƙididdige sigogi don ainihin bambancin IP ɗin ku.
7. A kan Example Design tab, don Exampda Design Files, zaɓi zaɓin Simulation don samar da testbench, kuma zaɓi zaɓi na Synthesis don samar da ƙirar ƙirar kayan aiki.ample. Verilog HDL kawai files suna haifarwa.
   Lura: Ba a samuwa VHDL IP core mai aiki. Ƙayyade Verilog HDL kawai, don ƙirar ainihin IP ɗin kuample.
8. Don Kit ɗin Ci gaban Target, zaɓi Agilex I-jerin Transceiver-SoC Dev Kit
9. Danna Generate Example Design button. Zaɓi ExampTagar Zane Directory ya bayyana.
10. Idan kuna son gyara ƙirar ƙirar examphanyar shugabanci ko suna daga abubuwan da aka nuna (alt_e25_f_0_example_design), bincika zuwa sabuwar hanya kuma rubuta sabon ƙira exampsunan directory (ample_dir>).
11. Danna Ok.

1.2.1. Zane Exampda Parameters
Tebur 2. Ma'auni a cikin Exampda Design Tab

Siga	Bayani
Exampda Design	Akwai exampda zayyana don saitunan sigar IP. Tashoshi ɗaya kawai exampAna tallafawa ƙira don wannan IP.
Exampda Design Files	The files don samarwa don nau'ikan ci gaba daban-daban. • Kwaikwayo-yana haifar da abin da ake bukata files don simulating exampzane. • Ƙirƙiri-yana haifar da kira files. Yi amfani da waɗannan files don tattara ƙira a cikin Intel Quartus Prime Pro software software don gwajin kayan aiki da yin nazarin lokaci mai tsayi.
Ƙirƙira File Tsarin	Tsarin RTL files don kwaikwayo-Verilog.
Zaɓi Board	Kayan aikin tallafi don aiwatar da ƙira. Lokacin da kuka zaɓi kwamitin haɓakawa na Intel FPGA, yi amfani da na'urar AGIB027R31B1E2VRO azaman Na'urar Target don ƙira.ampda tsara. Agilex I-jerin Transceiver-SoC Dev Kit: Wannan zaɓi yana ba ku damar gwada ƙirar ƙiraample a kan zaɓaɓɓen kayan haɓaka IP na Intel FPGA. Wannan zaɓi yana zaɓar Na'urar Target ta atomatik na AGIB027R31B1E2VRO. Idan bita na hukumar yana da nau'in na'ura daban-daban, zaku iya canza na'urar da aka yi niyya. Babu: Wannan zaɓin ya keɓe ɓangarori na hardware don ƙirar ƙirarample.

1.3. Samar da Tile Files

Ƙwararren Ƙwararrun Tallafawa mataki ne na farko da aka yi amfani da shi don samar da abubuwan da suka danganci tayal files da ake buƙata don kwaikwaiyo da ƙirar hardware. Ana buƙatar ƙirar tayal don kowa
F-tile na ƙirar ƙirar ƙira. Dole ne ku kammala wannan matakin kafin simintin.

1. A saurin umarni, kewaya zuwa babban fayil ɗin compilation_test_design a cikin tsohon kuampda design: cd /compilation_test_design.
2. Gudun umarni mai zuwa: quartus_tlg alt_eth_25g

1.4. Yin kwaikwayon F-tile 25G Ethernet Intel FPGA IP Design 
Exampda Testbench
Kuna iya haɗawa da kwaikwayi ƙirar ta hanyar gudanar da rubutun kwaikwayo daga saurin umarni.

1. A saurin umarni, canza testbench simulating directory mai aiki: cdample_dir>/ex_25g/sim.
2. Gudanar da simintin saitin IP:ip-setup-simulation -quartusproject=../../compilation_test_design/alt_eth_25g.qpf

Tebur 3. Matakai don Kwaikwayi Testbench

Na'urar kwaikwayo	Umarni
VCS*	A cikin layin umarni, rubuta sh run_vcs.sh
QuestaSim*	A cikin layin umarni, rubuta vsim -do run_vsim.do -logfile vsim.log Idan kun fi son yin kwaikwayo ba tare da kawo QuestaSim GUI ba, rubuta vsim -c -do run_vsim.do -logfile vsim.log
Cadence -Xcelium*	A cikin layin umarni, rubuta sh run_xcelium.sh

Nasarar kwaikwayo ta ƙare da saƙo mai zuwa:
Anyi Simulators. ko Testbench cikakke.
Bayan nasarar kammalawa, zaku iya tantance sakamakon.
1.5. Ƙirƙirar da Ƙaddamar da Zane Exampa cikin Hardware
Editan madaidaicin madaidaicin 25G Ethernet Intel FPGA IP yana ba ku damar tattarawa da daidaita ƙirar ƙira.ampa kan kayan haɓakawa da aka yi niyya.

Don haɗawa da daidaita ƙirar ƙira exampa kan hardware, bi waɗannan matakan:

1. Kaddamar da Intel Quartus Prime Pro Edition software kuma zaɓi Processing ➤ Fara Tari don haɗa ƙira.
2. Bayan kun ƙirƙiri abin SRAM file .sof, bi waɗannan matakan don tsara kayan ƙirar kayan aikin exampa kan na'urar Intel Agilex:
   a. A cikin Tools menu, danna Programmer.
   b. A cikin Programmer, danna Saitin Hardware.
   c. Zaɓi na'urar shirye-shirye.
   d. Zaɓi kuma ƙara allon Intel Agilex zuwa zaman Intel Quartus Prime Pro Edition ɗin ku.
   e. Tabbatar cewa an saita Yanayin zuwa JTAG.
   f. Zaɓi na'urar Intel Agilex kuma danna Ƙara Na'ura. Mai shirye-shirye yana nunawa
   toshe zane na haɗin kai tsakanin na'urorin da ke kan allo.
   g. A cikin jere tare da sof ɗinku, duba akwatin don .sof.
   h. Duba akwatin da ke cikin ginshiƙin Shirin/Sanya.
   i. Danna Fara.

1.6. Gwajin F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
Bayan kun tattara F-tile 25G Ethernet Intel FPGA IP core design exampda kuma saita shi a kan na'urar Intel Agilex, za ku iya amfani da na'urar Console don tsara ainihin IP.
Don kunna System Console da gwada ƙirar kayan masarufi exampko, bi waɗannan matakan:

1. A cikin Intel Quartus Prime Pro Edition software, zaɓi Kayan aiki ➤ Tsarin
   Kayan aikin gyara kuskure ➤ System Console don ƙaddamar da na'urar wasan bidiyo.
2. A cikin rukunin Tcl Console, rubuta cd hwtest don canza shugabanci zuwa / hardware_test_design/hwtest.
3. Buga tushen main.tcl don buɗe haɗi zuwa JTAG maigida.

Bi tsarin gwaji a sashin Gwajin Hardware na ƙira example kuma duba sakamakon gwajin a cikin System Console.

F-tile 25G Ethernet Design Exampdon Intel Agilex Devices

F-tile 25G Ethernet zane example yana nuna mafita na Ethernet don na'urorin Intel Agilex ta amfani da 25G Ethernet Intel FPGA IP core.
Ƙirƙirar ƙira exampdaga ExampLe Design tab na 25G Ethernet Intel FPGA IP editan siga. Hakanan zaka iya zaɓar don samar da ƙira tare da ko ba tare da shi ba
fasalin Reed-Solomon Forward Correction (RS-FEC).
2.1. Features

• Yana goyan bayan tashar Ethernet guda ɗaya mai aiki a 25G.
• Yana haifar da ƙira examptare da fasalin RS-FEC.
• Yana ba da testbench da rubutun kwaikwayo.
• Yana Haɓaka Maganar Tile F-Tile da Tsarin PLL Agogon Intel FPGA IP dangane da daidaitawar IP.

2.2. Bukatun Hardware da Software
Intel yana amfani da kayan masarufi da software masu zuwa don gwada ƙirar ƙiraampa cikin tsarin Linux:

• Intel Quartus Prime Pro Edition software.
• Siemens* EDA QuestaSim, Synopsys* VCS, da Cadence Xcelium na'urar kwaikwayo.
• Intel Agilex I-jerin Transceiver-SoC Development Kit (AGIB027R31B1E2VRO) don gwajin kayan aiki.

2.3. Bayanin Aiki
F-tile 25G Ethernet zane exampLe ya ƙunshi MAC+ PCS+ PMA core bambance-bambancen. Zane-zane na toshe masu zuwa suna nuna abubuwan ƙira da manyan sigina na babban matakin MAC+ PCS+ PMA core bambance-bambancen a cikin ƙirar F-tile 25G Ethernet ex.ample.
Hoto 5. Toshe zane-F-tile 25G Ethernet Design Example (MAC+PCS+PMA Core Variant)

2.3.1. Abubuwan Zane
Tebur 4. Abubuwan Zane

Bangaren	Bayani
F-tile 25G Ethernet Intel FPGA IP	Ya ƙunshi MAC, PCS, da Transceiver PHY, tare da tsari mai zuwa: • Bambancin Core: MAC+PCS+PMA • Kunna sarrafa kwarara: Na zaɓi • Kunna ƙirƙirar kuskuren hanyar haɗin gwiwa: Na zaɓi • Kunna preamble passthrough: Na zaɓi • Kunna tarin ƙididdiga: Na zaɓi • Kunna ƙididdigar ƙididdigar MAC: Na zaɓi • Mitar agogon maganaku: 156.25 Domin zane examptare da fasalin RS-FEC, an saita ƙarin siga mai zuwa: • Kunna RS-FEC: Na zaɓi
Bayanin F-Tile da Tsarin PLL yana rufe Intel FPGA IP	Bayanin F-Tile da Tsarin PLL yana rufe saitunan madaidaicin madaidaicin Intel FPGA IP daidai da buƙatun F-tile 25G Ethernet Intel FPGA IP. Idan kun samar da zane exampda amfani Ƙirƙirar Exampda Design maɓalli a cikin editan sigar IP, IP ɗin yana nan take ta atomatik. Idan ka ƙirƙiri naka zane exampDon haka, dole ne ku hanzarta wannan IP ɗin da hannu kuma ku haɗa duk tashoshin I/O. Don bayani game da wannan IP, koma zuwa F-Tile Architecture da PMA da FEC Direct PHY IP Jagorar Mai Amfani.
Hankalin abokin ciniki	Ya ƙunshi: • Generator na zirga-zirga, wanda ke haifar da fakitin fashe zuwa 25G Ethernet Intel FPGA IP core don watsawa. • Kula da zirga-zirga, wanda ke sa ido kan fakitin fashe da ke fitowa daga 25G Ethernet Intel FPGA IP core.
Source da Bincike	Sigina na tushe da bincike, gami da siginar sake saitin shigar da tsarin, wanda zaku iya amfani dashi don gyara kuskure.

Bayanai masu alaƙa
F-Tile Architecture da PMA da FEC Direct PHY IP Jagorar Mai Amfani

kwaikwayo

The testbench aika zirga-zirga ta hanyar IP core, motsa jiki da watsa gefe da karɓar gefen IP core.
2.4.1. Testbench
Hoto 6. Toshe zane na F-tile 25G Ethernet Intel FPGA IP Design ExampLe Simulation Testbench

Tebur 5. Abubuwan Gwajin Testbench

Bangaren	Bayani
Na'urar da ake gwadawa (DUT)	25G Ethernet Intel FPGA IP core.
Ethernet Fakiti Generator da Fakiti Monitor	• Fakitin janareta yana haifar da firam kuma aika zuwa DUT. • Fakiti Monitor yana lura da hanyoyin bayanan TX da RX kuma yana nuna firam ɗin a cikin na'urar wasan bidiyo.
Bayanin F-Tile da Tsarin PLL yana rufe Intel FPGA IP	Yana haifar da transceiver da tsarin agogon tunani na PLL.

2.4.2. Tsarin Simulators ExampAbubuwan da aka gyara
Tebur 6. F-tile 25G Ethernet Design Exampda Testbench File Bayani

File Suna	Bayani
Testbench da Simulation Files
Basic_avl_tb_top.v	Babban matakin gwajin benci file. Testbench yana ƙaddamar da DUT, yana aiwatar da tsarin ƙwaƙwalwar ajiya na Avalon® akan abubuwan ƙira da dabaru na abokin ciniki, kuma yana aikawa da karɓar fakiti zuwa ko daga 25G Ethernet Intel FPGA IP.
Rubutun Testbench
ci gaba…

File Suna	Bayani
run_vsim.do	Rubutun ModelSim don gudanar da gwajin benci.
run_vcs.sh	Rubutun Synopsys VCS don gudanar da gwajin benci.
run_xcelium.sh	Rubutun Cadence Xcelium don gudanar da testbench.

2.4.3. Shari'ar Gwaji
Yanayin gwajin simulation yana yin ayyuka masu zuwa:

1. Yana Haɓaka F-tile 25G Ethernet Intel FPGA IP da F-Tile Reference da Tsarin PLL Agogon Intel FPGA IP.
2. Yana jiran agogon RX da siginar halin PHY don daidaitawa.
3. Yana buga halin PHY.
4. Aika da karɓar ingantattun bayanai guda 10.
5. Yana nazarin sakamakon. Gwajin gwajin nasara yana nuna "Testbench cikakke."

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin simulation:

Tari

Bi hanya a cikin Haɗawa da Haɓaka Zane Example in Hardware don haɗawa da daidaita ƙirar ƙirar example a cikin kayan aikin da aka zaɓa.
Kuna iya ƙididdige amfani da albarkatu da Fmax ta amfani da ƙirar ƙira kawaiample. Kuna iya tattara ƙirar ku ta amfani da umarnin Fara Tari akan
Menu na sarrafawa a cikin software na Intel Quartus Prime Pro Edition. Ƙirƙirar nasara tana haifar da taƙaitaccen rahoton tattarawa.
Don ƙarin bayani, koma zuwa Ƙirƙirar Ƙira a cikin Jagorar Mai Amfani da Quartus Prime Pro Edition.
Bayanai masu alaƙa

• Ƙirƙirar da Ƙaddamar da Zane Example in Hardware shafi na 7
• Haɗin ƙira A cikin Jagorar Mai Amfani da Quartus Prime Pro Edition

2.6. Gwajin Hardware
A cikin kayan aikin hardware exampHar ila yau, za ku iya tsara ainihin IP a cikin yanayin madauki na ciki da kuma samar da zirga-zirga a gefen watsawa wanda ke dawowa ta hanyar karɓa.
Bi hanya a hanyar haɗin bayanan da aka bayar don gwada ƙirar ƙiraample a cikin kayan aikin da aka zaɓa.
Bayanai masu alaƙa
Gwajin F-tile 25G Ethernet Intel FPGA IP Hardware Design Example a shafi na 8
2.6.1. Hanyar Gwaji
Bi waɗannan matakan don gwada ƙira exampa cikin hardware:

1. Kafin ka gudanar da gwajin kayan aikin don wannan ƙirar exampto, dole ne ka sake saita tsarin:
   a. Danna Kayan aiki ➤ In-System Sources & Probes Editan kayan aikin don tsoho Source da GUI na bincike.
   b. Juya siginar sake saitin tsarin (Source[3:0]) daga 7 zuwa 8 don amfani da sake saiti kuma mayar da siginar sake saitin tsarin zuwa 7 don sakin tsarin daga yanayin sake saiti.
   c. Kula da siginonin Bincike kuma tabbatar da cewa matsayin yana aiki.
2. A cikin na'ura wasan bidiyo na tsarin, kewaya zuwa babban fayil hwtest kuma gudanar da umarni: main.tcl don zaɓar J.TAG malam. Ta hanyar tsoho, na farko JTAG master a JTAG an zaɓi sarkar. Don zaɓar JTAG babban don na'urorin Intel Agilex, gudanar da wannan umarni: set_jtag <number of appropriate JTAG master>. Example: saita_jtag 1.
3. Gudun umarni masu zuwa a cikin na'ura wasan bidiyo don fara gwajin madauki na serial:

Tebur 7. Ma'auni na umarni

Siga	Bayani	Exampda Amfani
chkphy_status	Yana Nuna mitocin agogo da matsayin kulle PHY.	% chkphy_status 0 # Duba matsayin hanyar haɗin gwiwa 0
chkmac_stats	Yana nuna ƙima a cikin ƙididdigar ƙididdigar MAC.	% chkmac_stats 0 # Yana duba mashin statistics na mahaɗin 0
share_duk_stats	Yana share masu ƙididdige ƙididdiga na IP.	% clear_all_stats 0 # Yana share kididdigar hanyar haɗin yanar gizo 0
fara_jin	Fara janareta fakiti.	% start_gen 0 # Fara samar da fakiti akan mahaɗin 0
tsaya_gen	Yana tsayar da janareta na fakiti.	% stop_gen 0 # Dakatar samar da fakiti akan hanyar haɗin gwiwa 0
madauki	Yana kunna madauki serial na ciki.	% loop_on 0 # Kunna lapback na ciki akan mahaɗin 0
madauki	Yana kashe madauki na ciki serial.	% loop_off 0 # Kashe lapback na ciki akan mahaɗin 0
reg_karatu	Yana dawo da ƙimar rajistar ainihin IP a .	% reg_read 0x402 # Karanta rajistar IP CSR a adireshin 402 na hanyar haɗin 0
reg_rubutu	Ya rubuta zuwa IP core rajista a adireshin .	% reg_write 0x401 0x1 # Rubuta 0x1 zuwa IP CSR rajistar rajista a adireshin 401 na hanyar haɗin 0

a. Rubuta loop_on don kunna yanayin dawowar serial na ciki.
b. Rubuta chkphy_status don duba matsayin PHY. Matsayin TXCLK, RXCLK, da RX yakamata su kasance suna da ƙima iri ɗaya da aka nuna a ƙasa don ingantaccen hanyar haɗin gwiwa:

c. Buga clear_all_stats don share rajistar kididdigar TX da RX.
d. Rubuta start_gen don fara samar da fakiti.
e. Nau'in stop_gen don dakatar da samar da fakiti.
f. Buga chkmac_stats don karanta ƙididdigar ƙididdiga ta TX da RX. Tabbatar cewa:
i. Fakitin fakitin da aka watsa sun dace da firam ɗin fakitin da aka karɓa.
ii. Ba a karɓi firam ɗin kuskure ba.
g. Buga loop_off don kashe madauki serial na ciki.
Hoto na 7. SampSakamakon Gwaji-TX da RX Statistics Counters

Tarihin Bita na Takardu don F-tile 25G Ethernet FPGA IP Design ExampJagorar Mai Amfani

Sigar Takardu	Intel Quartus Prime Version	Sigar IP	Canje-canje
2022.10.14	22.3	1.0.0	Sakin farko.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
ISO
9001:2015
Rajista

Online Version
Aika da martani
Saukewa: 750200
Shafin: 2022.10.14

Takardu / Albarkatu

intel F-Tile 25G Ethernet FPGA IP Design Example [pdf] Jagorar mai amfani F-Tile 25G Ethernet FPGA IP Design Example, F-Tile 25G, F-Tile 25G Ethernet FPGA, FPGA IP Design Example, IP Design Exampku, 750200

Magana

• Manual mai amfani