F-Tile DisplayPort FPGA IP Design Example
Isikhokelo somsebenzisi
F-Tile DisplayPort FPGA IP Design Example
Ihlaziywe kwi-Intel® Quartus® Prime Design Suite: 22.2 IP Version: 21.0.1
DisplayPort Intel FPGA IP Design Example Quick Start Guide
Izixhobo zeDisplayPort Intel® F-tile zibandakanya ibhentshi yokulinganisa yokulinganisa kunye noyilo lwehardware exhasa ukuhlanganiswa kunye novavanyo lwehardware FPGA IP yoyilo ex.ampiiLes ze-Intel Agilex™
IDisplayPort Intel FPGA IP ibonelela ngoyilo lulandelayo exampngaphantsi:
- I-DisplayPort SST parallel loopback ngaphandle kwemodyuli yePixel Clock yoBuyiselo (PCR).
- I-DisplayPort SST parallel loopback ene-AXIS Video Interface
Xa uvelisa i-ex yoyiloampLe, umhleli weparameter yenza ngokuzenzekelayo i files iyimfuneko ukulinganisa, ukuqulunqa, kunye nokuvavanya uyilo kwihardware.
Umfanekiso 1. Uphuhliso Stages
Ulwazi olunxulumeneyo
- DisplayPort Intel FPGA IP User Guide
- Ukufudukela kwi-Intel Quartus Prime Pro Edition
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo.
*Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
ISO 9001:2015 ibhalisiwe
1.1. Ulwakhiwo lukavimba weefayili
Umzobo 2. Ulwakhiwo lukavimba weefayili
Uluhlu 1. Uyilo Eksample Components
| Iifolda | Files |
| rtl/core | dp_core.ip |
| dp_rx. ip | |
| dp_tx. ip | |
| rtl/rx_phy | dp_gxb_rx/ ((ibhloko yesakhiwo seDP PMA UX) |
| dp_rx_data_fifo. ip | |
| rx_top_phy . sv | |
| rtl/tx_phy | dp_gxb_rx/ ((ibhloko yesakhiwo seDP PMA UX) |
| dp_tx_data_fifo.ip | |
| dp_tx_data_fifo.ip |
1.2. IiMfuno zeHardware kunye neSoftware
I-Intel isebenzisa i-hardware elandelayo kunye nesofthiwe yokuvavanya i-design example:
Hardware
- Intel Agilex I-Series Development Kit
- I-DisplayPort Source GPU
- Isinki yeDisplayPort (Monitor)
- Bitec DisplayPort FMC intombi ikhadi Revision 8C
- Iintambo zeDisplayPort
Isoftware
- Intel Quartus® Prime
- I-Synopsy* Isifanisi seVCS
1.3. Ukuvelisa uYilo
Sebenzisa iDisplayPort Intel FPGA IP parameter umhleli kwi-Intel Quartus Prime software ukuvelisa uyilo example.
Umzobo 3. Ukuvelisa i-Design Flow
- Khetha iZixhobo ➤ Ikhathalogu ye-IP, kwaye ukhethe i-Intel Agilex F-tile njengesixhobo sosapho ekujoliswe kuso.
Phawula: Uyilo example ixhasa kuphela izixhobo ze-Intel Agilex F-tile. - KwiKhathalogi ye-IP, fumana kwaye ucofe kabini i-DisplayPort Intel FPGA IP. Iwindow entsha yoKwahluka kwe-IP iyavela.
- Chaza igama elikwinqanaba eliphezulu lokwahluka kwe-IP yakho. Umhleli weparameter ugcina useto loguqulo lwe IP kwi file igama .ip.
- Khetha isixhobo se-Intel Agilex F-tile kwintsimi yeSixhobo, okanye ugcine i-Intel Quartus Prime ekhethiweyo yesixhobo sesoftware.
- Cofa u-Kulungile. Umhleli weparameter uyavela.
- Qwalasela iiparamitha ezifunekayo kuzo zombini i-TX kunye ne-RX.
- Phantsi koYilo Eksampkwi-tab, khetha i-DisplayPort SST Parallel Loopback Ngaphandle kwePCR.
- Khetha Ukulinganisa ukuvelisa ibhentshi yovavanyo, kwaye ukhethe uHlaziyo ukuvelisa uyilo lwehardware example. Kufuneka ukhethe enye kwezi iinketho ukuvelisa uyilo example files. Ukuba ukhetha zombini, ixesha lesizukulwana liba lide.
- KwiKhiti yoPhuhliso ekujoliswe kuyo, khetha i-Intel Agilex I-Series ye-SOC yoPhuhliso lweKit. Oku kubangela ukuba isixhobo ekujoliswe kuso esikhethiweyo kwinyathelo lesi-4 ukutshintsha ukutshatisa isixhobo kwikhithi yophuhliso. Kwi-Intel Agilex I-Series SOC Development Kit, isixhobo esingagqibekanga yi-AGIB027R31B1E2VR0.
- Cofa uVelisa Example Design.
1.4. Ukulinganisa Uyilo
Uyilo lweDisplayPort Intel FPGA IP example testbench ilinganisa uyilo lwe-loopback olulandelelanayo ukusuka kumzekelo we-TX ukuya kumzekelo we-RX. Imodyuli yangaphakathi yokuvelisa ipateni yevidiyo iqhuba umzekelo weDisplayPort TX kunye nemveliso yevidiyo ye-RX idibanisa nabahloli be-CRC kwi-testbench.
Umzobo 4. Ukuhamba kokulinganisa uYilo
- Yiya kwi-Synopsys simulator ifolda kwaye ukhethe i-VCS.
- Qhuba ukulinganisa okushicilelweyo.
Umthombo vcs_sim.sh - Iskripthi senza i-Quartus TLG, iqulunqa kwaye iqhube i-testbench kwi-simulator.
- Hlalutya umphumo.
Ukulinganisa okuyimpumelelo kuphetha ngoMthombo kunye neSink SRC uthelekiso.
1.5. Ukuqulunqa kunye noVavanyo loYilo
Umzobo 5. Ukuqulunqa kunye nokulinganisa uYilo
Ukuqokelela kunye nokuqhuba uvavanyo lokubonisa kwi-hardware exampkuyilo, landela la manyathelo:
- Qinisekisa i-hardware example mveliso yoyilo igqityiwe.
- Qalisa isoftware ye-Intel Quartus Prime Pro Edition kwaye uvule / quartus/agi_dp_demo.qpf.
- Cofa Ukusetyenzwa ➤ Qalisa Ukuhlanganisa.
- Emva kokuhlanganiswa ngempumelelo, isoftware ye-Intel Quartus Prime Pro Edition yenza i-.sof file kulawulo lwakho oluchaziweyo.
- Qhagamshela iDisplayPort RX isinxibelelanisi kwikhadi lentombi leBitec kumthombo wangaphandle weDisplayPort, njengekhadi lemizobo kwiPC.
- Qhagamshela iDisplayPort TX isinxibelelanisi kwikhadi lentombi le-Bitec kwisixhobo sokuntywila seDisplayPort, njenge-analyzer yevidiyo okanye i-PC monitor.
- Qinisekisa ukuba zonke iiswitshi kwibhodi yophuhliso zikwimeko emiselweyo.
- Qwalasela isixhobo esikhethiweyo se-Intel Agilex F-Tile kwibhodi yophuhliso usebenzisa eyenziwe .sof file (Izixhobo ➤ uMcwangcisi ).
- Isixhobo sokutshona seDisplayPort sibonisa ividiyo eveliswe kumthombo wevidiyo.
Ulwazi olunxulumeneyo
Intel Agilex I-Series FPGA Development Kit Isikhokelo somsebenzisi/
1.5.1. Ukuhlaziya i-ELF File
Ngokungagqibekanga, iELF file uveliswa xa uvelisa uyilo oluguquguqukayo example.
Nangona kunjalo, kwezinye iimeko, kufuneka uhlaziye i-ELF file ukuba uguqula isoftware file okanye yenza ngokutsha i-dp_core.qsys file. Ukuhlaziya i-dp_core.qsys file ihlaziya i .sopcinfo file, efuna ukuba uhlaziye kwakhona i-ELF file.
- Yiya e /isoftware kwaye uhlele ikhowudi ukuba kuyimfuneko.
- Yiya e /iskripthi kwaye uphumeze iskripthi sokwakha esilandelayo: umthombo build_sw.sh
• Kwi-Windows, khangela kwaye uvule i-Nios II Command Shell. Kwi-Nios II Command Shell, yiya ku /script kwaye uphumeze umthombo build_sw.sh.
Phawula: Ukwenza iskripthi sokwakha Windows 10, inkqubo yakho ifuna i-Windows Subsystems ye-Linux (WSL). Ngolwazi oluthe vetshe malunga namanyathelo ofakelo lwe-WSL, bhekisa kwi-Nios II Software Developer Handbook.
• Kwi-Linux, sungula uMyili weQonga, kwaye uvule iziXhobo ➤ I-Nios II Command Shell. Kwi-Nios II Command Shell, yiya ku /script kwaye uphumeze umthombo build_sw.sh. - Qinisekisa i.elf file iveliswa kwi /software/ dp_demo.
- Khuphela eyenziwe .elf file kwi FPGA ngaphandle kokubuyisela i .sof file ngokwenza okushicilelweyo kulandelayo: nios2-khuphela /software/dp_demo/*.elf
- Cofa iqhosha lokuseta kwakhona kwibhodi yeFPGA ukuze isoftwe entsha isebenze.
1.6. DisplayPort Intel FPGA IP Design Example Parameters
Itheyibhile 2. DisplayPort Intel FPGA IP Design Example QSF isithintelo kwi-Intel Agilex Ftile Isixhobo
| QSF uMnyanzelo |
Inkcazo |
| set_global_assignment -igama VERILOG_MACRO "__DISPLAYPORT_inkxaso__=1" |
Ukususela kwi-Quartus 22.2 ukuya phambili, esi sithintelo se-QSF siyafuneka ukwenza i-DisplayPort yesiko SRC (Soft Reset Controller) ihambe. |
Itheyibhile 3. DisplayPort Intel FPGA IP Design Example Parameters for Intel Agilex F-tile Isixhobo
| Ipharamitha | Ixabiso | Inkcazo |
| Uyilo olukhoyo Eksample | ||
| Khetha uyilo | •Akukho nanye •DisplayPort SST Parallel Loopback ngaphandle kwePCR •DisplayPort SST Parallel Loopback ene-AXIS Video Interface |
Khetha uyilo example izakwenziwa. •Akukho: Akukho mzekelo woyiloample ikhona kukhetho lwangoku lweparameter. •I-DisplayPort SST Parallel Loopback ngaphandle kwePCR: Olu luyilo example ibonisa i-loopback enxuseneyo ukusuka kwisinki yeDisplayPort ukuya kumthombo weDisplayPort ngaphandle kwemodyuli yePixel Clock yoBuyiselo (PCR) xa ulayita iFayimitha yeFayimitha yoFakelo loNgeniso lweVidiyo. •DisplayPort SST Parallel Loopback with AXIS Video Interface: Olu luyilo example ibonisa i-loopback ehambelanayo ukusuka kwisinki ye-DisplayPort ukuya kumthombo we-DisplayPort nge-interface yeVidiyo ye-AXIS xa uVumela iiProtokholi zeDatha yeVidiyo eSebenzayo isetelwe kwi-AXIS-VVP epheleleyo. |
| Uyilo Eksample Files | ||
| Ukulinganisa | Layita icima | Layita olu khetho ukwenza okuyimfuneko files yokulinganisa testbench. |
| Ukudibanisa | Layita icima | Layita olu khetho ukwenza okuyimfuneko files for Intel Quartus Prime ukuhlanganiswa kunye noyilo hardware. |
| Yenziwe ifomathi yeHDL | ||
| Veza File Ifomathi | Verilog, VHDL | Khetha ifomathi oyikhethayo yeHDL yoyilo olwenziweyo example fileiseti. Qaphela: Olu khetho lumisela kuphela ifomathi yomgangatho ophezulu we IP owenziweyo files. Zonke ezinye files (umz. umzample testbenches kunye nenqanaba eliphezulu files yomboniso wehardware) zikwifomati yeVerilog HDL. |
| Ikhithi yoPhuhliso ekujoliswe kuyo | ||
| Khetha iBhodi | •Akukho Khipha yoPhuhliso •Intel Agilex I-Series Ikhithi yoPhuhliso |
Khetha ibhodi yoyilo ekujoliswe kulo example. |
| Ipharamitha | Ixabiso | Inkcazo |
| •Akukho Khithi yoPhuhliso: Olu khetho alubandakanyi yonke imiba yehardware yoyilo example. Undoqo we-P umisela zonke izabelo ze-pin kwizikhonkwane zenyani. •I-Intel Agilex I-Series FPGA Development Kit: Olu khetho lukhetha ngokuzenzekelayo isixhobo ekujoliswe kuso kwiprojekthi ukutshatisa isixhobo kule kit yophuhliso. Ungatshintsha isixhobo ekujoliswe kuso usebenzisa Guqula iDivayisi ekujoliswe kuyo iparamitha ukuba uhlaziyo lwebhodi yakho inomahluko wesixhobo esahlukileyo. I-IP engundoqo ibeka zonke izabelo ze-pin ngokwekhithi yophuhliso. Qaphela: Uyilo lwangaphambili ExampLe ayiqinisekiswanga ngokusebenza kwihardware kolukhupho lweQuartus. •Custom Development Kit: Olu khetho luvumela uyilo example iya kuvavanywa kwikhithi yophuhliso lomntu wesithathu kunye ne-Intel FPGA. Kusenokufuneka usete izabelo zepin uwedwa. |
||
| Isixhobo ekujoliswe kuso | ||
| Guqula isixhobo ekuJoliswe kuso | Layita icima | Layita olu khetho kwaye ukhethe uhlobo olukhethiweyo lwesixhobo sophuhliso lwekhithi. |
Uyilo oluDityanisiweyo lweLoopback ExampLes
Uyilo lweDisplayPort Intel FPGA IP exampLes bonisa i-parallel loopback ukusuka kumzekelo weDisplayPort RX ukuya kumzekelo weDisplayPort TX ngaphandle kwemodyuli yePixel yoBuyiselo lweClock (PCR).
Itheyibhile 4. DisplayPort Intel FPGA IP Design Example for Intel Agilex F-tile Isixhobo
| Uyilo Eksample | Ukutyunjwa | Data Rate | Indlela yesiteshi | Uhlobo lweLoopback |
| I-DisplayPort SST parallel loopback ngaphandle kwePCR | I-DisplayPort SST | I-RBR, i-HRB, i-HRB2, i-HBR3 | Simplex | IParallel ngaphandle kwePCR |
| I-DisplayPort SST parallel loopback ene-AXIS Video Interface | I-DisplayPort SST | I-RBR, i-HRB, i-HRB2, i-HBR3 | Simplex | Ngokuhambelana ne-AXIS Video Interface |
2.1. Intel Agilex F-ithayile DisplayPort SST Parallel Loopback Design Iimbonakalo
Uyilo lwe-loopback ye-SST ehambelanayo exampOku kubonisa ukuhanjiswa kwevidiyo enye ukusuka kwisinki yeDisplayPort ukuya kumthombo weDisplayPort.
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
ISO 9001:2015 ibhalisiwe
Umzobo 6. Intel Agilex F-tile DisplayPort SST Parallel Loopback ngaphandle PCR
- Kolu tshintsho, iparamitha yomthombo weDisplayPort, TX_SUPPORT_IM_ENABLE, ivuliwe kwaye ujongano lomfanekiso wevidiyo luyasetyenziswa.
- Isinki seDisplayPort sifumana ividiyo kunye okanye ukusasazwa kweaudio kumthombo wevidiyo wangaphandle onje ngeGPU kwaye iyibeke kwi-interface yevidiyo ehambelanayo.
- Imveliso yevidiyo yeDisplayPort iqhubela ngokuthe ngqo ujongano lwevidiyo yomthombo weDisplayPort kunye neekhowudi kwikhonkco eliphambili leDisplayPort ngaphambi kokuba idluliselwe esweni.
- I-IOPLL iqhuba zombini isinki yeDisplayPort kunye neewotshi zevidiyo zomthombo ngamaxesha amiselweyo.
- Ukuba iDisplayPort isinki kunye nomthombo we-MAX_LINK_RATE iparameter ibunjwe ukuba ibe yi-HBR3 kunye ne-PIXELS_PER_CLOCK iqwalaselwe ukuya kwi-Quad, iwotshi yevidiyo ibaleka ku-300 MHz ukuxhasa i-8Kp30 ye-pixel rate (1188/4 = 297 MHz).
Umfanekiso 7. Intel Agilex F-tile DisplayPort SST Parallel Loopback nge AXIS Video Ujongano
- Kulo mahluko, umthombo weDisplayPort kunye neparameter ye-sink, khetha i-AXIS-VVP FULL kwi-ENable ACTIVE VIDEO DATA PROTOCOLS ukwenzela ukuba i-Axis Video Interface isebenze.
- Isinki seDisplayPort sifumana ividiyo kunye okanye ukusasazwa kweaudio kumthombo wevidiyo wangaphandle onje ngeGPU kwaye iyibeke kwi-interface yevidiyo ehambelanayo.
- I-DisplayPort Sink iguqula umlambo wedatha yevidiyo kwidatha yevidiyo ye-axis kwaye iqhube i-DisplayPort umthombo we-axis ujongano lwedatha yedatha ngeVVP Video Frame Buffer. Umthombo weDisplayPort uguqula idatha yevidiyo ye-axis kwikhonkco eliphambili leDisplayPort ngaphambi kokuba idluliselwe kwimonitha.
- Kolu lwahluka loyilo, kukho iiwotshi ezintathu eziphambili zevidiyo, ezizezi rx/tx_axi4s_clk, rx_vid_clk, kunye tx_vid_clk. I-axi4s_clk isebenza kwi-300 MHz kuzo zombini iimodyuli ze-AXIS kuMthombo kunye neSinki. rx_vid_clk runsDP Sink Video pipeline at 300 MHz (ukuxhasa nasiphi na isisombululo ukuya kuthi ga kwi-8Kp30 4PIPs), ngelixa i-tx_vid_clk iqhuba umbhobho wevidiyo we-DP Source kwi-Pixel Clock frequency (eyahlulwe zii-PIPs).
- Olu lwahluka loyilo oluzenzekelayo luqwalasela i-tx_vid_clk frequency ngokusebenzisa inkqubo ye-I2C kwibhodi ye-SI5391B OSC xa uyilo lubhaqa iswitshi kwisisombululo.
- Olu lwahluka loyilo lubonisa kuphela inani elimiselweyo lezisombululo njengoko kuchaziwe ngaphambili kwisoftware yeDisplayPort, ethi:
— 720p60, RGB
— 1080p60, RGB
— 4K30, RGB
— 4K60, RGB
2.2. iClock Scheme
Iskimu sewotshi sibonisa imimandla yewotshi kwiDisplayPort Intel FPGA IP yoyilo example.
Umzobo 8. I-Intel Agilex F-tile ye-DisplayPort Transceiver clocking scheme
Itheyibhile 5. Iimpawu zeSkimu sokuValela
| Iwotshi kumzobo |
Inkcazo |
| I-SysPLL irefclk | Iwotshi yereferensi yeNkqubo ye-F-tile ye-PLL enokuba yiyo nayiphi na ifrikhwensi yewotshi eyahlulwahlulwa yiNkqubo ye-PLL yaloo maza aphumayo. Kulo mzekelo woyiloample, inkqubo_pll_clk_link kunye rx/tx refclk_link ukwabelana efanayo 150 MHz SysPLL refclk. |
| Iwotshi kumzobo | Inkcazo |
| Kufuneka ibe yiwotshi esebenza simahla edityaniswe kwiqhosha lewotshi yesalathisi ezinikeleyo ukuya kwizibuko lewotshi yegalelo le-Reference kunye neNkqubo ye-PLL Iiwotshi ze-IP, ngaphambi kokudibanisa i-port ephumayo ehambelanayo ne-DisplayPort Phy Top. Qaphela: Kuyilo mzekeloample, qwalasela iClock Controller GUI Si5391A OUT6 ukuya kwi-150 MHz. |
|
| inkqubo pll clk ikhonkco | Ubuncinci benkqubo yePLL yokuphuma rhoqo ukuxhasa yonke ireyithi yeDisplayPort yi-320 MHz. Lo mzekelo woyiloample isebenzisa i-900 MHz (ephezulu) i-frequency yemveliso ukuze i-SysPLL refclk ibe nokwabelana nge-rx/tx refclk_link eyi-150 MHz. |
| rx_cdr_refclk_link / tx_pll_refclk_link | I-Rx CDR kunye ne-Tx PLL Link refclk elungiswe kwi-150 MHz ukuxhasa yonke ireyithi yedatha ye-DisplayPort. |
| rx_ls_clkout / tx_ls_clkout | I-DisplayPort Link Isantya sewotshi kwiwotshi ye-DisplayPort engundoqo we-IP. Amaxesha alingana neRayithi yeDatha yahlula ngobubanzi bedatha obunxuseneyo. Example: Ubuninzi = izinga ledatha / ububanzi bedatha = 8.1G (HBR3) / 40 bits = 202.5 MHz |
2.3. Ukulinganisa Testbench
I-testbench yokulinganisa ilinganisa i-DisplayPort TX ye-serial loopback kwi-RX.
Umzobo 9. I-DisplayPort Intel FPGA IP ye-Simplex Mode yokulinganisa i-Testbench Block Diagram
Itheyibhile 6. Izixhobo zeTestbench
| Icandelo | Inkcazo |
| Ijenereyitha yeepateni zeVidiyo | Le jenereyitha ivelisa iipatheni zebha yombala onokuthi uyiqwalasele. Unokwenza iparameterize yefomathi yexesha levidiyo. |
| Ulawulo lweTestbench | Le bhloko ilawula ukulandelelana kovavanyo lokulinganisa kwaye ivelise iimpawu ezifunekayo zokuvuselela kwi-core TX. Ibhloko yokulawula i-testbench iphinda ifunde ixabiso le-CRC ukusuka kwimithombo yomibini kunye ne-sink ukwenza uthelekiso. |
| RX Link Isantya Clock Clock umhloli | Lo mkhangeli uyaqinisekisa ukuba i-RX transceiver efunyenweyo iwashi iyahambelana na nesantya sedatha esifunwayo. |
| TX Link Isantya Clock Clock umhloli | Lo mkhangeli uqinisekisa ukuba i-TX transceiver efunyenweyo iphinda-phinda ihambelana nesantya sedatha esifunwayo. |
I-testbench yokulinganisa yenza ezi zingqinisiso zilandelayo:
Uluhlu loku-7. Testbench Verifications
| Iikhrayitheriya zoVavanyo |
Ukuqinisekisa |
| • Qhagamshelana noQeqesho kwiNqanaba leDatha HBR3 • Funda iirejista ze-DPCD ukujonga ukuba i-DP Status iseti kwaye ilinganisa zombini i-TX kunye ne-RX Link Speed frequency. |
Idibanisa i-Frequency Checker ukulinganisa iSayithi seNqanaba imveliso yewotshi evela kwi-TX kunye ne-RX transceiver. |
| • Sebenzisa ipateni yevidiyo ukusuka ku-TX ukuya kwi-RX. • Qinisekisa i-CRC kuzo zombini umthombo kunye nesinki ukujonga ukuba ziyahambelana na |
• Dibanisa ipateni yevidiyo kwiMthombo weDisplayPort ukuvelisa ipateni yevidiyo. • Ulawulo lwe-Testbench ngokulandelayo lufunda zombini i-Source kunye ne-Sink CRC esuka kwi-DPTX kunye neerejista ze-DPRX kwaye zithelekise ukuqinisekisa ukuba zombini ixabiso le-CRC liyafana. Qaphela: Ukuqinisekisa ukuba i-CRC ibalwa, kufuneka uvule i-parameter yovavanyo oluzenzekelayo lwe-CTS. |
Imbali yoHlaziyo yoXwebhu lwe-F-Tile DisplayPort Intel FPGA IP Design Example Isikhokelo somsebenzisi
| Inguqulelo yoXwebhu | Intel Quartus Prime Version | IP Version | Iinguqu |
| 2022.09.02 | 22. | 20.0.1 | •Utshintshe isihloko soxwebhu ukusuka kwiDisplayPort Intel Agilex F-Tile FPGA IP Design Example Isikhokelo soMsebenzisi kwi-F-Tile DisplayPort Intel FPGA IP Design Example Isikhokelo somsebenzisi. •Uyilo lweVidiyo ye-AXIS esebenzayo Example eyahlukileyo. •Ilususile uyilo lweNkalo eNcinci kwaye endaweni yalo kwafakwa uMfanekiso weSiyilelo esiNinziample. •Isusiwe inowuthi kwiDisplayPort Intel FPGA IP Design Example Isikhokelo sokuQala esiKhawulezayo esithi i-Intel Quartus Prime 21.4 inguqulelo yesoftware ixhasa kuphela uYilo lwangaphambili Examples. •Kufakwe inani elichanekileyo endaweni yeSakhiwo sikavimba weefayili. •Yongeza icandelo Ukuhlaziya i-ELF File phantsi koKuqulunqa nokuVavanya uYilo. •Kuhlaziywe icandelo leHardware kunye neeMfuno zeSoftware ukuze liquke izixhobo ezongezelelweyo iimfuno. |
| 2021.12.13 | 21. | 20.0.0 | Ukukhutshwa kokuqala. |
Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo.
*Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.
ISO 9001:2015 ibhalisiwe
Version Online
Ukuzisa impendulo
UG-20347
I-ID: 709308
Inguqulelo: 2022.09.02
Amaxwebhu / Izibonelelo
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intel F-Tile DisplayPort FPGA IP Design Example [pdf] Isikhokelo somsebenzisi F-Tile DisplayPort FPGA IP Design Example, F-Tile DisplayPort, DisplayPort, FPGA IP Design Example, IP Design Example, UG-20347, 709308 |
