MICROCHIP RTG4 Addendum RTG4 FPGAs Board Design and Layout Guidelines
Folasaga
O lenei faʻaopoopoga i le AC439: Faʻatonu a le Komiti Faʻatonu ma Taʻiala mo le RTG4 FPGA Application Note, o loʻo tuʻuina atu ai faʻamatalaga faʻaopoopo, e faʻamamafa ai o le DDR3 taʻiala e tutusa le umi o loʻo lolomiina i le toe iloiloga 9 poʻo mulimuli ane e faʻamuamua i luga o le faʻatulagaina o le laupapa o loʻo faʻaaogaina mo le RTG4™ kit atinaʻe. I le taimi muamua, o le RTG4 development kit sa na'o le Inisinia Silicon (ES). Ina ua maeʻa le faʻasalalauga muamua, na mulimuli ane faʻatumu le pusa i tulaga masani (STD) ma le -1 saoasaoa vasega RTG4 masini gaosiga. Numera vaega, RTG4-DEV-KIT ma RTG4-DEV-KIT-1 o lo'o sau fa'atasi ma le STD saosaoa vasega ma -1 saosaoa vasega masini.
E le gata i lea, o lenei faʻaopoopoga o loʻo aofia ai faʻamatalaga i luga o le masini I / O amio mo le tele o faʻasologa o le eletise ma le paʻu, faʻapea foʻi ma le, DEVRST_N faʻamaonia i le taimi masani.
Iloiloga o le RTG4-DEV-KIT DDR3 Fa'atonu Fa'atonu
- RTG4 atina'e pusa fa'atinoina se fa'amatalaga 32-bit ma le 4-bit ECC DDR3 fa'afeso'ota'i mo ta'itasi o le RTG4 FDDR fa'atonu ma poloka PHY (FDDR Sasa'e ma Sisifo). O le atina'e o lo'o fa'atulagaina fa'aletino e lima fa'amaumauga paita laina.
- O le pusa e mulimuli i le lele e ala i le faʻaogaina o auala e pei ona faʻamatalaina i le DDR3 Layout Guidelines vaega o AC439: Board Design and Layout Guidelines mo RTG4 FPGA Application Note. Ae ui i lea, talu ai o lenei pusa atinaʻe na mamanuina aʻo leʻi lolomiina le tusi talosaga, e le ogatusa ma taʻiala faʻafetaui umi faʻafouina o loʻo faʻamatalaina i le tusi talosaga. I le DDR3 faʻamatalaga, o loʻo i ai se +/- 750 ps tapulaa i luga o le skew i le va o faamatalaga strobe (DQS) ma DDR3 uati (CK) i masini manatua DDR3 taitasi i le taimi o se fefaʻatauaiga tusitusi (DSS).
- Pe a mulimulitaʻia le umi o taʻiala i le AC439 toe iloilo 9 poʻo le mulimuli ane o le tusi talosaga, o le RTG4 laupapa faʻatulagaina o le a fetaui ma le tDQSS tapulaʻa mo mea uma e lua -1 ma STD i le faagasologa atoa, vol.tagu, ma le vevela (PVT) fa'aogaina le tele o lo'o lagolagoina e masini gaosiga RTG4. E fa'ataunu'uina lea e ala i le fa'avasegaina o le fa'aletonu pito sili ona leaga i le va o le DQS ma le CK i pine RTG4. Aemaise lava, pe a faʻaaogaina le
fausia-RTG4 FDDR pule faaopoopo PHY, o le DQS taʻitaʻia CK e 370 ps maualuga mo le -1 masini vasega saoasaoa ma DQS Taʻitaʻia CK e 447 ps maualuga mo se masini STD saosaoa vasega, i tulaga sili ona leaga. - Faʻavae i luga o le auʻiliʻiliga o loʻo faʻaalia i le Laulau 1-1, o le RTG4-DEV-KIT-1 e faʻafeiloaʻi tapulaʻa tDQSS i masini manatua taʻitasi, i tulaga sili ona leaga mo le RTG4 FDDR. Ae ui i lea, e pei ona faʻaalia i le Laulau 1-2, o le RTG4-DEV-KIT faʻatulagaina, faʻatumuina i masini STD speed grade RTG4, e le fetaui ma le tDQSS mo le fa ma le lima masini manatua i luga o le topology lele, i tulaga sili ona leaga o le faʻaogaina. mo le RTG4 FDDR. I se tulaga lautele, o le RTG4-DEV-KIT o loʻo faʻaaogaina i tulaga masani, e pei o le vevela o le potu i totonu o se siosiomaga fale faigaluega. O le mea lea, o lenei suʻesuʻega sili ona leaga e le faʻaogaina i le RTG4-DEV-KIT faʻaaogaina i tulaga masani. O le auʻiliʻiliga e fai ma faʻataʻitaʻigaampLe o le mafuaaga e taua ai le mulimuli i le DDR3 le umi e tutusa taʻiala o loʻo lisiina i le AC439, ina ia faʻafeiloaʻi se mamanu laupapa faʻaoga tDQSS mo se talosaga vaalele.
- Ina ia faʻamalamalama atili i lenei example, ma faʻaalia pe faʻafefea ona totogi ma le lima mo se faʻatulagaina o le RTG4 laupapa e le mafai ona ausia le AC439 DDR3 taʻiala umi, o le RTG4-DEV-KIT faʻatasi ma masini STD speed grade e mafai lava ona faʻafetaui le tDQSS i masini manatua taʻitasi, i tulaga sili ona leaga, aua o le RTG4 FDDR pule fa'aopoopo fa'atasi ma le PHY o lo'o iai le malosi e fa'atuai ai le fa'ailoga DQS i le laina paita fa'amatalaga. E mafai ona fa'aogaina lenei suiga fa'aletonu e fa'aitiitia ai le skew i le va o le DQS ma le CK i se masini manatua e iai le tDQSS> 750 ps. Va'ai le vaega o A'oa'oga DRAM, i le UG0573: RTG4 FPGA High Speed DDR Interfaces User Guide mo nisi fa'amatalaga e uiga i le fa'aogaina o fa'atonuga fa'atuai tuai (i le resitala REG_PHY_WR_DQS_SLAVE_RATIO) mo DQS i le taimi o se fefa'atauaiga tusitusi. O lenei fa'atuai tau e mafai ona fa'aoga i le Libero® SoC pe'ā fa'apipi'i se fa'atonu FDDR fa'atasi ai ma le fa'amatagofieina otometi e ala i le suia o le fa'asologa o le CoreABC FDDR fa'asologa fa'a-autometi. E mafai ona fa'aoga se faiga fa'apena i se fa'atulagaina o laupapa fa'aoga e le fetaui ma tDQSS i masini manatua ta'itasi.
Laulau 1-1. Iloiloga o le RTG4-DEV-KIT-1 tDQSS Fa'atatauga mo -1 Vaega ma le FDDR1 Feso'ota'iga
| Ala Iloiloina | Umi ole Uati (mils) | Fa'atuai le Fa'asalalauina o le Uati (ps) | Umi o Fa'amatalaga (mils) | Fa'asalalau Fa'amatalaga n
Fa'atuai (ps) |
Eseesega ile CLKDQS
ona o le Fa'asologa (mils) |
tDQSS i manatuaga uma, pe a uma le laupapa skew+FPGA DQSCLK
skew (ps) |
| FPGA-1st Memory | 2578 | 412.48 | 2196 | 351.36 | 61.12 | 431.12 |
| FPGA-2nd Memory | 3107 | 497.12 | 1936 | 309.76 | 187.36 | 557.36 |
| FPGA-3rd Memory | 3634 | 581.44 | 2231 | 356.96 | 224.48 | 594.48 |
| FPGA-4th Memory | 4163 | 666.08 | 2084 | 333.44 | 332.64 | 702.64 |
| FPGA-5th Memory | 4749 | 759.84 | 2848 | 455.68 | 304.16 | 674.16 |
Manatua: I tulaga sili ona leaga, RTG4 FDDR DDR3 DQS-CLK skew mo -1 masini e 370 ps maualuga ma 242 ps laʻititi.
Laulau 1-2. Iloiloga o le RTG4-DEV-KIT tDQSS Fa'atatauga mo Vaega STD ma le FDDR1 Feso'ota'iga
| Ala Iloiloina | Umi ole Uati (mils) | Fa'atuai le Fa'asalalauina o Uati
(ps) |
Umi o Fa'amatalaga (mils) | Fa'asalalauga ma Fa'atuai (ps) | Eseesega ile CLKDQS
ona o le Fa'asologa (mils) |
tDQSS i manatuaga uma, pe a uma le laupapa skew+FPGA DQSCLK
skew (ps) |
| FPGA-1st Memory | 2578 | 412.48 | 2196 | 351.36 | 61.12 | 508.12 |
| FPGA-2nd Memory | 3107 | 497.12 | 1936 | 309.76 | 187.36 | 634.36 |
| FPGA-3rd Memory | 3634 | 581.44 | 2231 | 356.96 | 224.48 | 671.48 |
| FPGA-4th Memory | 4163 | 666.08 | 2084 | 333.44 | 332.64 | 779.64 |
| FPGA-5th Memory | 4749 | 759.84 | 2848 | 455.68 | 304.16 | 751.16 |
Fa'aaliga: I tulaga sili ona leaga, RTG4 FDDR DDR3 DQS-CLK skew mo STD masini e 447 ps maualuga ma 302 ps laʻititi.
Manatua: Fa'atatau mo le tuai o fa'asalalauga a le Komiti e 160 ps/inisi sa fa'aogaina i lenei au'ili'iligaample mo faʻamatalaga. Ole tuai ole fa'asalalauina ole laupapa mose laupapa fa'aoga e fa'alagolago ile laupapa fa'apitoa o lo'o su'esu'eina.
Fa'asologa o Malosiaga
O lenei faʻaopoopoga ile AC439: Faʻatonu a le Komiti Faʻatonu ma Taʻiala mo le RTG4 FPGA Application Note, e tuʻuina atu ai faʻamatalaga faaopoopo, e faʻamamafa ai le taua tele e mulimulitaʻi i le Board Design Guidelines. Ia mautinoa o loʻo mulimulitaʻia taʻiala e faʻatatau i le Malosi i luga ma le Malosi i lalo.
Malosiaga
O le siata o lo'o i lalo o lo'o lisiina ai tulaga fa'aoga fa'aola fa'apipi'i ma a latou ta'iala e fa'atatau i le fa'aoso i luga.
Laulau 2-1. Ta'iala Fa'aola
| Fa'aoga Tulaga | Fa'asologa Manaomia | Amioga | Fa'amatalaga |
| DEVRST_N
Fa'ailoa i le taimi e fa'aola ai le eletise, se'ia o'o uma sapalai eletise RTG4 i tulaga fa'atonu |
Leai se ramp-o'o maualuga mana'omia. Sapalai ramp-i luga e tatau ona oso i luga monotonically. | O le taimi lava e oʻo atu ai le VDD ma le VPP i le faʻagaoioia o faʻailoga (VDD ~= 0.55V, VPP ~= 2.2V) ma
DEVRST_N ua tatala mai, o le POR Delay Counter o le a tamoe mo ~ 40ms masani (50ms max), ona fa'aogaina lea o le masini e fa'atino ai le fa'aogaina o ata 11 ma 12 (DEVRST_N PUFT) o System Controller User's Guide (UG0576). I se isi faaupuga, o lenei faasologa e 40 ms + 1.72036 ms (masani) mai le tulaga DEVRST_N ua tatalaina. Manatua ole fa'aoga mulimuli ole DEVRST_N e le fa'atali le POR fa'atau e fa'atino ai le mana i galuega fa'atino ma o lea fa'asologa e na'o le 1.72036 ms (masani). |
I le mamanu, o galuega faatino o le a le atoatoa (ie opeopea) a'o fa'aola le eletise. A uma loa le fa'atau POR
ua maea, DEVRST_N ua tatalaina ma VDDI I/O sapalai uma ua taunuu i latou ~ 0.6V paepae, ona fa'atigaina lea o le I/Os ma fa'agaoioia le toso a'e vaivai, se'ia o'o ina fa'asolo atu galuega i le fa'atonutonuina o tagata, i Ata 11 ma le 12 o le UG0576. O galuega taua e tatau ona tumau i lalo i le taimi o le eletise e manaʻomia ai se faʻalavelave toso i lalo 1K-ohm. |
| DEVRST_N
toso i luga i le VPP ma sapalai uma ramp i luga pe tusa o le taimi lava e tasi |
VDDPLL e le tatau ona avea ma
fa'ai'u mana-sapalai i ramp i luga, ma e tatau ona ausia le pito maualalo fautuaina voltage a'o le'i tuuina atu le sapalai mulimuli (VDD poʻo le VDDI) amata rampi luga e taofia ai le lokaina o le PLL fa'aletonu. Va'ai ile RTG4 Clocking Resources User Guide (UG0586) mo se fa'amatalaga ile fa'aogaina ole CCC/PLL READY_VDDPLL fa'aoga e aveese ai le fa'asologa o mana'oga mo le VDDPLL sapalai eletise. Po'o le nonoa SERDES_x_Lyz_VDDAIO i le sapalai tutusa ma le VDD, pe fa'amautinoa latou te fa'aola i le taimi e tasi. |
O le taimi lava e oʻo atu ai le VDD ma le VPP i le faʻagaoioia o faʻailoga (VDD ~= 0.55V, VPP ~= 2.2V) le
50 ms POR tuai fa'ata'ita'i o le a tamo'e. O le malosi o le masini e o'o i le taimi fa'atino e fa'atumauina Ata 9 ma le 10 (VDD PUFT) o le System Controller User's Guide (UG0576). I se isi faaupuga, o le taimi atoa e 57.95636 ms. |
I le mamanu, o galuega faatino o le a le atoatoa (ie opeopea) a'o fa'aola le eletise. A uma loa le fa'atau POR
ua mae'a, ua fa'amalolo DEVRST_N ma ua taunuu uma sapalai VDDI IO i latou ~ 0.6V paepae, ona fa'atigaina lea o le I/Os ma fa'agaoioia le toso a'e vaivai, se'ia o'o ina fa'asolo atu galuega i le fa'atonutonuina o tagata, i Ata 9 ma le 10 o le UG0576. O galuega taua e tatau ona tumau i lalo i le taimi o le eletise e manaʻomia ai se faʻalavelave toso i lalo 1K-ohm. |
| Fa'aoga Tulaga | Fa'asologa Manaomia | Amioga | Fa'amatalaga |
| VDD/ SERDES_VD DAIO -> VPP/VDDPLL
-> |
Fa'asologa o lo'o lisiina i le Scenario Column.
DEVRST_N ua toso i luga i le VPP. |
O le taimi lava e oʻo ai le VDD ma le VPP i le faʻagaoioia o faʻailoga (VDD ~ = 0.55V, VPP ~ = 2.2V) le 50ms
O le a tamo'e le fa'ata tuai o le POR. O le malosi o le masini e o'o i le taimi fa'atino e fa'atatau i Fa'atusa 9 ma le 10 (VDD PUFT) o System Controller User's Guide (UG0576). O le fa'amae'aina o le fa'asologa o le eletise ma le fa'aola i luga i le taimi fa'atino e fa'atatau i le sapalai VDDI mulimuli o lo'o fa'aola. |
I le mamanu, o galuega faatino o le a le atoatoa (ie opeopea) a'o fa'aola le eletise. A uma loa le fa'atau POR
ua maea, DEVRST_N ua tatalaina ma VDDI I/O sapalai uma ua taunuu i latou ~ 0.6V paepae, ona fa'atigaina lea o le IO ma fa'agaoioi le toso a'e vaivai, se'ia o'o i le suiga o galuega i le fa'atonutonuina o tagata, i Ata 9 ma le 10 o le UG0576. Leai se vaivai toso i luga faagaioiga i le taimi o le power-up seia oo uma VDDI sapalai ~ 0.6V. Le manuia autu o lenei fa'asologa o le sapalai VDDI mulimuli lea e o'o atu o le a le fa'agaoioia le toso a'e vaivai ma o le a suia sa'o mai le fa'aletonu i le fa'aogaina o le fa'aogaina. O lenei mea e mafai ona fesoasoani e faʻaititia le numera o fafo 1K toso i lalo tetee e manaʻomia mo mamanu o loʻo i ai le tele o faletupe I / O faʻamalosia e le VDDI mulimuli e tulaʻi mai. Mo isi faletupe I/O uma e fa'amalosia e so'o se VDDI sapalai e ese mai i le VDDI sapalai mulimuli e fa'atupula'ia, o galuega taua e tatau ona tumau maualalo i le taimi o le eletise e mana'omia ai le 1K-ohm toso i lalo tetee. |
| Faatali pe a ma le 51ms -> | |||
| VDDI (All IO
faletupe) |
|||
| OR | |||
| VDD/ SERDES_VD DAIO -> | |||
| VPP/ VDDPLL/ 3.3V_VDDI -> | |||
| Faatali pe a ma le 51ms -> | |||
| VDDI
(le-3.3V_VD DI) |
Iloiloga ile DEVRST_N Assertion ma Power-Down
Afai AC439: Fuafuaga a le Komiti Fa'atonu ma Ta'iala Fa'atulagaina mo RTG4 FPGA Ta'iala Fa'amatalaga e le o mulimulitaia fa'amolemole toeview fa'amatalaga nei:
- Mo le fa'asologa o le paoa ua tu'uina atu i le Laulau 2-2, e mafai e le tagata fa'aoga ona va'ai I/O glitches po'o le fa'atosina ma le tumau o mea tutupu i le taimi nei.
- E pei ona taʻua i le Customer Advisory Notification (CAN) 19002.5, o se ese mai le faʻasologa o le eletise o loʻo fautuaina i le RTG4 datasheet e mafai ona faʻaosoina ai se taimi le tumau i luga o le 1.2V VDD sapalai. Afai o le 3.3V VPP sapalai o ramped i lalo i luma o le 1.2V VDD sapalai, o se taimi le tumau i luga o le VDD o le a matauina e pei o le VPP ma le DEVRST_N (powered by VPP) oʻo i le 1.0V. E le tupu lenei taimi le tumau pe a fa'aumatia VPP mulimuli, e tusa ai ma le fa'amatalaga o fa'amaumauga.
- O le tele ma le umi o le taimi nei e faʻalagolago i le mamanu ua faʻatulagaina i le FPGA, faʻapitoa faʻapipiʻi faʻapipiʻi capacitance, ma le tali le tumau o le vol 1.2V.tage fa'atonu. I tulaga e le masani ai, o se taimi le tumau e oʻo atu i le 25A (poʻo le 30 Watts i luga o le 1.2V VDD sapalai) ua matauina. Ona o le tufatufaina atu o lenei VDD o loʻo i ai nei i luga o le ie FPGA atoa (e le o faʻaogaina i se vaega patino), ma lona taimi puupuu, e leai se popolega faʻalagolago pe a fai o le mana-paʻu le tumau e 25A pe itiiti.
- I le avea ai o se faiga fa'ata'ita'iga sili ona lelei, mulimuli i le fa'atonuga o fa'amaumauga e aloese ai mai le taimi nei.
- I/O glitches atonu e tusa ma le 1.7V mo le 1.2 ms.
- E mafai ona matauina le tele o faaletonu i mea e ave ai le Low po'o le Tristate.
- Fa'aletonu maualalo i mea fa'atino e fa'ata'avale E mafai ona maitauina le maualuga (e le mafai ona fa'aitiitia le fa'aletonu i le fa'aopoopoina o le toso i lalo ole 1 KΩ).
- O le fa'amalo i lalo o le VDDIx muamua e fa'atagaina ai le suiga mai le High i le Low, ae fa'atopetope le fa'atinoina o galuega e ono a'afia ai se laupapa fa'aoga o lo'o taumafai e toso maualuga le gaosiga pe a pa'u i lalo le RTG4 VDDIx. O le RTG4 e mana'omia le I/O Pads e le fa'aoso i fafo i luga a'e o le VDDix bank supply voltagma o le mea lea afai e faʻaopoopoina se faʻalavelave i fafo i se isi laina eletise, e tatau ona paʻu i lalo faʻatasi ma le VDDIx sapalai.
Laulau 2-2. Fa'aaliga Fa'aletonu I/O pe a le mulimulita'ia le Fa'atonuga Fa'atonuga Fa'alalo i lalo ile AC439.Tulaga Fa'atosina Fa'atino VDD (1.2V) VDDIx (<3.3V) VDDIx (3.3V) VPP (3.3V) DEVRST_N Amio Malosi i lalo I/O Fa'alavelave I- Rush i le taimi nei I/O Avetaavale Maulalo pe Tristated Ramp lalo pe a uma le VPP i soʻo se faʻatonuga Ramp i lalo muamua Nonoa ile VPP Ioe1 Ioe Ramp i lalo i soʻo se faʻatonuga pe a uma le DEVRST_N faʻamaonia Fa'ailoa atu a'o le'i fa'asoaina ramp lalo Ioe1 Leai I/O Avetaavale Maualuga Ramp lalo pe a uma le VPP i soʻo se faʻatonuga Ramp i lalo muamua Nonoa ile VPP Ioe Ioe Ramp i lalo i soʻo se faʻatonuga i luma ole VPP Ramp lalo mulimuli Nonoa ile VPP Leai2 Leai Ramp i lalo i soʻo se faʻatonuga pe a uma le DEVRST_N faʻamaonia Fa'ailoa atu a'o le'i fa'asoaina ramp lalo Ioe Leai - O le 1 KΩ toso i lalo tetee fafo e fautuaina e faaitiitia ai le maualuga glitch i le taua I/Os, lea e tatau ona tumau maualalo i le taimi o le eletise.
- O se faaletonu maualalo e na'o se I/O e toso ese mai fafo i se sapalai eletise e tumau pea le malosi e pei o le VPP ramps lalo. Ae ui i lea, o se soliga lea o tulaga fa'aoga fautuaina mai masini talu ai e le tatau ona maualuga le PAD pe a uma le VDDIx r tutusa.amps lalo.
- Afai e fa'amaonia DEVRST_N, e mafai e le tagata fa'aoga ona va'ai i se fa'aletonu maualalo i so'o se gaioiga I/O o lo'o maualuga le ta'avale ma fa'apea fo'i ona tosoina mai fafo e ala i se fa'asaga i le VDDI. Mo example, faatasi ai ma se 1KΩ toso-i luga tetee, se glitch maualalo oo atu i se vol itiititage o le 0.4V ma le umi o le 200 ns e mafai ona tupu a'o le'i togafitia le gaosiga.
Manatua: DEVRST_N e le tatau ona toso i luga a'e o le VPP voltagu. Ina ia aloese mai mea o loʻo i luga e matua fautuaina lava e mulimuli i le faʻaogaina o le eletise ma le faʻaogaina o le eletise o loʻo faʻamatalaina i le AC439: Faʻatonu a le Komiti Faʻatonu ma Taʻiala mo le RTG4 FPGA Application Note.
Toe Iloilo Tala'aga
O le tala fa'asolopito o lo'o fa'amatalaina suiga na fa'atinoina i le pepa. O suiga o lo'o lisiina e ala i toe iloiloga, amata i le lomiga o lo'o iai nei.
Laulau 3-1. Toe Iloilo Tala'aga
| Toe Iloiloga | Aso | Fa'amatalaga |
| A | 04/2022 | • A'o fai le DEVRST_N, o RTG4 I/Os uma o le a fa'asalaina. O mea e fa'aoso maualuga e le ie FPGA ma toso maualuga i fafo i luga o le laupapa e ono maua se fa'aletonu maualalo a'o le'i o'o i le tulaga tristate. E tatau ona su'esu'eina se mamanu laupapa e iai se fa'aaliga fa'apea ina ia malamalama i le a'afiaga o feso'ota'iga i galuega fa'atino a le FPGA e ono fa'alavelave pe a fa'ailoa DEVRST_N. Mo nisi fa'amatalaga, tagai i le Laasaga 5 ile vaega
2.2. Iloiloga ile DEVRST_N Assertion ma Power-Down. • Toe faaigoa Malosi-I lalo i le vaega 2.2. Iloiloga ile DEVRST_N Assertion ma Power-Down. • Suia i le mamanu Microchip. |
| 2 | 02/2022 | • Faaopoopo le vaega Power-Up.
• Fa'aopoopoina le vaega Fa'asologa o Malosiaga. |
| 1 | 07/2019 | Le lomiga muamua o lenei pepa. |
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- Mai Amerika i Matu, valaau 800.262.1060
- le lalolagi atoa, valaau 650.318.4460
- Fax, mai so'o se mea i le lalolagi, 650.318.8044
Le Microchip Webnofoaga
Microchip e maua le lagolago i luga ole laiga e ala i la matou webnofoaga i www.microchip.com/. Lenei web'upega tafa'ilagi e fa'aoga e fai ai files ma fa'amatalaga faigofie ona maua e tagata fa'atau. O nisi o mea e maua e aofia ai:
- Lagolago oloa - Pepa faʻamatalaga ma mea sese, faʻamatalaga talosaga ma samppolokalame, punaoa mamanu, ta'iala a le tagata fa'aoga ma pepa lagolago mo meafaigaluega, fa'asalalauga fou fa'akomepiuta ma polokalama fa'amaumauga
- Lagolago Fa'atekinisi Lautele - Fesili e masani ona fesiligia (FAQs), talosaga lagolago faʻapitoa, vaega faʻatalanoaga i luga ole laiga, Microchip design paaga polokalame lisi sui auai
- Pisinisi a Microchip - Filifilia oloa ma taʻiala faʻatonu, faʻasalalauga lata mai a Microchip, lisi o semina ma mea tutupu, lisi o ofisa faʻatau Microchip, tufatufaina ma sui fale gaosi oloa
Au'aunaga Fa'asilasilaga Suiga o Mea
O le auaunaga fa'asilasilaga suiga o oloa a Microchip e fesoasoani e fa'amautu ai tagata fa'atau i oloa Microchip. O le a maua e le au fai saofaga le faʻamatalaga imeli i soʻo se taimi e iai suiga, faʻafouga, toe teuteuga poʻo mea sese e fesoʻotaʻi ma se aiga o oloa faʻapitoa poʻo meafaigaluega atinaʻe e fiafia i ai.
Ina ia lesitala, alu i www.microchip.com/pcn ma mulimuli i faatonuga o le resitalaina.
Lagolago Tagata Fa'atau
O tagata fa'aoga o oloa Microchip e mafai ona maua fesoasoani e ala i le tele o auala:
- Fa'asoa po'o le Sui
- Ofisa Fa'atauga Fa'alotoifale
- Embedded Solutions Engineer (ESE)
- Lagolago Fa'atekinisi
E tatau i tagata fa'atau ona fa'afeso'ota'i le latou tufatufaina, sui po'o le ESE mo le lagolago. O loʻo avanoa foʻi ofisa faʻatau i le lotoifale e fesoasoani i tagata faʻatau. O lo'o iai se lisi o ofisa fa'atau ma nofoaga i totonu o lenei pepa.
E maua le lagolago fa'apitoa e ala ile webnofoaga i: www.microchip.com/support
Fa'ailoga Puipuiga o Fa'ailoga Fa'atonu a Microchip
Manatua faʻamatalaga o loʻo i lalo o le faʻaogaina o le puipuiga o tulafono i luga o oloa Microchip:
- O oloa Microchip e fetaui ma faʻamatalaga o loʻo i totonu o la latou Pepa Faʻamatalaga Microchip.
- E talitonu Microchip o lona aiga o oloa e saogalemu pe a faʻaaogaina i le auala faʻamoemoeina, i totonu o faʻamatalaga faʻaogaina, ma i lalo o tulaga masani.
- Microchip fa'atauaina ma puipuia fa'amalosi ana aia tatau tau meatotino. O taumafaiga e soli le tulafono o le puipuiga o le oloa Microchip e matua fa'asaina ma e ono solia ai le Digital Millennium Copyright Act.
- E le mafai e le Microchip poʻo se isi mea gaosi semiconductor ona faʻamaonia le saogalemu o lana tulafono. O le puipuiga o tulafono laiti e le o lona uiga tatou te faʻamautinoa o le oloa e "le mafai ona motusia". O le puipuiga o tulafono laiti o lo'o fa'asolosolo pea. Microchip ua tuuto atu i le faʻaauauina pea o le faʻaleleia atili o uiga puipuia o tulafono a tatou oloa.
Faasilasilaga Faaletulafono
- O lenei lomiga ma faʻamatalaga o loʻo i totonu e mafai ona faʻaaogaina i oloa Microchip, e aofia ai le mamanu, suʻega, ma tuʻufaʻatasia oloa Microchip ma lau talosaga. O le fa'aogaina o nei fa'amatalaga i so'o se isi lava faiga e solia ai nei aiaiga. O fa'amatalaga e uiga i fa'aoga masini e tu'uina atu mo na'o lou fa'amalieina ma e ono suia
e fa'afouga. O lau matafaioi le faʻamautinoa o lau talosaga e fetaui ma au faʻamatalaga. Fa'afeso'ota'i lou ofisa fa'atau Microchip fa'apitonu'u mo se lagolago fa'aopoopo pe, maua se lagolago fa'aopoopo ile www.microchip.com/en-us/support/design-help/client-support-services. - O LENEI FAʻAMATALAGA E TUUINA E MICROCHIP "AS IS". E LEAI FAIA e le MICROCHIP ni sui po'o se fa'amaoniga o so'o se ituaiga pe fa'aalia pe fa'aa'i, tusitusia pe tu'ugutu, tulāfono
POO ISI, E FAI I FA'AMATALAGA E AOFIA AI AE LE FAATAPUA I SO'O SE FA'AALIGA FA'AALIGA O LE LE'I SULIAGA, FA'AFO'A'I, MA FA'A'OGA MO SE FA'AMATALAGA, PO'O WARRANTY E FASA'I I ONA TU'UGA, UIGA, PO'O LE FA'AIGA. - E LEAI SE MEA E TATAU AI MICROCHIP MO SO'O SE FA'AMATALAGA, FA'AMATALAGA, FA'ASA'OGA, FA'AMATALAGA, PO'O LE FA'A'ALI'AGA MA'U'U, FA'AFIA, TAU, PO'O LE TU'U'UINA O SO'O SE I'UGA SO'O SE FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA, PE'O LE MEA NA FA'AUPUNA'I, E tusa lava pe fa'aletonu. FA'ATONU POO LE FA'AFIA E FA'AVAEINA. I LE AGATOGA FA'AALIGA E LE TULAFONO, O LE UMA AOFA'IGA A MICROCHIP I TOTOGI UMA I SO'O SE AUALA E FA'AIGA I LE FA'AMATALAGA POO LONA FA'A'OGA E LE'A LOLOA I LE TOTOGI O TOTOGI, AFAI E IAI, NA E TOTOGI SA'O I LE MICROCHIP MO LE FA'AMATALAGA.
O le fa'aogaina o masini Microchip i le tausiga o le ola ma/po'o le saogalemu o lo'o i le tulaga lamatia o le tagata fa'atau, ma e malie le tagata fa'atau e puipuia, fa'aleaga ma taofia Microchip le afaina mai so'o se mea leaga, tagi, suti, po'o tupe alu e mafua mai i lea fa'aoga. E leai ni laisene e tu'uina atu, fa'aalia po'o se isi mea, i lalo o so'o se Microchip aia tatau tau le atamai se'i vagana ua ta'ua.
Fa'ailoga Fa'ailoga
- Le igoa Microchip ma le logo, le Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash , Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, ma XMEGA o fa'ailoga fa'amaufa'ailoga a Microchip Technology Incorporated i Amerika ma isi atunu'u.
- AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, ma ZL o faʻailoga resitalaina o Microchip Technology Incorporated i Amerika.
- Taofi Fa'aigoa Fa'atasi, AKS, Analog-for-the-Digital Age, So'o se Capacitor, So'o se In, So'oOut, Suiga Fa'aopoopo, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching , ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Parallel, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Faʻamaonia logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE , Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Endurance Aofa'i, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, ma le ZENA o fa'ailoga fa'ailoga a Microchip Technology Incorporated i le
ISA ma isi atunuu. - O le SQTP o se faailoga tautua a Microchip Technology Incorporated i Amerika O le logo Adaptec, Frequency on Demand, Silicon Storage Technology, Symmcom, ma le Trusted Time o faʻailoga faʻamaufaʻailoga a Microchip Technology Inc. i isi atunuu.
- GestIC ose fa'ailoga fa'amaufa'ailoga a Microchip Technology Germany II GmbH & Co. KG, ose lala o Microchip Technology Inc., i isi atunu'u.
O isi fa'ailoga tau fefa'ataua'iga uma o lo'o ta'ua ii o meatotino a latou kamupani.
© 2022, Microchip Technology Incorporated ma ona lala. Ua Taofia Aia Tatau Uma.
ISBN: 978-1-6683-0362-7
Faiga Fa'atonuga
Mo faʻamatalaga e uiga i Microchip's Quality Management Systems, faʻamolemole asiasi www.microchip.com/quality.
Fa'atauga ma Au'aunaga i le Lalolagi Atoa
| AMERIKA | ASIA/ PASIFIK | ASIA/ PASIFIK | Europa |
| Ofisa Autasi
2355 Sisifo Chandler Blvd. Chandler, AZ 85224-6199 Telefoni: 480-792-7200 Fax: 480-792-7277 Lagolago Fa'atekinisi: www.microchip.com/support Web tuatusi: www.microchip.com Atlanta Duluth, GA Telefoni: 678-957-9614 Fax: 678-957-1455 Austin, TX Telefoni: 512-257-3370 Boston Westborough, MA Telefoni: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Telefoni: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Telefoni: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Telefoni: 248-848-4000 Houston, TX Telefoni: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Telefoni: 317-536-2380 Los Angeles Mission Viejo, CA Telefoni: 949-462-9523 Fax: 949-462-9608 Telefoni: 951-273-7800 Raleigh, NC Telefoni: 919-844-7510 Niu Ioka, NY Telefoni: 631-435-6000 San Jose, CA Telefoni: 408-735-9110 Telefoni: 408-436-4270 Kanata - Toronto Telefoni: 905-695-1980 Fax: 905-695-2078 |
Ausetalia – Sini
Telefoni: 61-2-9868-6733 Saina - Beijing Telefoni: 86-10-8569-7000 Saina – Chengdu Telefoni: 86-28-8665-5511 Saina – Chongqing Telefoni: 86-23-8980-9588 Saina – Dongguan Telefoni: 86-769-8702-9880 Saina – Guangzhou Telefoni: 86-20-8755-8029 Saina – Hangzhou Telefoni: 86-571-8792-8115 Saina - Hong Kong SAR Telefoni: 852-2943-5100 Saina – Nanjing Telefoni: 86-25-8473-2460 Saina – Qingdao Telefoni: 86-532-8502-7355 Saina – Shanghai Telefoni: 86-21-3326-8000 Saina – Shenyang Telefoni: 86-24-2334-2829 Saina – Shenzhen Telefoni: 86-755-8864-2200 Saina – Suzhou Telefoni: 86-186-6233-1526 Saina - Wuhan Telefoni: 86-27-5980-5300 Saina – Xian Telefoni: 86-29-8833-7252 Saina – Xiamen Telefoni: 86-592-2388138 Saina – Zhuhai Telefoni: 86-756-3210040 |
Initia – Bangalore
Telefoni: 91-80-3090-4444 Initia – New Delhi Telefoni: 91-11-4160-8631 Initia - Pune Telefoni: 91-20-4121-0141 Iapani - Osaka Telefoni: 81-6-6152-7160 Iapani - Tokyo Telefoni: 81-3-6880-3770 Korea – Daegu Telefoni: 82-53-744-4301 Korea – Seoul Telefoni: 82-2-554-7200 Meleisia – Kuala Lumpur Telefoni: 60-3-7651-7906 Meleisia – Penang Telefoni: 60-4-227-8870 Filipaina – Manila Telefoni: 63-2-634-9065 Singapore Telefoni: 65-6334-8870 Taiuani – Hsin Chu Telefoni: 886-3-577-8366 Taiuani – Kaohsiung Telefoni: 886-7-213-7830 Taiuani – Taipei Telefoni: 886-2-2508-8600 Taialani – Bangkok Telefoni: 66-2-694-1351 Vietnam – Ho Chi Minh Telefoni: 84-28-5448-2100 |
Ausetalia – Uelese
Telefoni: 43-7242-2244-39 Fax: 43-7242-2244-393 Tenimaka – Copenhagen Telefoni: 45-4485-5910 Fax: 45-4485-2829 Finelani – Espoo Telefoni: 358-9-4520-820 Farani – Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Siamani – Garching Telefoni: 49-8931-9700 Siamani – Haan Telefoni: 49-2129-3766400 Siamani – Heilbronn Telefoni: 49-7131-72400 Siamani – Karlsruhe Telefoni: 49-721-625370 Siamani – Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Siamani – Rosenheim Telefoni: 49-8031-354-560 Isaraelu – Ra’anana Telefoni: 972-9-744-7705 Italia – Milan Telefoni: 39-0331-742611 Fax: 39-0331-466781 Italia – Padova Telefoni: 39-049-7625286 Netherlands – Drunen Telefoni: 31-416-690399 Fax: 31-416-690340 Nouei – Trondheim Telefoni: 47-72884388 Polani – Warsaw Telefoni: 48-22-3325737 Romania – Bucharest Tel: 40-21-407-87-50 Sepania - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Suetena – Gothenberg Tel: 46-31-704-60-40 Suetena - Stockholm Telefoni: 46-8-5090-4654 Peretania - Wokingham Telefoni: 44-118-921-5800 Fax: 44-118-921-5820 |
© 2022 Microchip Technology Inc. ma ona lala
Pepa / Punaoa
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MICROCHIP RTG4 Addendum RTG4 FPGAs Board Design and Layout Guidelines [pdf] Taiala mo Tagata Fa'aoga RTG4 Addendum RTG4 FPGAs Board Design and Layout Guidelines, RTG4, Addendum RTG4 FPGAs Board Design and Layout Guidelines, Design and Layout Guidelines |
